[U-Boot,01/10] spi: sun4i: Poll for rxfifo empty

Message ID 20190209131500.29954-2-jagan@amarulasolutions.com
State Changes Requested
Delegated to: Jagannadha Sutradharudu Teki
Headers show
Series
  • spi: Add Allwinner A31 SPI driver
Related show

Commit Message

Jagan Teki Feb. 9, 2019, 1:14 p.m.
To drain rx fifo the fifo need to poll till the fifo
count become empty.

The current code is using wait_for_bit logic on control
register with exchange burst mode mask, which is not a
proper way of waiting for draining fifo.

So, add code for polling fifo status register till rxfifo
count become empty.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/spi/sun4i_spi.c | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

Comments

André Przywara Feb. 13, 2019, 1:11 a.m. | #1
On Sat,  9 Feb 2019 18:44:51 +0530
Jagan Teki <jagan@amarulasolutions.com> wrote:

Hi,

> To drain rx fifo the fifo need to poll till the fifo
> count become empty.
> 
> The current code is using wait_for_bit logic on control
> register with exchange burst mode mask, which is not a
> proper way of waiting for draining fifo.
> 
> So, add code for polling fifo status register till rxfifo
> count become empty.
> 
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
>  drivers/spi/sun4i_spi.c | 15 +++++++++------
>  1 file changed, 9 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/spi/sun4i_spi.c b/drivers/spi/sun4i_spi.c
> index 38cc743c61..87b396a96e 100644
> --- a/drivers/spi/sun4i_spi.c
> +++ b/drivers/spi/sun4i_spi.c
> @@ -31,6 +31,8 @@
>  
>  #include <asm/arch/clock.h>
>  
> +#include <linux/iopoll.h>
> +
>  #define SUN4I_FIFO_DEPTH	64
>  
>  #define SUN4I_RXDATA_REG	0x00
> @@ -46,7 +48,6 @@
>  #define SUN4I_CTL_LMTF			BIT(6)
>  #define SUN4I_CTL_TF_RST		BIT(8)
>  #define SUN4I_CTL_RF_RST		BIT(9)
> -#define SUN4I_CTL_XCH_MASK		0x0400
>  #define SUN4I_CTL_XCH			BIT(10)
>  #define SUN4I_CTL_CS_MASK		0x3000
>  #define SUN4I_CTL_CS(cs)		(((cs) << 12) & SUN4I_CTL_CS_MASK)
> @@ -308,7 +309,7 @@ static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen,
>  	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
>  
>  	u32 len = bitlen / 8;
> -	u32 reg;
> +	u32 reg, rx_fifocnt;
>  	u8 nbytes;
>  	int ret;
>  
> @@ -343,10 +344,12 @@ static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen,
>  		reg = readl(&priv->regs->ctl);
>  		writel(reg | SUN4I_CTL_XCH, &priv->regs->ctl);
>  
> -		/* Wait transfer to complete */
> -		ret = wait_for_bit_le32(&priv->regs->ctl, SUN4I_CTL_XCH_MASK,
> -					false, SUN4I_SPI_TIMEOUT_US, false);
> -		if (ret) {
> +		/* Wait till RX FIFO to be empty */
> +		ret = readl_poll_timeout(&priv->regs->ctl, rx_fifocnt,

That's not the right register, it should be regs->fifo_sta.

> +					 !(((rx_fifocnt & SUN4I_FIFO_STA_RF_CNT_MASK) >>
> +					 SUN4I_FIFO_STA_RF_CNT_BITS) < nbytes),

I think removing the negation and using ">=" instead is less confusing.

Cheers,
Andre.


> +					 SUN4I_SPI_TIMEOUT_US);
> +		if (ret < 0) {
>  			printf("ERROR: sun4i_spi: Timeout transferring data\n");
>  			sun4i_spi_set_cs(bus, slave_plat->cs, false);
>  			return ret;

Patch

diff --git a/drivers/spi/sun4i_spi.c b/drivers/spi/sun4i_spi.c
index 38cc743c61..87b396a96e 100644
--- a/drivers/spi/sun4i_spi.c
+++ b/drivers/spi/sun4i_spi.c
@@ -31,6 +31,8 @@ 
 
 #include <asm/arch/clock.h>
 
+#include <linux/iopoll.h>
+
 #define SUN4I_FIFO_DEPTH	64
 
 #define SUN4I_RXDATA_REG	0x00
@@ -46,7 +48,6 @@ 
 #define SUN4I_CTL_LMTF			BIT(6)
 #define SUN4I_CTL_TF_RST		BIT(8)
 #define SUN4I_CTL_RF_RST		BIT(9)
-#define SUN4I_CTL_XCH_MASK		0x0400
 #define SUN4I_CTL_XCH			BIT(10)
 #define SUN4I_CTL_CS_MASK		0x3000
 #define SUN4I_CTL_CS(cs)		(((cs) << 12) & SUN4I_CTL_CS_MASK)
@@ -308,7 +309,7 @@  static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen,
 	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 
 	u32 len = bitlen / 8;
-	u32 reg;
+	u32 reg, rx_fifocnt;
 	u8 nbytes;
 	int ret;
 
@@ -343,10 +344,12 @@  static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen,
 		reg = readl(&priv->regs->ctl);
 		writel(reg | SUN4I_CTL_XCH, &priv->regs->ctl);
 
-		/* Wait transfer to complete */
-		ret = wait_for_bit_le32(&priv->regs->ctl, SUN4I_CTL_XCH_MASK,
-					false, SUN4I_SPI_TIMEOUT_US, false);
-		if (ret) {
+		/* Wait till RX FIFO to be empty */
+		ret = readl_poll_timeout(&priv->regs->ctl, rx_fifocnt,
+					 !(((rx_fifocnt & SUN4I_FIFO_STA_RF_CNT_MASK) >>
+					 SUN4I_FIFO_STA_RF_CNT_BITS) < nbytes),
+					 SUN4I_SPI_TIMEOUT_US);
+		if (ret < 0) {
 			printf("ERROR: sun4i_spi: Timeout transferring data\n");
 			sun4i_spi_set_cs(bus, slave_plat->cs, false);
 			return ret;