| Message ID | 1546157627-45489-6-git-send-email-tien.fong.chee@intel.com |
|---|---|
| State | Superseded |
| Delegated to: | Marek Vasut |
| Headers | show |
| Series | Add support for loading FPGA bitstream | expand |
On 12/30/18 9:13 AM, tien.fong.chee@intel.com wrote: > From: Tien Fong Chee <tien.fong.chee@intel.com> > > Add support for loading FPGA bitstream to get DDR up running before > U-Boot is loaded into DDR. Boot device initialization, generic firmware > loader and SPL FAT support are required for this whole mechanism to work. > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> > --- > arch/arm/mach-socfpga/spl_a10.c | 46 ++++++++++++++++++++++++++++++++++++++- > 1 files changed, 45 insertions(+), 1 deletions(-) > > diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c > index 3ea64f7..93f5f46 100644 > --- a/arch/arm/mach-socfpga/spl_a10.c > +++ b/arch/arm/mach-socfpga/spl_a10.c > @@ -1,6 +1,6 @@ > // SPDX-License-Identifier: GPL-2.0+ > /* > - * Copyright (C) 2012 Altera Corporation <www.altera.com> > + * Copyright (C) 2012-2018 Altera Corporation <www.altera.com> > */ > > #include <common.h> > @@ -23,9 +23,14 @@ > #include <fdtdec.h> > #include <watchdog.h> > #include <asm/arch/pinmux.h> > +#include <asm/arch/fpga_manager.h> > +#include <mmc.h> > > DECLARE_GLOBAL_DATA_PTR; > > +#define FPGA_SOCFGA_A10_RBF_CORE_LOAD_DDR (1 * 1024) > +#define FPGA_SOCFGA_A10_RBF_CORE_BUFFER_SIZE (40 * 1024 * 1024) > + > static const struct socfpga_system_manager *sysmgr_regs = > (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; > > @@ -73,6 +78,45 @@ void spl_board_init(void) > WATCHDOG_RESET(); > > arch_early_init_r(); > + > + /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */ > + if (is_fpgamgr_user_mode()) { > + config_pins(gd->fdt_blob, "shared"); > + config_pins(gd->fdt_blob, "fpga"); What happens if config_pins() fails ? The function returns some return value. > + } else if (!is_fpgamgr_early_user_mode()) { > + /* Program IOSSM(early IO release) or full FPGA */ > + fpga_fs_info fpga_fsinfo; > + int len; > + char buf[16 * 1024] __aligned(ARCH_DMA_MINALIGN); > + > + fpga_fsinfo.filename = (char *)get_fpga_filename( Is the cast needed ? > + gd->fdt_blob, > + &len, > + FPGA_SOCFPGA_A10_RBF_PERIPH); > + > + if (fpga_fsinfo.filename) > + socfpga_loadfs(&fpga_fsinfo, buf, sizeof(buf), 0); > + } > + > + /* If the IOSSM/full FPGA is already loaded, start DDR */ > + if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode()) > + ddr_calibration_sequence(); > + > + if (!is_fpgamgr_user_mode()) { > + fpga_fs_info fpga_fsinfo; > + int len; > + > + fpga_fsinfo.filename = (char *)get_fpga_filename( > + gd->fdt_blob, > + &len, > + FPGA_SOCFPGA_A10_RBF_CORE); > + > + if (fpga_fsinfo.filename) > + socfpga_loadfs(&fpga_fsinfo, > + (const void *)FPGA_SOCFGA_A10_RBF_CORE_LOAD_DDR, > + (size_t)FPGA_SOCFGA_A10_RBF_CORE_BUFFER_SIZE, > + 0); > + } > } > > void board_init_f(ulong dummy) >
On Sun, 2018-12-30 at 16:51 +0100, Marek Vasut wrote: > On 12/30/18 9:13 AM, tien.fong.chee@intel.com wrote: > > > > From: Tien Fong Chee <tien.fong.chee@intel.com> > > > > Add support for loading FPGA bitstream to get DDR up running before > > U-Boot is loaded into DDR. Boot device initialization, generic > > firmware > > loader and SPL FAT support are required for this whole mechanism to > > work. > > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> > > --- > > arch/arm/mach-socfpga/spl_a10.c | 46 > > ++++++++++++++++++++++++++++++++++++++- > > 1 files changed, 45 insertions(+), 1 deletions(-) > > > > diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach- > > socfpga/spl_a10.c > > index 3ea64f7..93f5f46 100644 > > --- a/arch/arm/mach-socfpga/spl_a10.c > > +++ b/arch/arm/mach-socfpga/spl_a10.c > > @@ -1,6 +1,6 @@ > > // SPDX-License-Identifier: GPL-2.0+ > > /* > > - * Copyright (C) 2012 Altera Corporation <www.altera.com> > > + * Copyright (C) 2012-2018 Altera Corporation <www.altera.com> > > */ > > > > #include <common.h> > > @@ -23,9 +23,14 @@ > > #include <fdtdec.h> > > #include <watchdog.h> > > #include <asm/arch/pinmux.h> > > +#include <asm/arch/fpga_manager.h> > > +#include <mmc.h> > > > > DECLARE_GLOBAL_DATA_PTR; > > > > +#define FPGA_SOCFGA_A10_RBF_CORE_LOAD_DDR (1 * 1024) > > +#define FPGA_SOCFGA_A10_RBF_CORE_BUFFER_SIZE (40 * 1024 * > > 1024) > > + > > static const struct socfpga_system_manager *sysmgr_regs = > > (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; > > > > @@ -73,6 +78,45 @@ void spl_board_init(void) > > WATCHDOG_RESET(); > > > > arch_early_init_r(); > > + > > + /* If the full FPGA is already loaded, ie.from EPCQ, > > config fpga pins */ > > + if (is_fpgamgr_user_mode()) { > > + config_pins(gd->fdt_blob, "shared"); > > + config_pins(gd->fdt_blob, "fpga"); > What happens if config_pins() fails ? The function returns some > return > value. There is return value for config_pins, i can add the debug print out for the return value. > > > > > + } else if (!is_fpgamgr_early_user_mode()) { > > + /* Program IOSSM(early IO release) or full FPGA */ > > + fpga_fs_info fpga_fsinfo; > > + int len; > > + char buf[16 * 1024] __aligned(ARCH_DMA_MINALIGN); > > + > > + fpga_fsinfo.filename = (char *)get_fpga_filename( > Is the cast needed ? there is a warning arch/arm/mach-socfpga/spl_a10.c:109:24: warning: assignment discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers] fpga_fsinfo.filename = get_fpga_filename( > > > > > + gd->fdt_blob, > > + &len, > > + FPGA_SOCFPGA_A10_R > > BF_PERIPH); > > + > > + if (fpga_fsinfo.filename) > > + socfpga_loadfs(&fpga_fsinfo, buf, > > sizeof(buf), 0); > > + } > > + > > + /* If the IOSSM/full FPGA is already loaded, start DDR */ > > + if (is_fpgamgr_early_user_mode() || > > is_fpgamgr_user_mode()) > > + ddr_calibration_sequence(); > > + > > + if (!is_fpgamgr_user_mode()) { > > + fpga_fs_info fpga_fsinfo; > > + int len; > > + > > + fpga_fsinfo.filename = (char *)get_fpga_filename( > > + gd->fdt_blob, > > + &len, > > + FPGA_SOCFPGA_A10_R > > BF_CORE); > > + > > + if (fpga_fsinfo.filename) > > + socfpga_loadfs(&fpga_fsinfo, > > + (const void > > *)FPGA_SOCFGA_A10_RBF_CORE_LOAD_DDR, > > + (size_t)FPGA_SOCFGA_A10_RBF_CORE_B > > UFFER_SIZE, > > + 0); > > + } > > } > > > > void board_init_f(ulong dummy) > > >
On 1/1/19 4:39 AM, Chee, Tien Fong wrote: > On Sun, 2018-12-30 at 16:51 +0100, Marek Vasut wrote: >> On 12/30/18 9:13 AM, tien.fong.chee@intel.com wrote: >>> >>> From: Tien Fong Chee <tien.fong.chee@intel.com> >>> >>> Add support for loading FPGA bitstream to get DDR up running before >>> U-Boot is loaded into DDR. Boot device initialization, generic >>> firmware >>> loader and SPL FAT support are required for this whole mechanism to >>> work. >>> >>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> >>> --- >>> arch/arm/mach-socfpga/spl_a10.c | 46 >>> ++++++++++++++++++++++++++++++++++++++- >>> 1 files changed, 45 insertions(+), 1 deletions(-) >>> >>> diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach- >>> socfpga/spl_a10.c >>> index 3ea64f7..93f5f46 100644 >>> --- a/arch/arm/mach-socfpga/spl_a10.c >>> +++ b/arch/arm/mach-socfpga/spl_a10.c >>> @@ -1,6 +1,6 @@ >>> // SPDX-License-Identifier: GPL-2.0+ >>> /* >>> - * Copyright (C) 2012 Altera Corporation <www.altera.com> >>> + * Copyright (C) 2012-2018 Altera Corporation <www.altera.com> >>> */ >>> >>> #include <common.h> >>> @@ -23,9 +23,14 @@ >>> #include <fdtdec.h> >>> #include <watchdog.h> >>> #include <asm/arch/pinmux.h> >>> +#include <asm/arch/fpga_manager.h> >>> +#include <mmc.h> >>> >>> DECLARE_GLOBAL_DATA_PTR; >>> >>> +#define FPGA_SOCFGA_A10_RBF_CORE_LOAD_DDR (1 * 1024) >>> +#define FPGA_SOCFGA_A10_RBF_CORE_BUFFER_SIZE (40 * 1024 * >>> 1024) >>> + >>> static const struct socfpga_system_manager *sysmgr_regs = >>> (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; >>> >>> @@ -73,6 +78,45 @@ void spl_board_init(void) >>> WATCHDOG_RESET(); >>> >>> arch_early_init_r(); >>> + >>> + /* If the full FPGA is already loaded, ie.from EPCQ, >>> config fpga pins */ >>> + if (is_fpgamgr_user_mode()) { >>> + config_pins(gd->fdt_blob, "shared"); >>> + config_pins(gd->fdt_blob, "fpga"); >> What happens if config_pins() fails ? The function returns some >> return >> value. > There is return value for config_pins, i can add the debug print out > for the return value. And if the function fails, for whatever reason, what does that mean for the system ? Does the system fail ? I think so, right ? >>> + } else if (!is_fpgamgr_early_user_mode()) { >>> + /* Program IOSSM(early IO release) or full FPGA */ >>> + fpga_fs_info fpga_fsinfo; >>> + int len; >>> + char buf[16 * 1024] __aligned(ARCH_DMA_MINALIGN); >>> + >>> + fpga_fsinfo.filename = (char *)get_fpga_filename( >> Is the cast needed ? > there is a warning > arch/arm/mach-socfpga/spl_a10.c:109:24: warning: assignment discards > 'const' qualifier from pointer target type [-Wdiscarded-qualifiers] > fpga_fsinfo.filename = get_fpga_filename( Which tells you that you're forcibly turning a string which the compiler assumes to be constant into one which is not. You're missing const somewhere or you need to remove it from somewhere.
On Tue, 2019-01-01 at 21:31 +0100, Marek Vasut wrote: > On 1/1/19 4:39 AM, Chee, Tien Fong wrote: > > > > On Sun, 2018-12-30 at 16:51 +0100, Marek Vasut wrote: > > > > > > On 12/30/18 9:13 AM, tien.fong.chee@intel.com wrote: > > > > > > > > > > > > From: Tien Fong Chee <tien.fong.chee@intel.com> > > > > > > > > Add support for loading FPGA bitstream to get DDR up running > > > > before > > > > U-Boot is loaded into DDR. Boot device initialization, generic > > > > firmware > > > > loader and SPL FAT support are required for this whole > > > > mechanism to > > > > work. > > > > > > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> > > > > --- > > > > arch/arm/mach-socfpga/spl_a10.c | 46 > > > > ++++++++++++++++++++++++++++++++++++++- > > > > 1 files changed, 45 insertions(+), 1 deletions(-) > > > > > > > > diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach- > > > > socfpga/spl_a10.c > > > > index 3ea64f7..93f5f46 100644 > > > > --- a/arch/arm/mach-socfpga/spl_a10.c > > > > +++ b/arch/arm/mach-socfpga/spl_a10.c > > > > @@ -1,6 +1,6 @@ > > > > // SPDX-License-Identifier: GPL-2.0+ > > > > /* > > > > - * Copyright (C) 2012 Altera Corporation <www.altera.com> > > > > + * Copyright (C) 2012-2018 Altera Corporation <www.altera.com > > > > > > > > > */ > > > > > > > > #include <common.h> > > > > @@ -23,9 +23,14 @@ > > > > #include <fdtdec.h> > > > > #include <watchdog.h> > > > > #include <asm/arch/pinmux.h> > > > > +#include <asm/arch/fpga_manager.h> > > > > +#include <mmc.h> > > > > > > > > DECLARE_GLOBAL_DATA_PTR; > > > > > > > > +#define FPGA_SOCFGA_A10_RBF_CORE_LOAD_DDR (1 * 1024) > > > > +#define FPGA_SOCFGA_A10_RBF_CORE_BUFFER_SIZE (40 * 1024 > > > > * > > > > 1024) > > > > + > > > > static const struct socfpga_system_manager *sysmgr_regs = > > > > (struct socfpga_system_manager > > > > *)SOCFPGA_SYSMGR_ADDRESS; > > > > > > > > @@ -73,6 +78,45 @@ void spl_board_init(void) > > > > WATCHDOG_RESET(); > > > > > > > > arch_early_init_r(); > > > > + > > > > + /* If the full FPGA is already loaded, ie.from EPCQ, > > > > config fpga pins */ > > > > + if (is_fpgamgr_user_mode()) { > > > > + config_pins(gd->fdt_blob, "shared"); > > > > + config_pins(gd->fdt_blob, "fpga"); > > > What happens if config_pins() fails ? The function returns some > > > return > > > value. > > There is return value for config_pins, i can add the debug print > > out > > for the return value. > And if the function fails, for whatever reason, what does that mean > for > the system ? Does the system fail ? I think so, right ? Unexpected behavior. I can put the hang here or you got better idea? > > > > > > > > > > > > > > + } else if (!is_fpgamgr_early_user_mode()) { > > > > + /* Program IOSSM(early IO release) or full > > > > FPGA */ > > > > + fpga_fs_info fpga_fsinfo; > > > > + int len; > > > > + char buf[16 * 1024] > > > > __aligned(ARCH_DMA_MINALIGN); > > > > + > > > > + fpga_fsinfo.filename = (char > > > > *)get_fpga_filename( > > > Is the cast needed ? > > there is a warning > > arch/arm/mach-socfpga/spl_a10.c:109:24: warning: assignment > > discards > > 'const' qualifier from pointer target type [-Wdiscarded-qualifiers] > > fpga_fsinfo.filename = get_fpga_filename( > Which tells you that you're forcibly turning a string which the > compiler > assumes to be constant into one which is not. You're missing const > somewhere or you need to remove it from somewhere. Yes, i can fix it. >
diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index 3ea64f7..93f5f46 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2012 Altera Corporation <www.altera.com> + * Copyright (C) 2012-2018 Altera Corporation <www.altera.com> */ #include <common.h> @@ -23,9 +23,14 @@ #include <fdtdec.h> #include <watchdog.h> #include <asm/arch/pinmux.h> +#include <asm/arch/fpga_manager.h> +#include <mmc.h> DECLARE_GLOBAL_DATA_PTR; +#define FPGA_SOCFGA_A10_RBF_CORE_LOAD_DDR (1 * 1024) +#define FPGA_SOCFGA_A10_RBF_CORE_BUFFER_SIZE (40 * 1024 * 1024) + static const struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; @@ -73,6 +78,45 @@ void spl_board_init(void) WATCHDOG_RESET(); arch_early_init_r(); + + /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */ + if (is_fpgamgr_user_mode()) { + config_pins(gd->fdt_blob, "shared"); + config_pins(gd->fdt_blob, "fpga"); + } else if (!is_fpgamgr_early_user_mode()) { + /* Program IOSSM(early IO release) or full FPGA */ + fpga_fs_info fpga_fsinfo; + int len; + char buf[16 * 1024] __aligned(ARCH_DMA_MINALIGN); + + fpga_fsinfo.filename = (char *)get_fpga_filename( + gd->fdt_blob, + &len, + FPGA_SOCFPGA_A10_RBF_PERIPH); + + if (fpga_fsinfo.filename) + socfpga_loadfs(&fpga_fsinfo, buf, sizeof(buf), 0); + } + + /* If the IOSSM/full FPGA is already loaded, start DDR */ + if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode()) + ddr_calibration_sequence(); + + if (!is_fpgamgr_user_mode()) { + fpga_fs_info fpga_fsinfo; + int len; + + fpga_fsinfo.filename = (char *)get_fpga_filename( + gd->fdt_blob, + &len, + FPGA_SOCFPGA_A10_RBF_CORE); + + if (fpga_fsinfo.filename) + socfpga_loadfs(&fpga_fsinfo, + (const void *)FPGA_SOCFGA_A10_RBF_CORE_LOAD_DDR, + (size_t)FPGA_SOCFGA_A10_RBF_CORE_BUFFER_SIZE, + 0); + } } void board_init_f(ulong dummy)