| Message ID | 1394622364-6848-2-git-send-email-antoine.tenart@free-electrons.com |
|---|---|
| State | New |
| Headers | show |
On 12/03/2014 at 12:06:03 +0100, Antoine Ténart wrote : > Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com> > Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> > --- > Documentation/arm/Marvell/README | 5 + > .../devicetree/bindings/arm/marvell,berlin.txt | 1 + > arch/arm/boot/dts/berlin2q.dtsi | 167 +++++++++++++++++++++ > 3 files changed, 173 insertions(+) > create mode 100644 arch/arm/boot/dts/berlin2q.dtsi > > diff --git a/Documentation/arm/Marvell/README b/Documentation/arm/Marvell/README > index 5a930c1528ad..69ad05ea8ed8 100644 > --- a/Documentation/arm/Marvell/README > +++ b/Documentation/arm/Marvell/README > @@ -224,6 +224,11 @@ Berlin family (Digital Entertainment) > Core: Marvell PJ4B (ARMv7), Tauros3 L2CC > Homepage: http://www.marvell.com/digital-entertainment/armada-1500/ > Product Brief: http://www.marvell.com/digital-entertainment/armada-1500/assets/Marvell-ARMADA-1500-Product-Brief.pdf > + 88DE3114, Armada 1500 Pro > + Desgin name: BG2-Q > + Core: Quad Core ARM CA9, PL310 L2CC > + Homepage: http://www.marvell.com/digital-entertainment/armada-1500-pro/ > + Product Brief: http://www.marvell.com/digital-entertainment/armada-1500-pro/assets/Marvell_ARMADA_1500_PRO-01_product_brief.pdf > 88DE???? > Design name: BG3 > Core: ARM Cortex-A15, CA15 integrated L2CC > diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt > index 737afa5f8148..25472b74218f 100644 > --- a/Documentation/devicetree/bindings/arm/marvell,berlin.txt > +++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt > @@ -11,6 +11,7 @@ In addition, the above compatible shall be extended with the specific > SoC and board used. Currently known SoC compatibles are: > "marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100), > "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005) > + "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q) > "marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????) > "marvell,berlin3" for Marvell Armada ? (BG3, 88DE????) > > diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi > new file mode 100644 > index 000000000000..f58c9c64c60e > --- /dev/null > +++ b/arch/arm/boot/dts/berlin2q.dtsi > @@ -0,0 +1,167 @@ > +/* > + * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com> > + * > + * This file is licensed under the terms of the GNU General Public > + * License version 2. This program is licensed "as is" without any > + * warranty of any kind, whether express or implied. > + */ > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > + > +#include "skeleton.dtsi" > + > +/ { > + model = "Marvell Armada 1500 pro (BG2-Q) SoC"; > + compatible = "marvell,berlin2q", "marvell,berlin"; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu@0 { > + compatible = "arm,cortex-a9"; > + device_type = "cpu"; > + next-level-cache = <&l2>; > + reg = <0>; > + }; > + > + cpu@1 { > + compatible = "arm,cortex-a9"; > + device_type = "cpu"; > + next-level-cache = <&l2>; > + reg = <1>; > + }; > + > + cpu@2 { > + compatible = "arm,cortex-a9"; > + device_type = "cpu"; > + next-level-cache = <&l2>; > + reg = <2>; > + }; > + > + cpu@3 { > + compatible = "arm,cortex-a9"; > + device_type = "cpu"; > + next-level-cache = <&l2>; > + reg = <3>; > + }; > + }; > + > + clocks { > + #address-cells = <1>; > + #size-cells = <1>; > + > + smclk: sysmgr-clock { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <25000000>; > + }; > + The 25MHz crystal is on the board, please move it to the board dts. > + sysclk: system-clock { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <400000000>; > + }; > + }; > + > + soc { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + ranges = <0 0xf7000000 0x1000000>; > + interrupt-parent = <&gic>; > + > + l2: l2-cache-controller@ac0000 { > + compatible = "arm,pl310-cache"; > + reg = <0xac0000 0x1000>; > + cache-level = <2>; > + }; > + > + gic: interrupt-controller@ad1000 { > + compatible = "arm,cortex-a9-gic"; > + reg = <0xad1000 0x1000>, <0xad0100 0x100>; > + interrupt-controller; > + #interrupt-cells = <3>; > + }; > + > + local-timer@ad0600 { > + compatible = "arm,cortex-a9-twd-timer"; > + reg = <0xad0600 0x20>; > + clocks = <&sysclk>; > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; > + status = "okay"; > + }; > + > + apb@e80000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + ranges = <0 0xe80000 0x10000>; > + interrupt-parent = <&aic>; > + > + timer0: timer@2c00 { > + compatible = "snps,dw-apb-timer"; > + reg = <0x2c00 0x14>; > + interrupts = <8>; > + clock-freq = <100000000>; > + status = "okay"; > + }; > + > + timer1: timer@2c14 { > + compatible = "snps,dw-apb-timer"; > + reg = <0x2c14 0x14>; > + clock-freq = <100000000>; > + status = "disabled"; > + }; > + > + aic: interrupt-controller@3800 { > + compatible = "snps,dw-apb-ictl"; > + reg = <0x3800 0x30>; > + interrupt-controller; > + #interrupt-cells = <1>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + > + apb@fc0000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + ranges = <0 0xfc0000 0x10000>; > + interrupt-parent = <&sic>; > + > + uart0: uart@9000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x9000 0x100>; > + interrupt-parent = <&sic>; > + interrupts = <8>; > + clock-frequency = <25000000>; > + reg-shift = <2>; > + status = "disabled"; > + }; > + > + uart1: uart@a000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0xa000 0x100>; > + interrupt-parent = <&sic>; > + interrupts = <9>; > + clock-frequency = <25000000>; > + reg-shift = <2>; > + status = "disabled"; > + }; > + > + sic: interrupt-controller@e000 { > + compatible = "snps,dw-apb-ictl"; > + reg = <0xe000 0x30>; > + interrupt-controller; > + #interrupt-cells = <1>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + }; > +}; > -- > 1.8.3.2 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On 03/12/2014 12:22 PM, Alexandre Belloni wrote: > On 12/03/2014 at 12:06:03 +0100, Antoine Ténart wrote : >> Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com> >> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> >> --- >> Documentation/arm/Marvell/README | 5 + >> .../devicetree/bindings/arm/marvell,berlin.txt | 1 + Please separate doc and dtsi changes into separate patches. >> arch/arm/boot/dts/berlin2q.dtsi | 167 +++++++++++++++++++++ >> 3 files changed, 173 insertions(+) >> create mode 100644 arch/arm/boot/dts/berlin2q.dtsi >> >> diff --git a/Documentation/arm/Marvell/README b/Documentation/arm/Marvell/README >> index 5a930c1528ad..69ad05ea8ed8 100644 >> --- a/Documentation/arm/Marvell/README >> +++ b/Documentation/arm/Marvell/README >> @@ -224,6 +224,11 @@ Berlin family (Digital Entertainment) >> Core: Marvell PJ4B (ARMv7), Tauros3 L2CC >> Homepage: http://www.marvell.com/digital-entertainment/armada-1500/ >> Product Brief: http://www.marvell.com/digital-entertainment/armada-1500/assets/Marvell-ARMADA-1500-Product-Brief.pdf >> + 88DE3114, Armada 1500 Pro >> + Desgin name: BG2-Q s/Desgin/Design/ >> + Core: Quad Core ARM CA9, PL310 L2CC s/ARM CA9/ARM Cortex-A9/ >> + Homepage: http://www.marvell.com/digital-entertainment/armada-1500-pro/ >> + Product Brief: http://www.marvell.com/digital-entertainment/armada-1500-pro/assets/Marvell_ARMADA_1500_PRO-01_product_brief.pdf >> 88DE???? >> Design name: BG3 >> Core: ARM Cortex-A15, CA15 integrated L2CC >> diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt >> index 737afa5f8148..25472b74218f 100644 >> --- a/Documentation/devicetree/bindings/arm/marvell,berlin.txt >> +++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt >> @@ -11,6 +11,7 @@ In addition, the above compatible shall be extended with the specific >> SoC and board used. Currently known SoC compatibles are: >> "marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100), >> "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005) >> + "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q) Please add 88DE3114 above like there is already for the other SoCs. >> "marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????) >> "marvell,berlin3" for Marvell Armada ? (BG3, 88DE????) >> >> diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi >> new file mode 100644 >> index 000000000000..f58c9c64c60e >> --- /dev/null >> +++ b/arch/arm/boot/dts/berlin2q.dtsi >> @@ -0,0 +1,167 @@ >> +/* >> + * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com> >> + * >> + * This file is licensed under the terms of the GNU General Public >> + * License version 2. This program is licensed "as is" without any >> + * warranty of any kind, whether express or implied. >> + */ >> + >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> + >> +#include "skeleton.dtsi" >> + >> +/ { >> + model = "Marvell Armada 1500 pro (BG2-Q) SoC"; >> + compatible = "marvell,berlin2q", "marvell,berlin"; [...] >> + clocks { >> + #address-cells = <1>; >> + #size-cells = <1>; >> + >> + smclk: sysmgr-clock { >> + compatible = "fixed-clock"; >> + #clock-cells = <0>; >> + clock-frequency = <25000000>; >> + }; >> + > > The 25MHz crystal is on the board, please move it to the board dts. If you can confirm that sysmgr clock comes directly from this crystal, I agree. If it is fed into a pll and can possibly be modified or gated, make it depend on a 25MHz board crystal. If 25MHz is the only option for this clock input, I could also live with it being part of the SoC description. Sebastian
On 03/12/2014 11:06 AM, Antoine Ténart wrote: > Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com> > Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> > --- Missed some comments on the nodes below. [...] > diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi > new file mode 100644 > index 000000000000..f58c9c64c60e > --- /dev/null > +++ b/arch/arm/boot/dts/berlin2q.dtsi > @@ -0,0 +1,167 @@ > +/* > + * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com> > + * > + * This file is licensed under the terms of the GNU General Public > + * License version 2. This program is licensed "as is" without any > + * warranty of any kind, whether express or implied. > + */ > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > + > +#include "skeleton.dtsi" > + > +/ { > + model = "Marvell Armada 1500 pro (BG2-Q) SoC"; > + compatible = "marvell,berlin2q", "marvell,berlin"; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu@0 { > + compatible = "arm,cortex-a9"; > + device_type = "cpu"; > + next-level-cache = <&l2>; > + reg = <0>; > + }; > + > + cpu@1 { > + compatible = "arm,cortex-a9"; > + device_type = "cpu"; > + next-level-cache = <&l2>; > + reg = <1>; > + }; > + > + cpu@2 { > + compatible = "arm,cortex-a9"; > + device_type = "cpu"; > + next-level-cache = <&l2>; > + reg = <2>; > + }; > + > + cpu@3 { > + compatible = "arm,cortex-a9"; > + device_type = "cpu"; > + next-level-cache = <&l2>; > + reg = <3>; > + }; > + }; > + > + clocks { > + #address-cells = <1>; > + #size-cells = <1>; You are not numbering the clocks below. Shouldn't this be #address-cells = <0>; #size-cells = <0>; then? > + > + smclk: sysmgr-clock { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <25000000>; > + }; > + > + sysclk: system-clock { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <400000000>; > + }; > + }; > + > + soc { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + ranges = <0 0xf7000000 0x1000000>; > + interrupt-parent = <&gic>; > + > + l2: l2-cache-controller@ac0000 { > + compatible = "arm,pl310-cache"; > + reg = <0xac0000 0x1000>; > + cache-level = <2>; > + }; > + > + gic: interrupt-controller@ad1000 { > + compatible = "arm,cortex-a9-gic"; > + reg = <0xad1000 0x1000>, <0xad0100 0x100>; > + interrupt-controller; > + #interrupt-cells = <3>; > + }; > + > + local-timer@ad0600 { Please keep nodes sorted by address. > + compatible = "arm,cortex-a9-twd-timer"; > + reg = <0xad0600 0x20>; > + clocks = <&sysclk>; Playing with Chromecast, I remember local-timer running at sysclk/3 or something. I know berlin2/berlin2cd is wrong here. Can you check that for berlin2q local-timer also runs at sysclk/n? > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; > + status = "okay"; > + }; > + > + apb@e80000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + ranges = <0 0xe80000 0x10000>; > + interrupt-parent = <&aic>; > + > + timer0: timer@2c00 { > + compatible = "snps,dw-apb-timer"; > + reg = <0x2c00 0x14>; > + interrupts = <8>; > + clock-freq = <100000000>; > + status = "okay"; > + }; > + > + timer1: timer@2c14 { > + compatible = "snps,dw-apb-timer"; > + reg = <0x2c14 0x14>; > + clock-freq = <100000000>; > + status = "disabled"; > + }; berlin2/berlin2cd have a vast amount of 8 apb timers. Any timers missing here or did Marvell remove them? > + aic: interrupt-controller@3800 { > + compatible = "snps,dw-apb-ictl"; > + reg = <0x3800 0x30>; > + interrupt-controller; > + #interrupt-cells = <1>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + > + apb@fc0000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + ranges = <0 0xfc0000 0x10000>; > + interrupt-parent = <&sic>; > + > + uart0: uart@9000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x9000 0x100>; > + interrupt-parent = <&sic>; > + interrupts = <8>; > + clock-frequency = <25000000>; > + reg-shift = <2>; > + status = "disabled"; > + }; > + > + uart1: uart@a000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0xa000 0x100>; > + interrupt-parent = <&sic>; > + interrupts = <9>; > + clock-frequency = <25000000>; > + reg-shift = <2>; > + status = "disabled"; > + }; Also for uart, can you please double-check if there is no uart2? Sebastian > + sic: interrupt-controller@e000 { > + compatible = "snps,dw-apb-ictl"; > + reg = <0xe000 0x30>; > + interrupt-controller; > + #interrupt-cells = <1>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + }; > +}; >
On 13/03/2014 at 09:56:48 +0000, Sebastian Hesselbarth wrote : > On 03/12/2014 12:22 PM, Alexandre Belloni wrote: > > > >The 25MHz crystal is on the board, please move it to the board dts. > > If you can confirm that sysmgr clock comes directly from this crystal, > I agree. If it is fed into a pll and can possibly be modified or gated, > make it depend on a 25MHz board crystal. If 25MHz is the only option > for this clock input, I could also live with it being part of the SoC > description. > Yeah, after more discussion, the 25 MHz crystl is the only option and it is fed to an oscillator that generate the reference clock for the PLLs. It is probably fine to let it in the dtsi.
On 03/13/2014 10:08 AM, Alexandre Belloni wrote: > On 13/03/2014 at 09:56:48 +0000, Sebastian Hesselbarth wrote : >> On 03/12/2014 12:22 PM, Alexandre Belloni wrote: >>> >>> The 25MHz crystal is on the board, please move it to the board dts. >> >> If you can confirm that sysmgr clock comes directly from this crystal, >> I agree. If it is fed into a pll and can possibly be modified or gated, >> make it depend on a 25MHz board crystal. If 25MHz is the only option >> for this clock input, I could also live with it being part of the SoC >> description. >> > > Yeah, after more discussion, the 25 MHz crystl is the only option and it > is fed to an oscillator that generate the reference clock for the PLLs. > It is probably fine to let it in the dtsi. > Fine, I am planing to do more work on Berlin and especially clocks next cycle. So most of the fixed-clocks will vanish anyway. BTW, back at ELCE/ARM summit I successfully enabled SMP for berlin2. I'll dig that patch out for you to re-test on Quad-core bg2q. Sebastian
On 13/03/2014 11:17, Sebastian Hesselbarth wrote: > BTW, back at ELCE/ARM summit I successfully enabled SMP for berlin2. > I'll dig that patch out for you to re-test on Quad-core bg2q. I was just starting to work on the enabling the SMP. Please send me your patch, I'll test it on the bg2q. Antoine
On 13/03/2014 at 10:05:31 +0000, Sebastian Hesselbarth wrote : > On 03/12/2014 11:06 AM, Antoine Ténart wrote: > >+ compatible = "arm,cortex-a9-twd-timer"; > >+ reg = <0xad0600 0x20>; > >+ clocks = <&sysclk>; > > Playing with Chromecast, I remember local-timer running at sysclk/3 or > something. I know berlin2/berlin2cd is wrong here. Can you check that > for berlin2q local-timer also runs at sysclk/n? > Actually, what we have is sysclk = cpuclk/3 so I guess it depends on what you call sysclk. > >+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; > >+ status = "okay"; > >+ }; > >+ > >+ apb@e80000 { > >+ compatible = "simple-bus"; > >+ #address-cells = <1>; > >+ #size-cells = <1>; > >+ > >+ ranges = <0 0xe80000 0x10000>; > >+ interrupt-parent = <&aic>; > >+ > >+ timer0: timer@2c00 { > >+ compatible = "snps,dw-apb-timer"; > >+ reg = <0x2c00 0x14>; > >+ interrupts = <8>; > >+ clock-freq = <100000000>; > >+ status = "okay"; > >+ }; > >+ > >+ timer1: timer@2c14 { > >+ compatible = "snps,dw-apb-timer"; > >+ reg = <0x2c14 0x14>; > >+ clock-freq = <100000000>; > >+ status = "disabled"; > >+ }; > > berlin2/berlin2cd have a vast amount of 8 apb timers. Any timers missing > here or did Marvell remove them? > > > Also for uart, can you please double-check if there is no uart2? > We don't have those informations, maybe Jisheng can help ?
Hi, On Thu, 13 Mar 2014 03:43:03 -0700 Alexandre Belloni <alexandre.belloni@free-electrons.com> wrote: > On 13/03/2014 at 10:05:31 +0000, Sebastian Hesselbarth wrote : > > On 03/12/2014 11:06 AM, Antoine Ténart wrote: > > >+ compatible = "arm,cortex-a9-twd-timer"; > > >+ reg = <0xad0600 0x20>; > > >+ clocks = <&sysclk>; > > > > Playing with Chromecast, I remember local-timer running at sysclk/3 or twdclk is running at cpuclk/3. On chromecast, freq of cpuclk is the same as sysclk. But parent of twdclk is cpuclk. > > something. I know berlin2/berlin2cd is wrong here. Can you check that > > for berlin2q local-timer also runs at sysclk/n? > > > > Actually, what we have is sysclk = cpuclk/3 so I guess it depends on > what you call sysclk. > > > >+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; > > >+ status = "okay"; > > >+ }; > > >+ > > >+ apb@e80000 { > > >+ compatible = "simple-bus"; > > >+ #address-cells = <1>; > > >+ #size-cells = <1>; > > >+ > > >+ ranges = <0 0xe80000 0x10000>; > > >+ interrupt-parent = <&aic>; > > >+ > > >+ timer0: timer@2c00 { > > >+ compatible = "snps,dw-apb-timer"; > > >+ reg = <0x2c00 0x14>; > > >+ interrupts = <8>; > > >+ clock-freq = <100000000>; > > >+ status = "okay"; > > >+ }; > > >+ > > >+ timer1: timer@2c14 { > > >+ compatible = "snps,dw-apb-timer"; > > >+ reg = <0x2c14 0x14>; > > >+ clock-freq = <100000000>; > > >+ status = "disabled"; > > >+ }; > > > > berlin2/berlin2cd have a vast amount of 8 apb timers. Any timers missing > > here or did Marvell remove them? We still have 8 apb timers > > > > > > Also for uart, can you please double-check if there is no uart2? > > > > We don't have those informations, maybe Jisheng can help ? uart2 is removed Thanks, Jisheng
diff --git a/Documentation/arm/Marvell/README b/Documentation/arm/Marvell/README index 5a930c1528ad..69ad05ea8ed8 100644 --- a/Documentation/arm/Marvell/README +++ b/Documentation/arm/Marvell/README @@ -224,6 +224,11 @@ Berlin family (Digital Entertainment) Core: Marvell PJ4B (ARMv7), Tauros3 L2CC Homepage: http://www.marvell.com/digital-entertainment/armada-1500/ Product Brief: http://www.marvell.com/digital-entertainment/armada-1500/assets/Marvell-ARMADA-1500-Product-Brief.pdf + 88DE3114, Armada 1500 Pro + Desgin name: BG2-Q + Core: Quad Core ARM CA9, PL310 L2CC + Homepage: http://www.marvell.com/digital-entertainment/armada-1500-pro/ + Product Brief: http://www.marvell.com/digital-entertainment/armada-1500-pro/assets/Marvell_ARMADA_1500_PRO-01_product_brief.pdf 88DE???? Design name: BG3 Core: ARM Cortex-A15, CA15 integrated L2CC diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt index 737afa5f8148..25472b74218f 100644 --- a/Documentation/devicetree/bindings/arm/marvell,berlin.txt +++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt @@ -11,6 +11,7 @@ In addition, the above compatible shall be extended with the specific SoC and board used. Currently known SoC compatibles are: "marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100), "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005) + "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q) "marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????) "marvell,berlin3" for Marvell Armada ? (BG3, 88DE????) diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi new file mode 100644 index 000000000000..f58c9c64c60e --- /dev/null +++ b/arch/arm/boot/dts/berlin2q.dtsi @@ -0,0 +1,167 @@ +/* + * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +#include "skeleton.dtsi" + +/ { + model = "Marvell Armada 1500 pro (BG2-Q) SoC"; + compatible = "marvell,berlin2q", "marvell,berlin"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + next-level-cache = <&l2>; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + next-level-cache = <&l2>; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + next-level-cache = <&l2>; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + next-level-cache = <&l2>; + reg = <3>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + + smclk: sysmgr-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + sysclk: system-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0xf7000000 0x1000000>; + interrupt-parent = <&gic>; + + l2: l2-cache-controller@ac0000 { + compatible = "arm,pl310-cache"; + reg = <0xac0000 0x1000>; + cache-level = <2>; + }; + + gic: interrupt-controller@ad1000 { + compatible = "arm,cortex-a9-gic"; + reg = <0xad1000 0x1000>, <0xad0100 0x100>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + local-timer@ad0600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xad0600 0x20>; + clocks = <&sysclk>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; + }; + + apb@e80000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0xe80000 0x10000>; + interrupt-parent = <&aic>; + + timer0: timer@2c00 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c00 0x14>; + interrupts = <8>; + clock-freq = <100000000>; + status = "okay"; + }; + + timer1: timer@2c14 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c14 0x14>; + clock-freq = <100000000>; + status = "disabled"; + }; + + aic: interrupt-controller@3800 { + compatible = "snps,dw-apb-ictl"; + reg = <0x3800 0x30>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + apb@fc0000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0xfc0000 0x10000>; + interrupt-parent = <&sic>; + + uart0: uart@9000 { + compatible = "snps,dw-apb-uart"; + reg = <0x9000 0x100>; + interrupt-parent = <&sic>; + interrupts = <8>; + clock-frequency = <25000000>; + reg-shift = <2>; + status = "disabled"; + }; + + uart1: uart@a000 { + compatible = "snps,dw-apb-uart"; + reg = <0xa000 0x100>; + interrupt-parent = <&sic>; + interrupts = <9>; + clock-frequency = <25000000>; + reg-shift = <2>; + status = "disabled"; + }; + + sic: interrupt-controller@e000 { + compatible = "snps,dw-apb-ictl"; + reg = <0xe000 0x30>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; +};