Message ID | 20131107124234.GA2459@msticlxl57.ims.intel.com |
---|---|
State | New |
Headers | show |
Hello,
On 07 Nov 15:42, Kirill Yukhin wrote:
> Could you pls take a look?
Ping?
--
Thanks, K
On Tue, 2013-11-12 at 11:38 +0300, Kirill Yukhin wrote: > Hello, > > On 07 Nov 15:42, Kirill Yukhin wrote: > > Could you pls take a look? > > Ping? > > -- > Thanks, K Looks OK to me, go ahead and check it in. Steve Ellcey sellcey@mips.com
> diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c > index a128b19..446ee59 100644 > --- a/gcc/config/ia64/ia64.c > +++ b/gcc/config/ia64/ia64.c > @@ -1527,12 +1527,19 @@ ia64_split_tmode_move (rtx operands[]) > && reg_overlap_mentioned_p (operands[0], operands[1])) > { > rtx base = XEXP (operands[1], 0); > + rtx first_write = gen_rtx_REG (DImode, REGNO (operands[0])); > while (GET_CODE (base) != REG) > base = XEXP (base, 0); > > if (REGNO (base) == REGNO (operands[0])) > - reversed = true; > - dead = true; > + { > + reversed = true; > + first_write = gen_rtx_REG (DImode, REGNO (operands[0]) + 1); > + } > + > + if (GET_CODE (operands[0]) == REG > + && reg_overlap_mentioned_p (first_write, operands[1])) > + dead = true; > } > /* Another reason to do the moves in reversed order is if the first > element of the target register pair is also the second element of Note that the new "GET_CODE (operands[0]) == REG" check is redundant, since REGNO (operands[0]) is already accessed before. And instead of generating very short-lived RTL, you could use refers_to_regno_p instead. I suspect that the problem reported by Jeff is related to the usage of "dead" in the REG subcase of the MEM case of ia64_split_tmode. There is a dangling comment to that effect in ia64_split_tmode_move just above the block.
Hello, > I suspect that the problem reported by Jeff is related to the usage of "dead" > in the REG subcase of the MEM case of ia64_split_tmode. There is a dangling > comment to that effect in ia64_split_tmode_move just above the block. We're failing here. Trying to split SET with these operands: operands[0] is (reg:TI 14 r14 [orig:448 *_61[_12]{lb: 1 sz: 64}.text ] [448]) operands[1] is (mem:TI (reg/f:DI 15 r15 [447]) [3 *_61[_12]{lb: 1 sz: 64}.text+0 S16 A128]) I think that such a set (despite of intersect by r15) is valid. This RTX is splitted by ia64_split_tmode_move into these 2 insns: (insn 199 0 0 (set (reg:DI 14 r14) (mem:DI (post_inc:DI (reg/f:DI 15 r15 [447])) [3 *_61[_12]{lb: 1 sz: 64}.text+0 S8 A128])) -1 (nil)) (insn 200 199 0 (set (reg:DI 15 r15) (mem:DI (post_dec:DI (reg/f:DI 15 r15 [447])) [3 *_61[_12]{lb: 1 sz: 64}.text+8 S8 A64])) -1 (nil)) Although r15 post_dec in second insn seems to be useless code seems to be valid for me. What do you guys think? -- Thanks, K
> We're failing here. Trying to split SET with these operands: > operands[0] is (reg:TI 14 r14 [orig:448 *_61[_12]{lb: 1 sz: 64}.text ] > [448]) operands[1] is (mem:TI (reg/f:DI 15 r15 [447]) [3 *_61[_12]{lb: 1 > sz: 64}.text+0 S16 A128]) > > I think that such a set (despite of intersect by r15) is valid. Yes, that's the purpose of the block in ia64_split_tmode_move. > This RTX is splitted by ia64_split_tmode_move into these 2 insns: > (insn 199 0 0 (set (reg:DI 14 r14) > (mem:DI (post_inc:DI (reg/f:DI 15 r15 [447])) [3 > *_61[_12]{lb: 1 sz: 64}.text+0 S8 A128])) -1 (nil)) > (insn 200 199 0 (set (reg:DI 15 r15) > (mem:DI (post_dec:DI (reg/f:DI 15 r15 [447])) [3 > *_61[_12]{lb: 1 sz: 64}.text+8 S8 A64])) -1 (nil)) > > Although r15 post_dec in second insn seems to be useless code seems to be > valid for me. What do you guys think? But the post_dec will clobber r15, won't it?
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c index a128b19..446ee59 100644 --- a/gcc/config/ia64/ia64.c +++ b/gcc/config/ia64/ia64.c @@ -1527,12 +1527,19 @@ ia64_split_tmode_move (rtx operands[]) && reg_overlap_mentioned_p (operands[0], operands[1])) { rtx base = XEXP (operands[1], 0); + rtx first_write = gen_rtx_REG (DImode, REGNO (operands[0])); while (GET_CODE (base) != REG) base = XEXP (base, 0); if (REGNO (base) == REGNO (operands[0])) - reversed = true; - dead = true; + { + reversed = true; + first_write = gen_rtx_REG (DImode, REGNO (operands[0]) + 1); + } + + if (GET_CODE (operands[0]) == REG + && reg_overlap_mentioned_p (first_write, operands[1])) + dead = true; } /* Another reason to do the moves in reversed order is if the first element of the target register pair is also the second element of