| Message ID | 524A7CF9.5030707@linaro.org |
|---|---|
| State | New |
| Headers | show |
On 10/01/13 08:42, Kugan wrote: > Hi, > > I am attaching a patch that reverts Split shift di patterns (r197527) as > it introduced PR58578. I am also attaching a patch to add a testcase > based on this failiures. > > No regression on qemu for arm-none-eabi and new testcase now passes. > > Is this OK? > > Thanks, > Kugan > Ok if no regressions. Thanks, Ramana
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7c9a6c5..abc545f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,15 @@ +2013-10-01 Kugan Vivekanandarajah <kuganv@linaro.org> + + PR target/58578 + Revert + 2013-04-05 Greta Yorsh <Greta.Yorsh@arm.com> + * config/arm/arm.md (arm_ashldi3_1bit): define_insn into + define_insn_and_split. + (arm_ashrdi3_1bit,arm_lshrdi3_1bit): Likewise. + (shiftsi3_compare): New pattern. + (rrx): New pattern. + * config/arm/unspecs.md (UNSPEC_RRX): New. + 2013-09-30 Richard Sandiford <rdsandiford@googlemail.com> * vec.h (vec_prefix, vec): Prefix member names with "m_".
Hi, I am attaching a patch that reverts Split shift di patterns (r197527) as it introduced PR58578. I am also attaching a patch to add a testcase based on this failiures. No regression on qemu for arm-none-eabi and new testcase now passes. Is this OK? Thanks, Kugan diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 3b22081..4b9f991 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2013-10-01 Kugan Vivekanandarajah <kuganv@linaro.org> + + PR Target/58578 + * gcc.target/arm/pr58578.c: New test. + 2013-09-30 Jakub Jelinek <jakub@redhat.com> PR middle-end/58564 diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index b094cff..e8d5464 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -3867,26 +3867,13 @@ " ) -(define_insn_and_split "arm_ashldi3_1bit" +(define_insn "arm_ashldi3_1bit" [(set (match_operand:DI 0 "s_register_operand" "=r,&r") (ashift:DI (match_operand:DI 1 "s_register_operand" "0,r") (const_int 1))) (clobber (reg:CC CC_REGNUM))] "TARGET_32BIT" - "#" ; "movs\\t%Q0, %Q1, asl #1\;adc\\t%R0, %R1, %R1" - "&& reload_completed" - [(parallel [(set (reg:CC CC_REGNUM) - (compare:CC (ashift:SI (match_dup 1) (const_int 1)) - (const_int 0))) - (set (match_dup 0) (ashift:SI (match_dup 1) (const_int 1)))]) - (set (match_dup 2) (plus:SI (plus:SI (match_dup 3) (match_dup 3)) - (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] - { - operands[2] = gen_highpart (SImode, operands[0]); - operands[0] = gen_lowpart (SImode, operands[0]); - operands[3] = gen_highpart (SImode, operands[1]); - operands[1] = gen_lowpart (SImode, operands[1]); - } + "movs\\t%Q0, %Q1, asl #1\;adc\\t%R0, %R1, %R1" [(set_attr "conds" "clob") (set_attr "length" "8") (set_attr "type" "multiple")] @@ -3964,43 +3951,18 @@ " ) -(define_insn_and_split "arm_ashrdi3_1bit" +(define_insn "arm_ashrdi3_1bit" [(set (match_operand:DI 0 "s_register_operand" "=r,&r") (ashiftrt:DI (match_operand:DI 1 "s_register_operand" "0,r") (const_int 1))) (clobber (reg:CC CC_REGNUM))] "TARGET_32BIT" - "#" ; "movs\\t%R0, %R1, asr #1\;mov\\t%Q0, %Q1, rrx" - "&& reload_completed" - [(parallel [(set (reg:CC CC_REGNUM) - (compare:CC (ashiftrt:SI (match_dup 3) (const_int 1)) - (const_int 0))) - (set (match_dup 2) (ashiftrt:SI (match_dup 3) (const_int 1)))]) - (set (match_dup 0) (unspec:SI [(match_dup 1) - (reg:CC_C CC_REGNUM)] - UNSPEC_RRX))] - { - operands[2] = gen_highpart (SImode, operands[0]); - operands[0] = gen_lowpart (SImode, operands[0]); - operands[3] = gen_highpart (SImode, operands[1]); - operands[1] = gen_lowpart (SImode, operands[1]); - } + "movs\\t%R0, %R1, asr #1\;mov\\t%Q0, %Q1, rrx" [(set_attr "conds" "clob") (set_attr "length" "8") (set_attr "type" "multiple")] ) -(define_insn "*rrx" - [(set (match_operand:SI 0 "s_register_operand" "=r") - (unspec:SI [(match_operand:SI 1 "s_register_operand" "r") - (reg:CC_C CC_REGNUM)] - UNSPEC_RRX))] - "TARGET_32BIT" - "mov\\t%0, %1, rrx" - [(set_attr "conds" "use") - (set_attr "type" "mov_shift")] -) - (define_expand "ashrsi3" [(set (match_operand:SI 0 "s_register_operand" "") (ashiftrt:SI (match_operand:SI 1 "s_register_operand" "") @@ -4070,27 +4032,13 @@ " ) -(define_insn_and_split "arm_lshrdi3_1bit" +(define_insn "arm_lshrdi3_1bit" [(set (match_operand:DI 0 "s_register_operand" "=r,&r") (lshiftrt:DI (match_operand:DI 1 "s_register_operand" "0,r") (const_int 1))) (clobber (reg:CC CC_REGNUM))] "TARGET_32BIT" - "#" ; "movs\\t%R0, %R1, lsr #1\;mov\\t%Q0, %Q1, rrx" - "&& reload_completed" - [(parallel [(set (reg:CC CC_REGNUM) - (compare:CC (lshiftrt:SI (match_dup 3) (const_int 1)) - (const_int 0))) - (set (match_dup 2) (lshiftrt:SI (match_dup 3) (const_int 1)))]) - (set (match_dup 0) (unspec:SI [(match_dup 1) - (reg:CC_C CC_REGNUM)] - UNSPEC_RRX))] - { - operands[2] = gen_highpart (SImode, operands[0]); - operands[0] = gen_lowpart (SImode, operands[0]); - operands[3] = gen_highpart (SImode, operands[1]); - operands[1] = gen_lowpart (SImode, operands[1]); - } + "movs\\t%R0, %R1, lsr #1\;mov\\t%Q0, %Q1, rrx" [(set_attr "conds" "clob") (set_attr "length" "8") (set_attr "type" "multiple")] @@ -4183,21 +4131,6 @@ (set_attr "type" "alu_shift_reg,alu_shift_imm,alu_shift_imm,alu_shift_reg")] ) -(define_insn "*shiftsi3_compare" - [(set (reg:CC CC_REGNUM) - (compare:CC (match_operator:SI 3 "shift_operator" - [(match_operand:SI 1 "s_register_operand" "r,r") - (match_operand:SI 2 "arm_rhs_operand" "M,r")]) - (const_int 0))) - (set (match_operand:SI 0 "s_register_operand" "=r,r") - (match_op_dup 3 [(match_dup 1) (match_dup 2)]))] - "TARGET_32BIT" - "* return arm_output_shift(operands, 1);" - [(set_attr "conds" "set") - (set_attr "shift" "1") - (set_attr "type" "alus_shift_imm,alus_shift_reg")] -) - (define_insn "*shiftsi3_compare0" [(set (reg:CC_NOOV CC_REGNUM) (compare:CC_NOOV (match_operator:SI 3 "shift_operator" diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index c43a6a6..508603c 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -83,8 +83,6 @@ ; FPSCR rounding mode and signal inexactness. UNSPEC_VRINTA ; Represent a float to integral float rounding ; towards nearest, ties away from zero. - UNSPEC_RRX ; Rotate Right with Extend shifts register right - ; by one place, with Carry flag shifted into bit[31]. ]) (define_c_enum "unspec" [ diff --git a/gcc/testsuite/gcc.target/arm/pr58578.c b/gcc/testsuite/gcc.target/arm/pr58578.c new file mode 100644 index 0000000..2b474f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr58578.c @@ -0,0 +1,54 @@ + +/* PR target/58578 */ +/* { dg-do run } */ +/* { dg-options "-O1" } */ + +#include <stdlib.h> + +typedef struct { + long _prec; + int _flag; + long _exp; +} __my_st_t; + +typedef __my_st_t *__my_st_ptr; + +int +_test_fn (__my_st_ptr y, const __my_st_ptr xt) +{ + int inexact; + if (xt->_exp != -2147483647L) + { + (y->_flag = xt->_flag); + } + + do { + __my_st_ptr _y = y; + long _err1 = -2 * xt->_exp; + long _err2 = 2; + if (0 < _err1) + { + unsigned long _err = (unsigned long) _err1 + _err2; + if (__builtin_expect(!!(_err > _y->_prec + 1), 0)) + return 2; + return 3; + } + } while (0); + + return 0; +} + +int main () +{ + __my_st_t x, y; + long pz; + int inex; + + x._prec = 914; + y._exp = 18; + if (_test_fn (&x, &y)) + { + abort(); + } + return 0; +}