diff mbox

Intel pci device quirk remove D3 delay

Message ID 20130910231043.GA31857@linux.intel.com
State Accepted
Headers show

Commit Message

Todd Brandt Sept. 10, 2013, 11:10 p.m. UTC 
The latest Ivy Bridge Intel chipsets have a hardware optimization which
allows on-chip PCI devices to ignore the 10ms delay before entering
or exitting D3 suspend.

This patch implements the optimization as a pci quirk, since we want
tight control over which devices use it. This way we can test each device
individually to be sure there are no issues before we enable the quirk.
The first set of devices are from the Haswell platform, which includes
every PCI device that is on the northbridge and southbridge.

After testing this patch reduces the haswell suspend time from 93 ms to
47 ms and resume time from 160 ms to 64 ms. 

Signed-off-by: Todd Brandt <todd.e.brandt@linux.intel.com>

 drivers/pci/quirks.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)


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Comments

Rafael J. Wysocki Sept. 11, 2013, 1:20 p.m. UTC | #1 
On Tuesday, September 10, 2013 04:10:43 PM Todd E Brandt wrote:
> The latest Ivy Bridge Intel chipsets have a hardware optimization which
> allows on-chip PCI devices to ignore the 10ms delay before entering
> or exitting D3 suspend.
> 
> This patch implements the optimization as a pci quirk, since we want
> tight control over which devices use it. This way we can test each device
> individually to be sure there are no issues before we enable the quirk.
> The first set of devices are from the Haswell platform, which includes
> every PCI device that is on the northbridge and southbridge.
> 
> After testing this patch reduces the haswell suspend time from 93 ms to
> 47 ms and resume time from 160 ms to 64 ms. 
> 
> Signed-off-by: Todd Brandt <todd.e.brandt@linux.intel.com>

Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

>  drivers/pci/quirks.c | 23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index e85d230..98ea960 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -2955,6 +2955,29 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
>  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
>  
>  /*
> + * PCI devices which are on Intel chips can skip the 10ms delay
> + * before entering D3 mode.
> + */
> +static void quirk_remove_d3_delay(struct pci_dev *dev)
> +{
> +	dev->d3_delay = 0;
> +}
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
> +
> +/*
>   * Some devices may pass our check in pci_intx_mask_supported if
>   * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
>   * support this feature.
> 
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> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
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Bjorn Helgaas Sept. 24, 2013, 11:19 p.m. UTC | #2 
On Tue, Sep 10, 2013 at 04:10:43PM -0700, Todd E Brandt wrote:
> The latest Ivy Bridge Intel chipsets have a hardware optimization which

You said "Ivy Bridge" above but use "Haswell" below.  Let me know if
anything needs to be corrected here.

> allows on-chip PCI devices to ignore the 10ms delay before entering
> or exitting D3 suspend.
> 
> This patch implements the optimization as a pci quirk, since we want
> tight control over which devices use it. This way we can test each device
> individually to be sure there are no issues before we enable the quirk.
> The first set of devices are from the Haswell platform, which includes
> every PCI device that is on the northbridge and southbridge.
> 
> After testing this patch reduces the haswell suspend time from 93 ms to
> 47 ms and resume time from 160 ms to 64 ms. 
> 
> Signed-off-by: Todd Brandt <todd.e.brandt@linux.intel.com>
> 
>  drivers/pci/quirks.c | 23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)

I added Rafael's ack and applied this for v3.13 (but I can still make
corrections if required).

Let me know if you want this in v3.12 instead.

Bjorn

> 
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index e85d230..98ea960 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -2955,6 +2955,29 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
>  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
>  
>  /*
> + * PCI devices which are on Intel chips can skip the 10ms delay
> + * before entering D3 mode.
> + */
> +static void quirk_remove_d3_delay(struct pci_dev *dev)
> +{
> +	dev->d3_delay = 0;
> +}
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
> +
> +/*
>   * Some devices may pass our check in pci_intx_mask_supported if
>   * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
>   * support this feature.
> 
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Bjorn Helgaas Sept. 25, 2013, 9:48 p.m. UTC | #3 
On Tue, Sep 24, 2013 at 5:19 PM, Bjorn Helgaas <bhelgaas@google.com> wrote:
> On Tue, Sep 10, 2013 at 04:10:43PM -0700, Todd E Brandt wrote:
>> The latest Ivy Bridge Intel chipsets have a hardware optimization which
>
> You said "Ivy Bridge" above but use "Haswell" below.  Let me know if
> anything needs to be corrected here.

Reading this again, the text really doesn't make sense as-is.  So
please confirm what this should say.

It sure looks like it should say "The latest *Haswell* Intel chipsets ..."

If you really mean "Ivy Bridge," then you should say something about
how Haswell is related to Ivy Bridge.  No doubt this is all obvious to
Intel folks, but it's not to me :)

Bjorn

>> allows on-chip PCI devices to ignore the 10ms delay before entering
>> or exitting D3 suspend.
>>
>> This patch implements the optimization as a pci quirk, since we want
>> tight control over which devices use it. This way we can test each device
>> individually to be sure there are no issues before we enable the quirk.
>> The first set of devices are from the Haswell platform, which includes
>> every PCI device that is on the northbridge and southbridge.
>>
>> After testing this patch reduces the haswell suspend time from 93 ms to
>> 47 ms and resume time from 160 ms to 64 ms.
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Arjan van de Ven Sept. 25, 2013, 10:17 p.m. UTC | #4 
On 9/25/2013 2:48 PM, Bjorn Helgaas wrote:
> On Tue, Sep 24, 2013 at 5:19 PM, Bjorn Helgaas <bhelgaas@google.com> wrote:
>> On Tue, Sep 10, 2013 at 04:10:43PM -0700, Todd E Brandt wrote:
>>> The latest Ivy Bridge Intel chipsets have a hardware optimization which
>>
>> You said "Ivy Bridge" above but use "Haswell" below.  Let me know if
>> anything needs to be corrected here.
>
> Reading this again, the text really doesn't make sense as-is.  So
> please confirm what this should say.
>
> It sure looks like it should say "The latest *Haswell* Intel chipsets ..."
>
> If you really mean "Ivy Bridge," then you should say something about
> how Haswell is related to Ivy Bridge.  No doubt this is all obvious to
> Intel folks, but it's not to me :)

it should read "Haswell".

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Bjorn Helgaas Sept. 25, 2013, 11:01 p.m. UTC | #5 
On Wed, Sep 25, 2013 at 4:17 PM, Arjan van de Ven <arjan@linux.intel.com> wrote:
> On 9/25/2013 2:48 PM, Bjorn Helgaas wrote:
>>
>> On Tue, Sep 24, 2013 at 5:19 PM, Bjorn Helgaas <bhelgaas@google.com>
>> wrote:
>>>
>>> On Tue, Sep 10, 2013 at 04:10:43PM -0700, Todd E Brandt wrote:
>>>>
>>>> The latest Ivy Bridge Intel chipsets have a hardware optimization which
>>>
>>>
>>> You said "Ivy Bridge" above but use "Haswell" below.  Let me know if
>>> anything needs to be corrected here.
>>
>>
>> Reading this again, the text really doesn't make sense as-is.  So
>> please confirm what this should say.
>>
>> It sure looks like it should say "The latest *Haswell* Intel chipsets ..."
>>
>> If you really mean "Ivy Bridge," then you should say something about
>> how Haswell is related to Ivy Bridge.  No doubt this is all obvious to
>> Intel folks, but it's not to me :)
>
>
> it should read "Haswell".

Fixed, thanks!

Bjorn
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diff mbox

Patch

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index e85d230..98ea960 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2955,6 +2955,29 @@  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
 
 /*
+ * PCI devices which are on Intel chips can skip the 10ms delay
+ * before entering D3 mode.
+ */
+static void quirk_remove_d3_delay(struct pci_dev *dev)
+{
+	dev->d3_delay = 0;
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
+
+/*
  * Some devices may pass our check in pci_intx_mask_supported if
  * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
  * support this feature.