@@ -3685,7 +3685,7 @@ (define_insn "l<fcvt_pattern><su_optab><
"TARGET_FLOAT"
"fcvt<frint_suffix><su>\\t%<GPI:w>0, %<GPF:s>1"
[(set_attr "v8type" "fcvtf2i")
- (set_attr "type" "f_cvt")
+ (set_attr "type" "f_cvtf2i")
(set_attr "mode" "<GPF:MODE>")
(set_attr "mode2" "<GPI:MODE>")]
)
@@ -3785,7 +3785,7 @@ (define_insn "fix_trunc<GPF:mode><GPI:mo
"TARGET_FLOAT"
"fcvtzs\\t%<GPI:w>0, %<GPF:s>1"
[(set_attr "v8type" "fcvtf2i")
- (set_attr "type" "f_cvt")
+ (set_attr "type" "f_cvtf2i")
(set_attr "mode" "<GPF:MODE>")
(set_attr "mode2" "<GPI:MODE>")]
)
@@ -3796,7 +3796,7 @@ (define_insn "fixuns_trunc<GPF:mode><GPI
"TARGET_FLOAT"
"fcvtzu\\t%<GPI:w>0, %<GPF:s>1"
[(set_attr "v8type" "fcvtf2i")
- (set_attr "type" "f_cvt")
+ (set_attr "type" "f_cvtf2i")
(set_attr "mode" "<GPF:MODE>")
(set_attr "mode2" "<GPI:MODE>")]
)
@@ -3807,7 +3807,7 @@ (define_insn "float<GPI:mode><GPF:mode>2
"TARGET_FLOAT"
"scvtf\\t%<GPF:s>0, %<GPI:w>1"
[(set_attr "v8type" "fcvti2f")
- (set_attr "type" "f_cvt")
+ (set_attr "type" "f_cvti2f")
(set_attr "mode" "<GPF:MODE>")
(set_attr "mode2" "<GPI:MODE>")]
)
@@ -289,7 +289,7 @@ (define_insn_reservation "v10_farith" 5
(define_insn_reservation "v10_cvt" 5
(and (eq_attr "vfp10" "yes")
- (eq_attr "type" "f_cvt"))
+ (eq_attr "type" "f_cvt,f_cvti2f,f_cvtf2i"))
"1020a_e+v10_fmac")
(define_insn_reservation "v10_fmul" 6
@@ -471,7 +471,7 @@ (define_insn_reservation "cortex_a15_vfp
(define_insn_reservation "cortex_a15_vfp_cvt" 6
(and (eq_attr "tune" "cortexa15")
- (eq_attr "type" "f_cvt"))
+ (eq_attr "type" "f_cvt,f_cvtf2i,f_cvti2f"))
"ca15_issue1,ca15_cx_vfp")
(define_insn_reservation "cortex_a15_vfp_cmpd" 8
@@ -168,7 +168,8 @@ (define_insn_reservation "cortex_a5_bran
(define_insn_reservation "cortex_a5_fpalu" 4
(and (eq_attr "tune" "cortexa5")
- (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls, f_cvt,\
+ (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls,\
+ f_cvt,f_cvtf2i,f_cvti2f,\
fcmps, fcmpd"))
"cortex_a5_ex1+cortex_a5_fpadd_pipe")
@@ -209,7 +209,8 @@ (define_insn_reservation "cortex_a53_bra
(define_insn_reservation "cortex_a53_fpalu" 4
(and (eq_attr "tune" "cortexa53")
- (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls, f_cvt,\
+ (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls,\
+ f_cvt,f_cvtf2i,f_cvti2f,\
fcmps, fcmpd, fcsel"))
"cortex_a53_slot0+cortex_a53_fpadd_pipe")
@@ -205,7 +205,7 @@ (define_insn_reservation "cortex_a7_stor
(define_insn_reservation "cortex_a7_fpalu" 4
(and (eq_attr "tune" "cortexa7")
(eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys,\
- f_cvt, fcmps, fcmpd"))
+ f_cvt, f_cvtf2i, f_cvti2f, fcmps, fcmpd"))
"cortex_a7_ex1+cortex_a7_fpadd_pipe")
;; For fconsts and fconstd, 8-bit immediate data is passed directly from
@@ -177,7 +177,7 @@ (define_insn_reservation "cortex_a8_vfp_
(define_insn_reservation "cortex_a8_vfp_cvt" 7
(and (eq_attr "tune" "cortexa8")
- (eq_attr "type" "f_cvt"))
+ (eq_attr "type" "f_cvt,f_cvtf2i,f_cvti2f"))
"cortex_a8_vfp,cortex_a8_vfplite*6")
;; NEON -> core transfers.
@@ -233,7 +233,7 @@ (define_reservation "ca9fp_add" "ca9_iss
(define_insn_reservation "cortex_a9_fadd" 4
(and (eq_attr "tune" "cortexa9")
- (eq_attr "type" "fadds, faddd, f_cvt"))
+ (eq_attr "type" "fadds, faddd, f_cvt, f_cvtf2i, f_cvti2f"))
"ca9fp_add")
(define_insn_reservation "cortex_a9_fcmp" 1
@@ -77,7 +77,7 @@ (define_insn_reservation "cortex_m4_f_fl
(define_insn_reservation "cortex_m4_f_cvt" 2
(and (eq_attr "tune" "cortexm4")
- (eq_attr "type" "f_cvt"))
+ (eq_attr "type" "f_cvt,f_cvtf2i,f_cvti2f"))
"cortex_m4_ex_v")
(define_insn_reservation "cortex_m4_f_load" 2
@@ -146,7 +146,7 @@ (define_insn_reservation "cortex_r4_fcmp
(define_insn_reservation "cortex_r4_f_cvt" 8
(and (eq_attr "tune_cortexr4" "yes")
- (eq_attr "type" "f_cvt"))
+ (eq_attr "type" "f_cvt,f_cvtf2i,f_cvti2f"))
"cortex_r4_single_issue*3")
(define_insn_reservation "cortex_r4_f_memd" 8
@@ -209,7 +209,8 @@ (define_bypass 5 "pj4_vfp_mac" "pj4_vfp_
(define_insn_reservation "pj4_vfp_cpy" 4
(and (eq_attr "tune" "marvell_pj4")
(eq_attr "type" "fcpys,ffariths,ffarithd,fconsts,fconstd,\
- fcmps,fcmpd,f_cvt")) "pj4_is,nothing*2,vissue,vfast,nothing*2")
+ fcmps,fcmpd,f_cvt,f_cvtf2i,f_cvti2f"))
+"pj4_is,nothing*2,vissue,vfast,nothing*2")
;; Enlarge latency, and wish that more nondependent insns are
;; scheduled immediately after VFP load.
@@ -55,7 +55,9 @@
; clz count leading zeros (CLZ).
; csel From ARMv8-A: conditional select.
; extend extend instruction (SXTB, SXTH, UXTB, UXTH).
-; f_cvt conversion between float and integral.
+; f_cvt conversion between float representations.
+; f_cvtf2i conversion between float and integral types.
+; f_cvti2f conversion between integral and float types.
; f_flag transfer of co-processor flags to the CPSR.
; f_load[d,s] double/single load from memory. Used for VFP unit.
; f_mcr transfer arm to vfp reg.
@@ -311,6 +313,8 @@ (define_attr "type"
csel,\
extend,\
f_cvt,\
+ f_cvtf2i,\
+ f_cvti2f,\
f_flag,\
f_loadd,\
f_loads,\
@@ -991,7 +991,7 @@ (define_insn "*truncsisf2_vfp"
"ftosizs%?\\t%0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
- (set_attr "type" "f_cvt")]
+ (set_attr "type" "f_cvtf2i")]
)
(define_insn "*truncsidf2_vfp"
@@ -1001,7 +1001,7 @@ (define_insn "*truncsidf2_vfp"
"ftosizd%?\\t%0, %P1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
- (set_attr "type" "f_cvt")]
+ (set_attr "type" "f_cvtf2i")]
)
@@ -1012,7 +1012,7 @@ (define_insn "fixuns_truncsfsi2"
"ftouizs%?\\t%0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
- (set_attr "type" "f_cvt")]
+ (set_attr "type" "f_cvtf2i")]
)
(define_insn "fixuns_truncdfsi2"
@@ -1022,7 +1022,7 @@ (define_insn "fixuns_truncdfsi2"
"ftouizd%?\\t%0, %P1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
- (set_attr "type" "f_cvt")]
+ (set_attr "type" "f_cvtf2i")]
)
@@ -1033,7 +1033,7 @@ (define_insn "*floatsisf2_vfp"
"fsitos%?\\t%0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
- (set_attr "type" "f_cvt")]
+ (set_attr "type" "f_cvti2f")]
)
(define_insn "*floatsidf2_vfp"
@@ -1043,7 +1043,7 @@ (define_insn "*floatsidf2_vfp"
"fsitod%?\\t%P0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
- (set_attr "type" "f_cvt")]
+ (set_attr "type" "f_cvti2f")]
)
@@ -1054,7 +1054,7 @@ (define_insn "floatunssisf2"
"fuitos%?\\t%0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
- (set_attr "type" "f_cvt")]
+ (set_attr "type" "f_cvti2f")]
)
(define_insn "floatunssidf2"
@@ -1064,7 +1064,7 @@ (define_insn "floatunssidf2"
"fuitod%?\\t%P0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
- (set_attr "type" "f_cvt")]
+ (set_attr "type" "f_cvti2f")]
)
@@ -1229,7 +1229,7 @@ (define_insn "*combine_vcvt_f32_<FCVTI32
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math"
"vcvt.f32.<FCVTI32typename>\\t%0, %1, %v2"
[(set_attr "predicable" "no")
- (set_attr "type" "f_cvt")]
+ (set_attr "type" "f_cvti2f")]
)
;; Not the ideal way of implementing this. Ideally we would be able to split
@@ -1246,7 +1246,7 @@ (define_insn "*combine_vcvt_f64_<FCVTI32
vmov.f32\\t%0, %1\;vcvt.f64.<FCVTI32typename>\\t%P0, %P0, %v2
vmov.f64\\t%P0, %1, %1\;vcvt.f64.<FCVTI32typename>\\t%P0, %P0, %v2"
[(set_attr "predicable" "no")
- (set_attr "type" "f_cvt")
+ (set_attr "type" "f_cvti2f")
(set_attr "length" "8")]
)
@@ -56,7 +56,8 @@ (define_insn_reservation "vfp_ffarith" 4
(define_insn_reservation "vfp_farith" 8
(and (eq_attr "generic_vfp" "yes")
- (eq_attr "type" "fadds,faddd,fconsts,fconstd,f_cvt,fmuls,fmacs,ffmas"))
+ (eq_attr "type" "fadds,faddd,fconsts,fconstd,f_cvt,f_cvtf2i,f_cvti2f,\
+ fmuls,fmacs,ffmas"))
"fmac")
(define_insn_reservation "vfp_fmul" 9