| Message ID | 1369590093-9086-1-git-send-email-guerr@julio.in |
|---|---|
| State | New |
| Headers | show |
ping 2013/5/26 Julio Guerra <guerr@julio.in>: > MPC86xx processors are based on the e600 core, which is not the case > in qemu where it is based on the 7400 processor. > > This patch creates the e600 core and instantiates the MPC86xx > processors based on it. Therefore, adding the high BATs and the SPRG > 4..7 registers, which are e600-specific [1]. > > This allows to define the MPC8610 processor too and my program running > on a real MPC8610 target is now able to run on qemu :) > > [1] http://cache.freescale.com/files/32bit/doc/ref_manual/E600CORERM.pdf > > Signed-off-by: Julio Guerra <guerr@julio.in> > --- > target-ppc/cpu-models.c | 10 ++-- > target-ppc/cpu-models.h | 4 +- > target-ppc/translate_init.c | 122 ++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 127 insertions(+), 9 deletions(-) > > diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c > index 17f56b7..8a2ab50 100644 > --- a/target-ppc/cpu-models.c > +++ b/target-ppc/cpu-models.c > @@ -792,17 +792,15 @@ > POWERPC_DEF_SVR("MPC8572E", "MPC8572E", > CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2) > /* e600 family */ > - POWERPC_DEF("e600", CPU_POWERPC_e600, 7400, > + POWERPC_DEF("e600", CPU_POWERPC_e600, e600, > "PowerPC e600 core") > /* PowerPC e600 microcontrollers */ > -#if defined(TODO) > POWERPC_DEF_SVR("MPC8610", "MPC8610", > - CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400) > -#endif > + CPU_POWERPC_MPC8610, POWERPC_SVR_8610, e600) > POWERPC_DEF_SVR("MPC8641", "MPC8641", > - CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400) > + CPU_POWERPC_MPC8641, POWERPC_SVR_8641, e600) > POWERPC_DEF_SVR("MPC8641D", "MPC8641D", > - CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400) > + CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, e600) > /* 32 bits "classic" PowerPC */ > /* PowerPC 6xx family */ > POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601, > diff --git a/target-ppc/cpu-models.h b/target-ppc/cpu-models.h > index a94f835..8ba96bb 100644 > --- a/target-ppc/cpu-models.h > +++ b/target-ppc/cpu-models.h > @@ -731,9 +731,7 @@ enum { > POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500, > POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500, > POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500, > -#if 0 > - POWERPC_SVR_8610 = xxx, > -#endif > + POWERPC_SVR_8610 = 0x80A00011, > POWERPC_SVR_8641 = 0x80900021, > POWERPC_SVR_8641D = 0x80900121, > }; > diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c > index 021a31e..916fe0d 100644 > --- a/target-ppc/translate_init.c > +++ b/target-ppc/translate_init.c > @@ -6525,2 +6525,2 @@ POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) > POWERPC_FLAG_BUS_CLK; > } > > +static void init_proc_e600(CPUPPCState *env) > +{ > + gen_spr_ne_601(env); > + gen_spr_7xx(env); > + /* Time base */ > + gen_tbl(env); > + /* 74xx specific SPR */ > + gen_spr_74xx(env); > + /* XXX : not implemented */ > + spr_register(env, SPR_UBAMR, "UBAMR", > + &spr_read_ureg, SPR_NOACCESS, > + &spr_read_ureg, SPR_NOACCESS, > + 0x00000000); > + /* XXX : not implemented */ > + spr_register(env, SPR_LDSTCR, "LDSTCR", > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + /* XXX : not implemented */ > + spr_register(env, SPR_ICTRL, "ICTRL", > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + /* XXX : not implemented */ > + spr_register(env, SPR_MSSSR0, "MSSSR0", > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + /* XXX : not implemented */ > + spr_register(env, SPR_PMC5, "PMC5", > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + /* XXX : not implemented */ > + spr_register(env, SPR_UPMC5, "UPMC5", > + &spr_read_ureg, SPR_NOACCESS, > + &spr_read_ureg, SPR_NOACCESS, > + 0x00000000); > + /* XXX : not implemented */ > + spr_register(env, SPR_PMC6, "PMC6", > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + /* XXX : not implemented */ > + spr_register(env, SPR_UPMC6, "UPMC6", > + &spr_read_ureg, SPR_NOACCESS, > + &spr_read_ureg, SPR_NOACCESS, > + 0x00000000); > + /* SPRGs */ > + spr_register(env, SPR_SPRG4, "SPRG4", > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + spr_register(env, SPR_USPRG4, "USPRG4", > + &spr_read_ureg, SPR_NOACCESS, > + &spr_read_ureg, SPR_NOACCESS, > + 0x00000000); > + spr_register(env, SPR_SPRG5, "SPRG5", > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + spr_register(env, SPR_USPRG5, "USPRG5", > + &spr_read_ureg, SPR_NOACCESS, > + &spr_read_ureg, SPR_NOACCESS, > + 0x00000000); > + spr_register(env, SPR_SPRG6, "SPRG6", > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + spr_register(env, SPR_USPRG6, "USPRG6", > + &spr_read_ureg, SPR_NOACCESS, > + &spr_read_ureg, SPR_NOACCESS, > + 0x00000000); > + spr_register(env, SPR_SPRG7, "SPRG7", > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + spr_register(env, SPR_USPRG7, "USPRG7", > + &spr_read_ureg, SPR_NOACCESS, > + &spr_read_ureg, SPR_NOACCESS, > + 0x00000000); > + /* Memory management */ > + gen_low_BATs(env); > + gen_high_BATs(env); > + gen_74xx_soft_tlb(env, 128, 2); > + init_excp_7450(env); > + env->dcache_line_size = 32; > + env->icache_line_size = 32; > + /* Allocate hardware IRQ controller */ > + ppc6xx_irq_init(env); > +} > + > +POWERPC_FAMILY(e600)(ObjectClass* oc, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(oc); > + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); > + > + dc->desc = "PowerPC e600"; > + pcc->init_proc = init_proc_e600; > + pcc->check_pow = check_pow_hid0_74xx; > + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | > + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | > + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | > + PPC_FLOAT_STFIWX | > + PPC_CACHE | PPC_CACHE_ICBI | > + PPC_CACHE_DCBA | PPC_CACHE_DCBZ | > + PPC_MEM_SYNC | PPC_MEM_EIEIO | > + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | > + PPC_MEM_TLBIA | PPC_74xx_TLB | > + PPC_SEGMENT | PPC_EXTERN | > + PPC_ALTIVEC; > + pcc->insns_flags2 = PPC_NONE; > + pcc->msr_mask = 0x000000000205FF77ULL; > + pcc->mmu_model = POWERPC_MMU_32B; > + pcc->excp_model = POWERPC_EXCP_74xx; > + pcc->bus_model = PPC_FLAGS_INPUT_6xx; > + pcc->bfd_mach = bfd_mach_ppc_7400; > + pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | > + POWERPC_FLAG_BE | POWERPC_FLAG_PMM | > + POWERPC_FLAG_BUS_CLK; > +} > + > #if defined (TARGET_PPC64) > #if defined(CONFIG_USER_ONLY) > #define POWERPC970_HID5_INIT 0x00000080 > -- > 1.8.1.4 -- Julio Guerra
Am 26.05.2013 19:41, schrieb Julio Guerra: > MPC86xx processors are based on the e600 core, which is not the case > in qemu where it is based on the 7400 processor. > > This patch creates the e600 core and instantiates the MPC86xx > processors based on it. Therefore, adding the high BATs and the SPRG > 4..7 registers, which are e600-specific [1]. > > This allows to define the MPC8610 processor too and my program running > on a real MPC8610 target is now able to run on qemu :) > > [1] http://cache.freescale.com/files/32bit/doc/ref_manual/E600CORERM.pdf > > Signed-off-by: Julio Guerra <guerr@julio.in> > --- > target-ppc/cpu-models.c | 10 ++-- > target-ppc/cpu-models.h | 4 +- > target-ppc/translate_init.c | 122 ++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 127 insertions(+), 9 deletions(-) From a technical (QOM) view this patch looks fine. However I can't judge whether all that code is right for e600 and whether you may want to share some code with e500 / e5500 in some way? CC'ing some Freescale folks. Regards, Andreas
>> >> However I can't judge whether all that code is right for e600 and >> whether you may want to share some code with e500 / e5500 in some way? >> CC'ing some Freescale folks. > > > e600 is a very different core from e500/e5500. It is a 74xx derivative. > The only thing I can see that could be shared with e500 is the code to > register SPRG4-7, but that's something that's already duplicated between a > bunch of cores. > Yes, and as previously said, this is almost entirely a copy/paste from the 7440 code, plus SPRGs 4..7, the high BATs and the POWERPC_MMU_32B setting. It can be shared in a later patch. -- Julio Guerra
2013/6/7 Julio Guerra <guerr@julio.in>: >>> >>> However I can't judge whether all that code is right for e600 and >>> whether you may want to share some code with e500 / e5500 in some way? >>> CC'ing some Freescale folks. >> >> >> e600 is a very different core from e500/e5500. It is a 74xx derivative. >> The only thing I can see that could be shared with e500 is the code to >> register SPRG4-7, but that's something that's already duplicated between a >> bunch of cores. >> > > Yes, and as previously said, this is almost entirely a copy/paste from > the 7440 code, plus SPRGs 4..7, the high BATs and the POWERPC_MMU_32B > setting. It can be shared in a later patch. > ping -- Julio Guerra
On 26.05.2013, at 19:41, Julio Guerra wrote: > MPC86xx processors are based on the e600 core, which is not the case > in qemu where it is based on the 7400 processor. > > This patch creates the e600 core and instantiates the MPC86xx > processors based on it. Therefore, adding the high BATs and the SPRG > 4..7 registers, which are e600-specific [1]. > > This allows to define the MPC8610 processor too and my program running > on a real MPC8610 target is now able to run on qemu :) > > [1] http://cache.freescale.com/files/32bit/doc/ref_manual/E600CORERM.pdf > > Signed-off-by: Julio Guerra <guerr@julio.in> Thanks, applied to ppc-next. Alex
2013/6/21 Alexander Graf <agraf@suse.de>: > > On 26.05.2013, at 19:41, Julio Guerra wrote: > >> MPC86xx processors are based on the e600 core, which is not the case >> in qemu where it is based on the 7400 processor. >> >> This patch creates the e600 core and instantiates the MPC86xx >> processors based on it. Therefore, adding the high BATs and the SPRG >> 4..7 registers, which are e600-specific [1]. >> >> This allows to define the MPC8610 processor too and my program running >> on a real MPC8610 target is now able to run on qemu :) >> >> [1] http://cache.freescale.com/files/32bit/doc/ref_manual/E600CORERM.pdf >> >> Signed-off-by: Julio Guerra <guerr@julio.in> > > Thanks, applied to ppc-next. > I just retested this patch and I noticed the `handle_mmu_fault` default value introduced by recent A. Farber patches on the CPU definitions is wrong with the selected memory model. Thus qemu complains about the MMU model. The following is missing in e600 CPU definition: > #if defined(CONFIG_SOFTMMU) > ppc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; > #endif Can you correct it or should I resend a patch (v3 or just the previous three lines) ? -- Julio Guerra
On 21.06.2013, at 14:01, Julio Guerra wrote: > 2013/6/21 Alexander Graf <agraf@suse.de>: >> >> On 26.05.2013, at 19:41, Julio Guerra wrote: >> >>> MPC86xx processors are based on the e600 core, which is not the case >>> in qemu where it is based on the 7400 processor. >>> >>> This patch creates the e600 core and instantiates the MPC86xx >>> processors based on it. Therefore, adding the high BATs and the SPRG >>> 4..7 registers, which are e600-specific [1]. >>> >>> This allows to define the MPC8610 processor too and my program running >>> on a real MPC8610 target is now able to run on qemu :) >>> >>> [1] http://cache.freescale.com/files/32bit/doc/ref_manual/E600CORERM.pdf >>> >>> Signed-off-by: Julio Guerra <guerr@julio.in> >> >> Thanks, applied to ppc-next. >> > > I just retested this patch and I noticed the `handle_mmu_fault` > default value introduced by recent A. Farber patches on the CPU > definitions is wrong with the selected memory model. Thus qemu > complains about the MMU model. > > The following is missing in e600 CPU definition: >> #if defined(CONFIG_SOFTMMU) >> ppc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; >> #endif > > Can you correct it or should I resend a patch (v3 or just the previous > three lines) ? Just send a patch on top of the current one. Alex
On 21.06.2013, at 01:16, Alexander Graf wrote: > > On 26.05.2013, at 19:41, Julio Guerra wrote: > >> MPC86xx processors are based on the e600 core, which is not the case >> in qemu where it is based on the 7400 processor. >> >> This patch creates the e600 core and instantiates the MPC86xx >> processors based on it. Therefore, adding the high BATs and the SPRG >> 4..7 registers, which are e600-specific [1]. >> >> This allows to define the MPC8610 processor too and my program running >> on a real MPC8610 target is now able to run on qemu :) >> >> [1] http://cache.freescale.com/files/32bit/doc/ref_manual/E600CORERM.pdf >> >> Signed-off-by: Julio Guerra <guerr@julio.in> > > Thanks, applied to ppc-next. Sorry, I only now realized how broken this patch was. The patch hunk headers don't align with the length of the hunks. Spaces at the beginning of lines get lost towards the end. The patch as is simply treats most of the code as comments. Check out what patchworks does with it: http://patchwork.ozlabs.org/patch/246445/ Just try to take that mbox file from there and git am it. You'll see what I mean. Please repost with a working mailer. Git-send-email works quite well for me ;). I've removed the patch from my queue again for now. Alex
On 06/21/2013 10:03 PM, Alexander Graf wrote: > > On 21.06.2013, at 14:01, Julio Guerra wrote: > >> 2013/6/21 Alexander Graf <agraf@suse.de>: >>> >>> On 26.05.2013, at 19:41, Julio Guerra wrote: >>> >>>> MPC86xx processors are based on the e600 core, which is not the case >>>> in qemu where it is based on the 7400 processor. >>>> >>>> This patch creates the e600 core and instantiates the MPC86xx >>>> processors based on it. Therefore, adding the high BATs and the SPRG >>>> 4..7 registers, which are e600-specific [1]. >>>> >>>> This allows to define the MPC8610 processor too and my program running >>>> on a real MPC8610 target is now able to run on qemu :) >>>> >>>> [1] http://cache.freescale.com/files/32bit/doc/ref_manual/E600CORERM.pdf >>>> >>>> Signed-off-by: Julio Guerra <guerr@julio.in> >>> >>> Thanks, applied to ppc-next. >>> >> >> I just retested this patch and I noticed the `handle_mmu_fault` >> default value introduced by recent A. Farber patches on the CPU >> definitions is wrong with the selected memory model. Thus qemu >> complains about the MMU model. >> >> The following is missing in e600 CPU definition: >>> #if defined(CONFIG_SOFTMMU) >>> ppc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; >>> #endif >> >> Can you correct it or should I resend a patch (v3 or just the previous >> three lines) ? > > Just send a patch on top of the current one. I do not really understand what this patch actually does but it breaks my pseries/power7 setup. Please, help. Starting program: /home/aik/qemu-system-ppc64 -L qemu-ppc64-bios/ -trace events=qemu_trace_events -net nic,model=e1000,addr=0:0:0 -net user,hostfwd=tcp::5000-:22 -m 1024 -machine pseries -nographic -vga none -enable-kvm -kernel guest.vmlinux.n -initrd 1.cpio [Thread debugging using libthread_db enabled] Using host libthread_db library "/lib64/libthread_db.so.1". ** ERROR:/home/alexey/pcipassthru/qemu-impreza/qom/object.c:152:type_get_parent: assertion failed: (type->parent_type != NULL) Breakpoint 4, 0x00000080c6eefb8c in .abort () from /lib64/libc.so.6 Missing separate debuginfos, use: debuginfo-install SDL-1.2.15-8.fc19.ppc64 bluez-libs-4.101-6.fc19.ppc64 boost-system-1.53.0-6.fc19.ppc64 boost-thread-1.53.0-6.fc19.ppc64 brlapi-0.6.0-5.fc19.ppc64 ceph-devel-0.56.4-1.fc19.ppc64 ceph-libs-0.56.4-1.fc19.ppc64 cryptopp-5.6.2-2.fc19.ppc64 cyrus-sasl-lib-2.1.26-8.fc19.ppc64p7 glib2-2.36.2-1.fc19.ppc64 glibc-2.17-4.fc19.ppc64p7 glusterfs-3.4.0-0.5.beta2.fc19.ppc64 glusterfs-api-3.4.0-0.5.beta2.fc19.ppc64 gmp-5.1.1-2.fc19.ppc64 gnutls-3.1.11-1.fc19.ppc64 keyutils-libs-1.5.5-4.fc19.ppc64 krb5-libs-1.11.2-10.fc19.ppc64 leveldb-1.9.0-1.fc19.ppc64 libX11-1.5.99.902-1.fc19.ppc64 libXau-1.0.6-7.fc19.ppc64 libcom_err-1.42.7-2.fc19.ppc64 libcurl-7.29.0-6.fc19.ppc64 libfdt-1.3.0-6.fc19.ppc64 libgcc-4.8.0-8.fc19.ppc64 libgcrypt-1.5.2-1.fc19.ppc64 libgpg-error-1.11-1.fc19.ppc64 libidn-1.26-2.fc19.ppc64 libjpeg-turbo-1.2.90-2.fc19.ppc64 libselinux-2.1.13-15.fc19.ppc64 libssh2-1.4.3-4.fc19.ppc64 libstdc++-4.8.0-8.fc19.ppc64 libtasn1-3.3-1.fc19.ppc64 libuuid-2.23.1-2.fc19.ppc64 libxcb-1.9-3.fc19.ppc64 ncurses-libs-5.9-11.20130511.fc19.ppc64 nettle-2.6-2.fc19.ppc64 nspr-4.9.6-1.fc19.ppc64 nss-3.14.3-13.0.fc19.ppc64 nss-softokn-freebl-3.14.3-1.fc19.ppc64 nss-util-3.14.3-1.fc19.ppc64 openldap-2.4.35-4.fc19.ppc64 openssl-libs-1.0.1e-4.fc19.ppc64p7 p11-kit-0.18.3-1.fc19.ppc64 pcre-8.32-6.fc19.ppc64p7 pixman-0.30.0-1.fc19.ppc64 snappy-1.1.0-1.fc19.ppc64 zlib-1.2.7-10.fc19.ppc64p7 (gdb) up #1 0x00000080c742d54c in .g_assertion_message () from /lib64/libglib-2.0.so.0 (gdb) #2 0x00000080c742d5f4 in .g_assertion_message_expr () from /lib64/libglib-2.0.so.0 (gdb) bt #0 0x00000080c6eefb8c in .abort () from /lib64/libc.so.6 #1 0x00000080c742d54c in .g_assertion_message () from /lib64/libglib-2.0.so.0 #2 0x00000080c742d5f4 in .g_assertion_message_expr () from /lib64/libglib-2.0.so.0 #3 0x0000000010260058 in type_get_parent (type=0x10f7b260) at /home/alexey/pcipassthru/qemu-impreza/qom/object.c:152 #4 0x0000000010260120 in type_class_get_size (ti=0x10f7b260) at /home/alexey/pcipassthru/qemu-impreza/qom/object.c:170 #5 0x00000000102603d8 in type_initialize (ti=0x10f7b260) at /home/alexey/pcipassthru/qemu-impreza/qom/object.c:236 #6 0x000000001026175c in object_class_foreach_tramp (key=0x10f7b3e0, value=0x10f7b260, opaque=0x3fffffffe5e0) at /home/alexey/pcipassthru/qemu-impreza/qom/object.c:626 #7 0x00000080c73e0ab0 in .g_hash_table_foreach () from /lib64/libglib-2.0.so.0 #8 0x000000001026188c in object_class_foreach (fn= @0x10681290: 0x10261988 <object_class_get_list_tramp>, implements_type=0x105c7188 "powerpc64-cpu", include_abstract=0x0, opaque=0x3fffffffe680) at /home/alexey/pcipassthru/qemu-impreza/qom/object.c:647 #9 0x0000000010261a3c in object_class_get_list (implements_type=0x105c7188 "powerpc64-cpu", include_abstract=0x0) at /home/alexey/pcipassthru/qemu-impreza/qom/object.c:679 #10 0x0000000010459dec in ppc_cpu_class_by_pvr (pvr=0x3f0201) at /home/alexey/pcipassthru/qemu-impreza/target-ppc/translate_init.c:7908 #11 0x00000000103ca368 in kvm_ppc_register_host_cpu_type () at /home/alexey/pcipassthru/qemu-impreza/target-ppc/kvm.c:1781 #12 0x00000000103c4fcc in kvm_arch_init (s=0x10fb8ab0) at /home/alexey/pcipassthru/qemu-impreza/target-ppc/kvm.c:110 #13 0x0000000010376138 in kvm_init () at /home/alexey/pcipassthru/qemu-impreza/kvm-all.c:1461 #14 0x00000000102c1b08 in configure_accelerator () at /home/alexey/pcipassthru/qemu-impreza/vl.c:2673 #15 0x00000000102c5e28 in main (argc=0x15, argv=0x3ffffffff218, envp=0x3ffffffff2c8) at /home/alexey/pcipassthru/qemu-impreza/vl.c:4062 (gdb) up #3 0x0000000010260058 in type_get_parent (type=0x10f7b260) at /home/alexey/pcipassthru/qemu-impreza/qom/object.c:152 152 g_assert(type->parent_type != NULL); (gdb) p *type $5 = {name = 0x10f7b3e0 "MPC8641-powerpc64-cpu", class_size = 0x0, instance_size = 0x0, class_init = @0x1069ac10: 0x103a287c <CPU_POWERPC_e600_POWERPC_SVR_8641_e600_cpu_class_init>, class_base_init = 0x0, class_finalize = 0x0, class_data = 0x0, instance_init = 0x0, instance_finalize = 0x0, abstract = 0x0, parent = 0x10f7b400 "e600-family-powerpc64-cpu", parent_type = 0x0, class = 0x0, num_interfaces = 0x0, interfaces = {{ typename = 0x0} <repeats 32 times>}} (gdb)
2013/6/24 Alexey Kardashevskiy <aik@ozlabs.ru>: > On 06/21/2013 10:03 PM, Alexander Graf wrote: >> >> On 21.06.2013, at 14:01, Julio Guerra wrote: >> >>> 2013/6/21 Alexander Graf <agraf@suse.de>: >>>> >>>> On 26.05.2013, at 19:41, Julio Guerra wrote: >>>> >>>>> MPC86xx processors are based on the e600 core, which is not the case >>>>> in qemu where it is based on the 7400 processor. >>>>> >>>>> This patch creates the e600 core and instantiates the MPC86xx >>>>> processors based on it. Therefore, adding the high BATs and the SPRG >>>>> 4..7 registers, which are e600-specific [1]. >>>>> >>>>> This allows to define the MPC8610 processor too and my program running >>>>> on a real MPC8610 target is now able to run on qemu :) >>>>> >>>>> [1] http://cache.freescale.com/files/32bit/doc/ref_manual/E600CORERM.pdf >>>>> >>>>> Signed-off-by: Julio Guerra <guerr@julio.in> >>>> >>>> Thanks, applied to ppc-next. >>>> >>> >>> I just retested this patch and I noticed the `handle_mmu_fault` >>> default value introduced by recent A. Farber patches on the CPU >>> definitions is wrong with the selected memory model. Thus qemu >>> complains about the MMU model. >>> >>> The following is missing in e600 CPU definition: >>>> #if defined(CONFIG_SOFTMMU) >>>> ppc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; >>>> #endif >>> >>> Can you correct it or should I resend a patch (v3 or just the previous >>> three lines) ? >> >> Just send a patch on top of the current one. > > > I do not really understand what this patch actually does but it breaks my > pseries/power7 setup. Please, help. > > > Starting program: /home/aik/qemu-system-ppc64 -L qemu-ppc64-bios/ -trace > events=qemu_trace_events -net nic,model=e1000,addr=0:0:0 -net > user,hostfwd=tcp::5000-:22 -m 1024 -machine pseries -nographic -vga none > -enable-kvm -kernel guest.vmlinux.n -initrd 1.cpio > [Thread debugging using libthread_db enabled] > Using host libthread_db library "/lib64/libthread_db.so.1". > ** > ERROR:/home/alexey/pcipassthru/qemu-impreza/qom/object.c:152:type_get_parent: > assertion failed: (type->parent_type != NULL) > > Breakpoint 4, 0x00000080c6eefb8c in .abort () from /lib64/libc.so.6 > Missing separate debuginfos, use: debuginfo-install SDL-1.2.15-8.fc19.ppc64 > bluez-libs-4.101-6.fc19.ppc64 boost-system-1.53.0-6.fc19.ppc64 > boost-thread-1.53.0-6.fc19.ppc64 brlapi-0.6.0-5.fc19.ppc64 > ceph-devel-0.56.4-1.fc19.ppc64 ceph-libs-0.56.4-1.fc19.ppc64 > cryptopp-5.6.2-2.fc19.ppc64 cyrus-sasl-lib-2.1.26-8.fc19.ppc64p7 > glib2-2.36.2-1.fc19.ppc64 glibc-2.17-4.fc19.ppc64p7 > glusterfs-3.4.0-0.5.beta2.fc19.ppc64 > glusterfs-api-3.4.0-0.5.beta2.fc19.ppc64 gmp-5.1.1-2.fc19.ppc64 > gnutls-3.1.11-1.fc19.ppc64 keyutils-libs-1.5.5-4.fc19.ppc64 > krb5-libs-1.11.2-10.fc19.ppc64 leveldb-1.9.0-1.fc19.ppc64 > libX11-1.5.99.902-1.fc19.ppc64 libXau-1.0.6-7.fc19.ppc64 > libcom_err-1.42.7-2.fc19.ppc64 libcurl-7.29.0-6.fc19.ppc64 > libfdt-1.3.0-6.fc19.ppc64 libgcc-4.8.0-8.fc19.ppc64 > libgcrypt-1.5.2-1.fc19.ppc64 libgpg-error-1.11-1.fc19.ppc64 > libidn-1.26-2.fc19.ppc64 libjpeg-turbo-1.2.90-2.fc19.ppc64 > libselinux-2.1.13-15.fc19.ppc64 libssh2-1.4.3-4.fc19.ppc64 > libstdc++-4.8.0-8.fc19.ppc64 libtasn1-3.3-1.fc19.ppc64 > libuuid-2.23.1-2.fc19.ppc64 libxcb-1.9-3.fc19.ppc64 > ncurses-libs-5.9-11.20130511.fc19.ppc64 nettle-2.6-2.fc19.ppc64 > nspr-4.9.6-1.fc19.ppc64 nss-3.14.3-13.0.fc19.ppc64 > nss-softokn-freebl-3.14.3-1.fc19.ppc64 nss-util-3.14.3-1.fc19.ppc64 > openldap-2.4.35-4.fc19.ppc64 openssl-libs-1.0.1e-4.fc19.ppc64p7 > p11-kit-0.18.3-1.fc19.ppc64 pcre-8.32-6.fc19.ppc64p7 > pixman-0.30.0-1.fc19.ppc64 snappy-1.1.0-1.fc19.ppc64 zlib-1.2.7-10.fc19.ppc64p7 > (gdb) up > #1 0x00000080c742d54c in .g_assertion_message () from /lib64/libglib-2.0.so.0 > (gdb) > #2 0x00000080c742d5f4 in .g_assertion_message_expr () from > /lib64/libglib-2.0.so.0 > (gdb) bt > #0 0x00000080c6eefb8c in .abort () from /lib64/libc.so.6 > #1 0x00000080c742d54c in .g_assertion_message () from /lib64/libglib-2.0.so.0 > #2 0x00000080c742d5f4 in .g_assertion_message_expr () from > /lib64/libglib-2.0.so.0 > #3 0x0000000010260058 in type_get_parent (type=0x10f7b260) > at /home/alexey/pcipassthru/qemu-impreza/qom/object.c:152 > #4 0x0000000010260120 in type_class_get_size (ti=0x10f7b260) > at /home/alexey/pcipassthru/qemu-impreza/qom/object.c:170 > #5 0x00000000102603d8 in type_initialize (ti=0x10f7b260) > at /home/alexey/pcipassthru/qemu-impreza/qom/object.c:236 > #6 0x000000001026175c in object_class_foreach_tramp (key=0x10f7b3e0, > value=0x10f7b260, > opaque=0x3fffffffe5e0) at > /home/alexey/pcipassthru/qemu-impreza/qom/object.c:626 > #7 0x00000080c73e0ab0 in .g_hash_table_foreach () from /lib64/libglib-2.0.so.0 > #8 0x000000001026188c in object_class_foreach (fn= > @0x10681290: 0x10261988 <object_class_get_list_tramp>, > implements_type=0x105c7188 "powerpc64-cpu", include_abstract=0x0, > opaque=0x3fffffffe680) > at /home/alexey/pcipassthru/qemu-impreza/qom/object.c:647 > #9 0x0000000010261a3c in object_class_get_list (implements_type=0x105c7188 > "powerpc64-cpu", > include_abstract=0x0) at > /home/alexey/pcipassthru/qemu-impreza/qom/object.c:679 > #10 0x0000000010459dec in ppc_cpu_class_by_pvr (pvr=0x3f0201) > at /home/alexey/pcipassthru/qemu-impreza/target-ppc/translate_init.c:7908 > #11 0x00000000103ca368 in kvm_ppc_register_host_cpu_type () > at /home/alexey/pcipassthru/qemu-impreza/target-ppc/kvm.c:1781 > #12 0x00000000103c4fcc in kvm_arch_init (s=0x10fb8ab0) > at /home/alexey/pcipassthru/qemu-impreza/target-ppc/kvm.c:110 > #13 0x0000000010376138 in kvm_init () at > /home/alexey/pcipassthru/qemu-impreza/kvm-all.c:1461 > #14 0x00000000102c1b08 in configure_accelerator () > at /home/alexey/pcipassthru/qemu-impreza/vl.c:2673 > #15 0x00000000102c5e28 in main (argc=0x15, argv=0x3ffffffff218, > envp=0x3ffffffff2c8) > at /home/alexey/pcipassthru/qemu-impreza/vl.c:4062 > (gdb) up > #3 0x0000000010260058 in type_get_parent (type=0x10f7b260) > at /home/alexey/pcipassthru/qemu-impreza/qom/object.c:152 > 152 g_assert(type->parent_type != NULL); > (gdb) p *type > $5 = {name = 0x10f7b3e0 "MPC8641-powerpc64-cpu", class_size = 0x0, > instance_size = 0x0, > class_init = @0x1069ac10: 0x103a287c > <CPU_POWERPC_e600_POWERPC_SVR_8641_e600_cpu_class_init>, > class_base_init = 0x0, class_finalize = 0x0, class_data = 0x0, > instance_init = 0x0, > instance_finalize = 0x0, abstract = 0x0, parent = 0x10f7b400 > "e600-family-powerpc64-cpu", > parent_type = 0x0, class = 0x0, num_interfaces = 0x0, interfaces = {{ > typename = 0x0} <repeats 32 times>}} > (gdb) > > As Alexander said, this patch is broken and incomplete, it has not been mainstreamed. A v3 will be re-submitted today, I'll let you know so that you can test your setup again. But to answer your question, MPC8641 board is - with this patch - instantiated with an e600 CPU whose TLBs are hardware or software reloadable. I don't know how it is handled in kvm mode, maybe it is due to the missing `mmu_fault_handler` that will be present in v3. -- Julio Guerra
Am 24.06.2013 um 08:13 schrieb Julio Guerra <guerr@julio.in>: > 2013/6/24 Alexey Kardashevskiy <aik@ozlabs.ru>: >> On 06/21/2013 10:03 PM, Alexander Graf wrote: >>> >>> On 21.06.2013, at 14:01, Julio Guerra wrote: >>> >>>> 2013/6/21 Alexander Graf <agraf@suse.de>: >>>>> >>>>> On 26.05.2013, at 19:41, Julio Guerra wrote: >>>>> >>>>>> MPC86xx processors are based on the e600 core, which is not the case >>>>>> in qemu where it is based on the 7400 processor. >>>>>> >>>>>> This patch creates the e600 core and instantiates the MPC86xx >>>>>> processors based on it. Therefore, adding the high BATs and the SPRG >>>>>> 4..7 registers, which are e600-specific [1]. >>>>>> >>>>>> This allows to define the MPC8610 processor too and my program running >>>>>> on a real MPC8610 target is now able to run on qemu :) >>>>>> >>>>>> [1] http://cache.freescale.com/files/32bit/doc/ref_manual/E600CORERM.pdf >>>>>> >>>>>> Signed-off-by: Julio Guerra <guerr@julio.in> >>>>> >>>>> Thanks, applied to ppc-next. >>>> >>>> I just retested this patch and I noticed the `handle_mmu_fault` >>>> default value introduced by recent A. Farber patches on the CPU >>>> definitions is wrong with the selected memory model. Thus qemu >>>> complains about the MMU model. >>>> >>>> The following is missing in e600 CPU definition: >>>>> #if defined(CONFIG_SOFTMMU) >>>>> ppc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; >>>>> #endif >>>> >>>> Can you correct it or should I resend a patch (v3 or just the previous >>>> three lines) ? >>> >>> Just send a patch on top of the current one. >> >> >> I do not really understand what this patch actually does but it breaks my >> pseries/power7 setup. Please, help. >> >> >> Starting program: /home/aik/qemu-system-ppc64 -L qemu-ppc64-bios/ -trace >> events=qemu_trace_events -net nic,model=e1000,addr=0:0:0 -net >> user,hostfwd=tcp::5000-:22 -m 1024 -machine pseries -nographic -vga none >> -enable-kvm -kernel guest.vmlinux.n -initrd 1.cpio >> [Thread debugging using libthread_db enabled] >> Using host libthread_db library "/lib64/libthread_db.so.1". >> ** >> ERROR:/home/alexey/pcipassthru/qemu-impreza/qom/object.c:152:type_get_parent: >> assertion failed: (type->parent_type != NULL) >> >> Breakpoint 4, 0x00000080c6eefb8c in .abort () from /lib64/libc.so.6 >> Missing separate debuginfos, use: debuginfo-install SDL-1.2.15-8.fc19.ppc64 >> bluez-libs-4.101-6.fc19.ppc64 boost-system-1.53.0-6.fc19.ppc64 >> boost-thread-1.53.0-6.fc19.ppc64 brlapi-0.6.0-5.fc19.ppc64 >> ceph-devel-0.56.4-1.fc19.ppc64 ceph-libs-0.56.4-1.fc19.ppc64 >> cryptopp-5.6.2-2.fc19.ppc64 cyrus-sasl-lib-2.1.26-8.fc19.ppc64p7 >> glib2-2.36.2-1.fc19.ppc64 glibc-2.17-4.fc19.ppc64p7 >> glusterfs-3.4.0-0.5.beta2.fc19.ppc64 >> glusterfs-api-3.4.0-0.5.beta2.fc19.ppc64 gmp-5.1.1-2.fc19.ppc64 >> gnutls-3.1.11-1.fc19.ppc64 keyutils-libs-1.5.5-4.fc19.ppc64 >> krb5-libs-1.11.2-10.fc19.ppc64 leveldb-1.9.0-1.fc19.ppc64 >> libX11-1.5.99.902-1.fc19.ppc64 libXau-1.0.6-7.fc19.ppc64 >> libcom_err-1.42.7-2.fc19.ppc64 libcurl-7.29.0-6.fc19.ppc64 >> libfdt-1.3.0-6.fc19.ppc64 libgcc-4.8.0-8.fc19.ppc64 >> libgcrypt-1.5.2-1.fc19.ppc64 libgpg-error-1.11-1.fc19.ppc64 >> libidn-1.26-2.fc19.ppc64 libjpeg-turbo-1.2.90-2.fc19.ppc64 >> libselinux-2.1.13-15.fc19.ppc64 libssh2-1.4.3-4.fc19.ppc64 >> libstdc++-4.8.0-8.fc19.ppc64 libtasn1-3.3-1.fc19.ppc64 >> libuuid-2.23.1-2.fc19.ppc64 libxcb-1.9-3.fc19.ppc64 >> ncurses-libs-5.9-11.20130511.fc19.ppc64 nettle-2.6-2.fc19.ppc64 >> nspr-4.9.6-1.fc19.ppc64 nss-3.14.3-13.0.fc19.ppc64 >> nss-softokn-freebl-3.14.3-1.fc19.ppc64 nss-util-3.14.3-1.fc19.ppc64 >> openldap-2.4.35-4.fc19.ppc64 openssl-libs-1.0.1e-4.fc19.ppc64p7 >> p11-kit-0.18.3-1.fc19.ppc64 pcre-8.32-6.fc19.ppc64p7 >> pixman-0.30.0-1.fc19.ppc64 snappy-1.1.0-1.fc19.ppc64 zlib-1.2.7-10.fc19.ppc64p7 >> (gdb) up >> #1 0x00000080c742d54c in .g_assertion_message () from /lib64/libglib-2.0.so.0 >> (gdb) >> #2 0x00000080c742d5f4 in .g_assertion_message_expr () from >> /lib64/libglib-2.0.so.0 >> (gdb) bt >> #0 0x00000080c6eefb8c in .abort () from /lib64/libc.so.6 >> #1 0x00000080c742d54c in .g_assertion_message () from /lib64/libglib-2.0.so.0 >> #2 0x00000080c742d5f4 in .g_assertion_message_expr () from >> /lib64/libglib-2.0.so.0 >> #3 0x0000000010260058 in type_get_parent (type=0x10f7b260) >> at /home/alexey/pcipassthru/qemu-impreza/qom/object.c:152 >> #4 0x0000000010260120 in type_class_get_size (ti=0x10f7b260) >> at /home/alexey/pcipassthru/qemu-impreza/qom/object.c:170 >> #5 0x00000000102603d8 in type_initialize (ti=0x10f7b260) >> at /home/alexey/pcipassthru/qemu-impreza/qom/object.c:236 >> #6 0x000000001026175c in object_class_foreach_tramp (key=0x10f7b3e0, >> value=0x10f7b260, >> opaque=0x3fffffffe5e0) at >> /home/alexey/pcipassthru/qemu-impreza/qom/object.c:626 >> #7 0x00000080c73e0ab0 in .g_hash_table_foreach () from /lib64/libglib-2.0.so.0 >> #8 0x000000001026188c in object_class_foreach (fn= >> @0x10681290: 0x10261988 <object_class_get_list_tramp>, >> implements_type=0x105c7188 "powerpc64-cpu", include_abstract=0x0, >> opaque=0x3fffffffe680) >> at /home/alexey/pcipassthru/qemu-impreza/qom/object.c:647 >> #9 0x0000000010261a3c in object_class_get_list (implements_type=0x105c7188 >> "powerpc64-cpu", >> include_abstract=0x0) at >> /home/alexey/pcipassthru/qemu-impreza/qom/object.c:679 >> #10 0x0000000010459dec in ppc_cpu_class_by_pvr (pvr=0x3f0201) >> at /home/alexey/pcipassthru/qemu-impreza/target-ppc/translate_init.c:7908 >> #11 0x00000000103ca368 in kvm_ppc_register_host_cpu_type () >> at /home/alexey/pcipassthru/qemu-impreza/target-ppc/kvm.c:1781 >> #12 0x00000000103c4fcc in kvm_arch_init (s=0x10fb8ab0) >> at /home/alexey/pcipassthru/qemu-impreza/target-ppc/kvm.c:110 >> #13 0x0000000010376138 in kvm_init () at >> /home/alexey/pcipassthru/qemu-impreza/kvm-all.c:1461 >> #14 0x00000000102c1b08 in configure_accelerator () >> at /home/alexey/pcipassthru/qemu-impreza/vl.c:2673 >> #15 0x00000000102c5e28 in main (argc=0x15, argv=0x3ffffffff218, >> envp=0x3ffffffff2c8) >> at /home/alexey/pcipassthru/qemu-impreza/vl.c:4062 >> (gdb) up >> #3 0x0000000010260058 in type_get_parent (type=0x10f7b260) >> at /home/alexey/pcipassthru/qemu-impreza/qom/object.c:152 >> 152 g_assert(type->parent_type != NULL); >> (gdb) p *type >> $5 = {name = 0x10f7b3e0 "MPC8641-powerpc64-cpu", class_size = 0x0, >> instance_size = 0x0, >> class_init = @0x1069ac10: 0x103a287c >> <CPU_POWERPC_e600_POWERPC_SVR_8641_e600_cpu_class_init>, >> class_base_init = 0x0, class_finalize = 0x0, class_data = 0x0, >> instance_init = 0x0, >> instance_finalize = 0x0, abstract = 0x0, parent = 0x10f7b400 >> "e600-family-powerpc64-cpu", >> parent_type = 0x0, class = 0x0, num_interfaces = 0x0, interfaces = {{ >> typename = 0x0} <repeats 32 times>}} >> (gdb) > > As Alexander said, this patch is broken and incomplete, it has not > been mainstreamed. A v3 will be re-submitted today, I'll let you know > so that you can test your setup again. > > But to answer your question, MPC8641 board is - with this patch - > instantiated with an e600 CPU whose TLBs are hardware or software > reloadable. I don't know how it is handled in kvm mode, maybe it is > due to the missing `mmu_fault_handler` that will be present in v3. No, this is QOM. With thr broken patch we add a CPU of class type "e600", but no class "e600". Alex > > -- > Julio Guerra
diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c index 17f56b7..8a2ab50 100644 --- a/target-ppc/cpu-models.c +++ b/target-ppc/cpu-models.c @@ -792,17 +792,15 @@ POWERPC_DEF_SVR("MPC8572E", "MPC8572E", CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2) /* e600 family */ - POWERPC_DEF("e600", CPU_POWERPC_e600, 7400, + POWERPC_DEF("e600", CPU_POWERPC_e600, e600, "PowerPC e600 core") /* PowerPC e600 microcontrollers */ -#if defined(TODO) POWERPC_DEF_SVR("MPC8610", "MPC8610", - CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400) -#endif + CPU_POWERPC_MPC8610, POWERPC_SVR_8610, e600) POWERPC_DEF_SVR("MPC8641", "MPC8641", - CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400) + CPU_POWERPC_MPC8641, POWERPC_SVR_8641, e600) POWERPC_DEF_SVR("MPC8641D", "MPC8641D", - CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400) + CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, e600) /* 32 bits "classic" PowerPC */ /* PowerPC 6xx family */ POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601, diff --git a/target-ppc/cpu-models.h b/target-ppc/cpu-models.h index a94f835..8ba96bb 100644 --- a/target-ppc/cpu-models.h +++ b/target-ppc/cpu-models.h @@ -731,9 +731,7 @@ enum { POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500, POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500, POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500, -#if 0 - POWERPC_SVR_8610 = xxx, -#endif + POWERPC_SVR_8610 = 0x80A00011, POWERPC_SVR_8641 = 0x80900021, POWERPC_SVR_8641D = 0x80900121, }; diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 021a31e..916fe0d 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -6525,2 +6525,2 @@ POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) POWERPC_FLAG_BUS_CLK; }
MPC86xx processors are based on the e600 core, which is not the case in qemu where it is based on the 7400 processor. This patch creates the e600 core and instantiates the MPC86xx processors based on it. Therefore, adding the high BATs and the SPRG 4..7 registers, which are e600-specific [1]. This allows to define the MPC8610 processor too and my program running on a real MPC8610 target is now able to run on qemu :) [1] http://cache.freescale.com/files/32bit/doc/ref_manual/E600CORERM.pdf Signed-off-by: Julio Guerra <guerr@julio.in> --- target-ppc/cpu-models.c | 10 ++-- target-ppc/cpu-models.h | 4 +- target-ppc/translate_init.c | 122 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 127 insertions(+), 9 deletions(-) +static void init_proc_e600(CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_7xx(env); + /* Time base */ + gen_tbl(env); + /* 74xx specific SPR */ + gen_spr_74xx(env); + /* XXX : not implemented */ + spr_register(env, SPR_UBAMR, "UBAMR", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_LDSTCR, "LDSTCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_ICTRL, "ICTRL", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MSSSR0, "MSSSR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_PMC5, "PMC5", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_UPMC5, "UPMC5", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_PMC6, "PMC6", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_UPMC6, "UPMC6", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* SPRGs */ + spr_register(env, SPR_SPRG4, "SPRG4", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_USPRG4, "USPRG4", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_SPRG5, "SPRG5", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_USPRG5, "USPRG5", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_SPRG6, "SPRG6", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_USPRG6, "USPRG6", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_SPRG7, "SPRG7", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_USPRG7, "USPRG7", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + gen_high_BATs(env); + gen_74xx_soft_tlb(env, 128, 2); + init_excp_7450(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env); +} + +POWERPC_FAMILY(e600)(ObjectClass* oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC e600"; + pcc->init_proc = init_proc_e600; + pcc->check_pow = check_pow_hid0_74xx; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | + PPC_FLOAT_STFIWX | + PPC_CACHE | PPC_CACHE_ICBI | + PPC_CACHE_DCBA | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | + PPC_MEM_TLBIA | PPC_74xx_TLB | + PPC_SEGMENT | PPC_EXTERN | + PPC_ALTIVEC; + pcc->insns_flags2 = PPC_NONE; + pcc->msr_mask = 0x000000000205FF77ULL; + pcc->mmu_model = POWERPC_MMU_32B; + pcc->excp_model = POWERPC_EXCP_74xx; + pcc->bus_model = PPC_FLAGS_INPUT_6xx; + pcc->bfd_mach = bfd_mach_ppc_7400; + pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | + POWERPC_FLAG_BE | POWERPC_FLAG_PMM | + POWERPC_FLAG_BUS_CLK; +} + #if defined (TARGET_PPC64) #if defined(CONFIG_USER_ONLY) #define POWERPC970_HID5_INIT 0x00000080 -- 1.8.1.4