| Message ID | CAKdSQZm-pwozsgxgmFxpQeX4y=Vw6e3LfAyWGHMegYfPOH3G4Q@mail.gmail.com |
|---|---|
| State | New |
| Headers | show |
On Tue, Jun 11, 2013 at 09:39:24AM +0400, Igor Zamyatin wrote: > Please see updated patch. > > Is it ok to install? Ok, thanks. > 2013-06-11 Igor Zamyatin <igor.zamyatin@intel.com> > > * doc/invoke.texi (core-avx2): Document. > (slm): Likewise. > (atom): Updated with MOVBE. Jakub
> Ok, thanks. > Checked into MT: http://gcc.gnu.org/ml/gcc-cvs/2013-06/msg00376.html I think we also should port core-avx2 into 4.8.x Thanks, K
On Tue, Jun 11, 2013 at 01:42:47PM +0400, Kirill Yukhin wrote: > > Ok, thanks. > > > Checked into MT: http://gcc.gnu.org/ml/gcc-cvs/2013-06/msg00376.html > I think we also should port core-avx2 into 4.8.x If you mean the documentation of it plus atom MOVBE listing, yes. Patch preapproved. Jakub
> Patch preapproved.
Checked into 4.8 branch:
http://gcc.gnu.org/ml/gcc-cvs/2013-06/msg00648.html
Thanks, K
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index b7b32f7..dd82880 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -13833,10 +13833,19 @@ Intel Core CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AES, PCLMUL, FSGSBASE, RDRND and F16C instruction set support. +@item core-avx2 +Intel Core CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2 +and F16C instruction set support. + @item atom -Intel Atom CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3 +Intel Atom CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3 instruction set support. +@item slm +Intel Silvermont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1 and SSE4.2 instruction set support. + @item k6
Please see updated patch. Is it ok to install? Thanks, Igor Changelog: 2013-06-11 Igor Zamyatin <igor.zamyatin@intel.com> * doc/invoke.texi (core-avx2): Document. (slm): Likewise. (atom): Updated with MOVBE. AMD K6 CPU with MMX instruction set support. On Mon, Jun 10, 2013 at 5:29 PM, Jakub Jelinek <jakub@redhat.com> wrote: > On Mon, Jun 10, 2013 at 05:25:36PM +0400, Igor Zamyatin wrote: >> Following patch documents Intel Silvermont support. >> >> OK to install? >> >> 2013-06-10 Igor Zamyatin <igor.zamyatin@intel.com> >> >> * doc/invoke.texi: Document slm. >> >> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi >> index b7b32f7..e4f1d45 100644 >> --- a/gcc/doc/invoke.texi >> +++ b/gcc/doc/invoke.texi >> @@ -13837,6 +13837,10 @@ set support. >> Intel Atom CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3 >> instruction set support. >> >> +@item slm >> +Intel Silvermont CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3, >> +SSE4.1, SSE4.2 instruction set support. > > Shouldn't it also list MOVBE (similarly for atom and core-avx2, btver2 > already lists it). > > core-avx2 isn't even documented at all in invoke.texi. > > Jakub