| Message ID | 1350557795-31487-2-git-send-email-ldewangan@nvidia.com |
|---|---|
| State | Superseded, archived |
| Headers | show |
On 10/18/2012 04:56 AM, Laxman Dewangan wrote: > Add base address of all slink controller of Tegra20 > and tegra30. Lets not add anything to iomap.h; we're trying to remove it. Instead, just put the raw address in the AUXDATA; I assume that's the only place these defines end up being used... -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Friday 19 October 2012 04:09 AM, Stephen Warren wrote: > On 10/18/2012 04:56 AM, Laxman Dewangan wrote: >> Add base address of all slink controller of Tegra20 >> and tegra30. > Lets not add anything to iomap.h; we're trying to remove it. Instead, > just put the raw address in the AUXDATA; I assume that's the only place > these defines end up being used... OK, I will drop this change and add the base address definition in the AUXDATA file only. -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h index fee3a94..0f46765 100644 --- a/arch/arm/mach-tegra/include/mach/iomap.h +++ b/arch/arm/mach-tegra/include/mach/iomap.h @@ -206,17 +206,23 @@ #define TEGRA_DVC_BASE 0x7000D000 #define TEGRA_DVC_SIZE SZ_512 -#define TEGRA_SPI1_BASE 0x7000D400 -#define TEGRA_SPI1_SIZE SZ_512 +#define TEGRA_SLINK1_BASE 0x7000D400 +#define TEGRA_SLINK1_SIZE SZ_512 -#define TEGRA_SPI2_BASE 0x7000D600 -#define TEGRA_SPI2_SIZE SZ_512 +#define TEGRA_SLINK2_BASE 0x7000D600 +#define TEGRA_SLINK2_SIZE SZ_512 -#define TEGRA_SPI3_BASE 0x7000D800 -#define TEGRA_SPI3_SIZE SZ_512 +#define TEGRA_SLINK3_BASE 0x7000D800 +#define TEGRA_SLINK3_SIZE SZ_512 -#define TEGRA_SPI4_BASE 0x7000DA00 -#define TEGRA_SPI4_SIZE SZ_512 +#define TEGRA_SLINK4_BASE 0x7000DA00 +#define TEGRA_SLINK4_SIZE SZ_512 + +#define TEGRA_SLINK5_BASE 0x7000DC00 +#define TEGRA_SLINK5_SIZE SZ_512 + +#define TEGRA_SLINK6_BASE 0x7000DE00 +#define TEGRA_SLINK6_SIZE SZ_512 #define TEGRA_RTC_BASE 0x7000E000 #define TEGRA_RTC_SIZE SZ_256
Add base address of all slink controller of Tegra20 and tegra30. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> --- arch/arm/mach-tegra/include/mach/iomap.h | 22 ++++++++++++++-------- 1 files changed, 14 insertions(+), 8 deletions(-)