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[2/2] mips-linux-user: Always support rdhwr.

Message ID 1333127797-8133-3-git-send-email-rth@twiddle.net
State New
Headers show

Commit Message

Richard Henderson March 30, 2012, 5:16 p.m. UTC
The kernel will emulate this instruction if it's not supported
natively.  This insn is used for TLS, among other things, and
so is required by modern glibc.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Cc: Riku Voipio <riku.voipio@iki.fi>
---
 target-mips/translate.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

Comments

Aurelien Jarno Aug. 27, 2012, 10:20 a.m. UTC | #1
On Fri, Mar 30, 2012 at 01:16:37PM -0400, Richard Henderson wrote:
> The kernel will emulate this instruction if it's not supported
> natively.  This insn is used for TLS, among other things, and
> so is required by modern glibc.
> 
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> Cc: Riku Voipio <riku.voipio@iki.fi>
> ---
>  target-mips/translate.c |    4 ++++
>  1 files changed, 4 insertions(+), 0 deletions(-)
> 
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 300d95e..ed28ca8 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -8111,7 +8111,11 @@ gen_rdhwr (CPUMIPSState *env, DisasContext *ctx, int rt, int rd)
>  {
>      TCGv t0;
>  
> +#if !defined(CONFIG_USER_ONLY)
> +    /* The Linux kernel will emulate rdhwr if it's not supported natively.
> +       Therefore only check the ISA in system mode.  */
>      check_insn(env, ctx, ISA_MIPS32R2);
> +#endif
>      t0 = tcg_temp_new();
>  
>      switch (rd) {

Thanks, applied.
diff mbox

Patch

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 300d95e..ed28ca8 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -8111,7 +8111,11 @@  gen_rdhwr (CPUMIPSState *env, DisasContext *ctx, int rt, int rd)
 {
     TCGv t0;
 
+#if !defined(CONFIG_USER_ONLY)
+    /* The Linux kernel will emulate rdhwr if it's not supported natively.
+       Therefore only check the ISA in system mode.  */
     check_insn(env, ctx, ISA_MIPS32R2);
+#endif
     t0 = tcg_temp_new();
 
     switch (rd) {