| Message ID | 20120510172918.13418.64781.stgit@dusk |
|---|---|
| State | New |
| Headers | show |
On Thu, May 10, 2012 at 11:29:19AM -0600, Paul Walmsley wrote: > During kernel init, the AM3505/AM3517 UART4 cannot complete its softreset: > > omap_hwmod: uart4: softreset failed (waited 10000 usec) > > This also results in another warning later in the boot process: > > omap_hwmod: uart4: enabled state can only be entered from initialized, idle, or disabled state > > >From empirical observation, the AM35xx UART4 IP block requires either > uart1_fck or uart2_fck to be enabled while UART4 resets. Otherwise > the reset will never complete. So this patch adds uart1_fck as an > optional clock for UART4 and adds the appropriate hwmod flag to cause > uart1_fck to be enabled during the reset process. (The choice of > uart1_fck over uart2_fck was arbitrary.) > > Unfortunately this observation raises many questions. Is it necessary > for uart1_fck or uart2_fck to be controlled with uart4_fck for the > UART4 to work correctly? What exactly do the AM35xx UART4 clock > tree and the related PRCM idle management FSMs look like? If anyone > has the ability to answer these questions through empirical functional > testing, or hardware information from the AM35xx designers, it would > be greatly appreciated. > > Cc: Benoît Cousson <b-cousson@ti.com> > Cc: Kyle Manna <kyle.manna@fuel7.com> > Cc: Mark A. Greer <mgreer@animalcreek.com> > Cc: Ranjith Lohithakshan <ranjithl@ti.com> > Signed-off-by: Paul Walmsley <paul@pwsan.com> Acked-by: Mark A. Greer <mgreer@animalcreek.com> (on an am3517evm) Mark
Hi Paul, On 5/10/2012 7:29 PM, Paul Walmsley wrote: > During kernel init, the AM3505/AM3517 UART4 cannot complete its softreset: > > omap_hwmod: uart4: softreset failed (waited 10000 usec) > > This also results in another warning later in the boot process: > > omap_hwmod: uart4: enabled state can only be entered from initialized, idle, or disabled state > >> From empirical observation, the AM35xx UART4 IP block requires either > uart1_fck or uart2_fck to be enabled while UART4 resets. Otherwise > the reset will never complete. So this patch adds uart1_fck as an > optional clock for UART4 and adds the appropriate hwmod flag to cause > uart1_fck to be enabled during the reset process. (The choice of > uart1_fck over uart2_fck was arbitrary.) > > Unfortunately this observation raises many questions. Is it necessary > for uart1_fck or uart2_fck to be controlled with uart4_fck for the > UART4 to work correctly? What exactly do the AM35xx UART4 clock > tree and the related PRCM idle management FSMs look like? If anyone > has the ability to answer these questions through empirical functional > testing, or hardware information from the AM35xx designers, it would > be greatly appreciated. I do not have any clue about that chip, but is this clock really what it is supposed to be? I mean, isn't the uart1_fck the parent of all the UART fck or something like that. Don't we just have an issue becasue the clock names are not accurate? Regards, Benoit > > Cc: Benoît Cousson<b-cousson@ti.com> > Cc: Kyle Manna<kyle.manna@fuel7.com> > Cc: Mark A. Greer<mgreer@animalcreek.com> > Cc: Ranjith Lohithakshan<ranjithl@ti.com> > Signed-off-by: Paul Walmsley<paul@pwsan.com> > --- > arch/arm/mach-omap2/clock3xxx_data.c | 8 ++++++-- > arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 17 +++++++++++++++++ > 2 files changed, 23 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c > index 11644bf..12c64db 100644 > --- a/arch/arm/mach-omap2/clock3xxx_data.c > +++ b/arch/arm/mach-omap2/clock3xxx_data.c > @@ -3201,8 +3201,12 @@ static struct clk vpfe_fck = { > }; > > /* > - * The UART1/2 functional clock acts as the functional > - * clock for UART4. No separate fclk control available. > + * The UART1/2 functional clock acts as the functional clock for > + * UART4. No separate fclk control available. XXX Well now we have a > + * uart4_fck that is apparently used as the UART4 functional clock, > + * but it also seems that uart1_fck or uart2_fck are still needed, at > + * least for UART4 softresets to complete. This really needs > + * clarification. > */ > static struct clk uart4_ick_am35xx = { > .name = "uart4_ick", > diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c > index c939131..c6653a80 100644 > --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c > +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c > @@ -535,6 +535,20 @@ static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { > { .dma_req = -1 } > }; > > +/* > + * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or > + * uart2_fck being enabled. So we add uart1_fck as an optional clock, > + * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really > + * should not be needed. The functional clock structure of the AM35xx > + * UART4 is extremely unclear and opaque; it is unclear what the role > + * of uart1/2_fck is for the UART4. Any clarification from either > + * empirical testing or the AM3505/3517 hardware designers would be > + * most welcome. > + */ > +static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = { > + { .role = "softreset_uart1_fck", .clk = "uart1_fck" }, > +}; > + > static struct omap_hwmod am35xx_uart4_hwmod = { > .name = "uart4", > .mpu_irqs = am35xx_uart4_mpu_irqs, > @@ -549,6 +563,9 @@ static struct omap_hwmod am35xx_uart4_hwmod = { > .idlest_idle_bit = AM35XX_ST_UART4_SHIFT, > }, > }, > + .opt_clks = am35xx_uart4_opt_clks, > + .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks), > + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, > .class =&omap2_uart_class, > }; > > >
Hi Benoît On Fri, 11 May 2012, Cousson, Benoit wrote: > I do not have any clue about that chip, but is this clock really what it is > supposed to be? I mean, isn't the uart1_fck the parent of all the UART fck or > something like that. Don't we just have an issue becasue the clock names are > not accurate? I guess that's what I'm trying to find out. According to the AM3517 TRM rev. B (SPRUGR0B) Figure 14-20 "UART Functional Integration" and Table 14-11 "UART Clocks", all of the UARTs appear to have independent functional clocks. The table even mentions a CM_FCLKEN1_CORE.EN_UART4 bit. But the PRCM chapter of this TRM doesn't mention that at all. So the documentation is not too useful here. On the rest of the OMAPs, as far as I know, the UART clocks are all separate. - Paul
On 5/11/2012 11:22 AM, Paul Walmsley wrote: > Hi Benoît > > On Fri, 11 May 2012, Cousson, Benoit wrote: > >> I do not have any clue about that chip, but is this clock really what it is >> supposed to be? I mean, isn't the uart1_fck the parent of all the UART fck or >> something like that. Don't we just have an issue becasue the clock names are >> not accurate? > > I guess that's what I'm trying to find out. > > According to the AM3517 TRM rev. B (SPRUGR0B) Figure 14-20 "UART > Functional Integration" and Table 14-11 "UART Clocks", all of the UARTs > appear to have independent functional clocks. The table even mentions a > CM_FCLKEN1_CORE.EN_UART4 bit. But the PRCM chapter of this TRM doesn't > mention that at all. So the documentation is not too useful here. > > On the rest of the OMAPs, as far as I know, the UART clocks are all > separate. In fact, not really. The same PER_48M_GFCLK clock is used for every UART instances in OMAP4. We do have a separate modulemode for each UART but as far as clocks are concerned, the source clock is the same. Regards, Benoit
On Fri, 11 May 2012, Cousson, Benoit wrote: > On 5/11/2012 11:22 AM, Paul Walmsley wrote: > > > On the rest of the OMAPs, as far as I know, the UART clocks are all > > separate. > > In fact, not really. The same PER_48M_GFCLK clock is used for every UART > instances in OMAP4. We do have a separate modulemode for each UART but as far > as clocks are concerned, the source clock is the same. By "separate" I mean that they are all independently gated. This does not appear to be the case with AM3517. Or perhaps it is the case and something isn't right with the idle management FSMs. - Paul
On 5/11/2012 11:35 AM, Paul Walmsley wrote: > On Fri, 11 May 2012, Cousson, Benoit wrote: > >> On 5/11/2012 11:22 AM, Paul Walmsley wrote: >> >>> On the rest of the OMAPs, as far as I know, the UART clocks are all >>> separate. >> >> In fact, not really. The same PER_48M_GFCLK clock is used for every UART >> instances in OMAP4. We do have a separate modulemode for each UART but as far >> as clocks are concerned, the source clock is the same. > > By "separate" I mean that they are all independently gated. This does not > appear to be the case with AM3517. Or perhaps it is the case and > something isn't right with the idle management FSMs. But they are not separately gated for OMAP4 either. This is the modulemode trick that make us think that, but it just means that the PRCM should ensure that this clock is needed when at least one UART modulemode is enabled. In fact the SPI modules are using the same clock. The modulemode is used to do some reference counting, but the gating is done globally. It was the same with the FCK_EN and ICK_EN in OMAP2&3. The PRCM spec show only one global gating between FUNC_48M_FCLK and PER_48M_GFCLK. All the modules are sharing the exact same clock. Regards, Benoit
On Fri, 11 May 2012, Cousson, Benoit wrote: > But they are not separately gated for OMAP4 either. This is the modulemode > trick that make us think that, but it just means that the PRCM should ensure > that this clock is needed when at least one UART modulemode is enabled. In > fact the SPI modules are using the same clock. > > The modulemode is used to do some reference counting, but the gating is done > globally. It was the same with the FCK_EN and ICK_EN in OMAP2&3. > > The PRCM spec show only one global gating between FUNC_48M_FCLK and > PER_48M_GFCLK. All the modules are sharing the exact same clock. Well, on OMAP3 and AM3517, they do not all share the same clock. If you look at the 34xx TRM vZU Table 17-11 "UART Clocks", you can see that the UART1 and 2 functional clocks are sourced from clocks managed by the CORE clockdomain, while UART3 is sourced from clocks managed by the PER clockdomain. This is also expressed in our OMAP3 clock tree. I realize this is slightly tangential to your point. As to where the clock gating nodes are actually located on a given piece of silicon, unfortunately I have no way of confirming that, aside from power measurement. You might be correct about what's going on with the AM3517 but it would be nice to get some confirmation from the AM35xx PRCM engineer(s). At this point one of two possibilities seem likely: either CM_FCLKEN1_CORE.EN_UART4 does nothing, or CM_FCLKEN1_CORE.EN_UART4 is necessary but not sufficient to get the UART4 to work. If CM_FCLKEN1_CORE.EN_UART4 does not actually do anything then we need to remove it from the kernel and ideally file a documentation bug to get it removed from the TRM. On the other hand, if we do have to enable CM_FCLKEN1_CORE.EN_UART4 to deassert the IdleAck to UART4, but the PRCM usecounting is broken, then I guess we'll need to add a workaround to the hwmod code to essentially support multiple "main clocks". - Paul
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 11644bf..12c64db 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -3201,8 +3201,12 @@ static struct clk vpfe_fck = { }; /* - * The UART1/2 functional clock acts as the functional - * clock for UART4. No separate fclk control available. + * The UART1/2 functional clock acts as the functional clock for + * UART4. No separate fclk control available. XXX Well now we have a + * uart4_fck that is apparently used as the UART4 functional clock, + * but it also seems that uart1_fck or uart2_fck are still needed, at + * least for UART4 softresets to complete. This really needs + * clarification. */ static struct clk uart4_ick_am35xx = { .name = "uart4_ick", diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index c939131..c6653a80 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -535,6 +535,20 @@ static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { { .dma_req = -1 } }; +/* + * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or + * uart2_fck being enabled. So we add uart1_fck as an optional clock, + * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really + * should not be needed. The functional clock structure of the AM35xx + * UART4 is extremely unclear and opaque; it is unclear what the role + * of uart1/2_fck is for the UART4. Any clarification from either + * empirical testing or the AM3505/3517 hardware designers would be + * most welcome. + */ +static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = { + { .role = "softreset_uart1_fck", .clk = "uart1_fck" }, +}; + static struct omap_hwmod am35xx_uart4_hwmod = { .name = "uart4", .mpu_irqs = am35xx_uart4_mpu_irqs, @@ -549,6 +563,9 @@ static struct omap_hwmod am35xx_uart4_hwmod = { .idlest_idle_bit = AM35XX_ST_UART4_SHIFT, }, }, + .opt_clks = am35xx_uart4_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks), + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .class = &omap2_uart_class, };