diff mbox

[SH] Fold prefetch insns

Message ID 1333821195.19154.94.camel@yam-132-YW-E178-FTW
State New
Headers show

Commit Message

Oleg Endo April 7, 2012, 5:53 p.m. UTC 
Hi,

The attached patch folds the prefetch insns for SH4 and SH2A.
As far as I can see, there is no need to have two of them.
The patch also adapts the sh2a-prefetch test case to be ran for SH4,
too.

Tested by running said test case with 
make check-gcc RUNTESTFLAGS="sh.exp=prefetch* --target_board=sh-sim
\{-m2/-ml,-m2/-mb,-m2a/-mb,-m2a-single/-mb,-m4/-ml,-m4/-mb,
-m4-single/-ml,-m4-single/-mb,-m4a-single/-ml,-m4a-single/-mb}"

OK?

Cheers,
Oleg

ChangeLog:

	* config/sh/sh.md (*prefetch_i4, prefetch_m2a): Merge into ...
	(*prefetch): ... this new insn.

testsuite/ChangeLog:

	* gcc.target/sh/sh2a-prefetch.c: Rename to ...
	* gcc.target/sh/prefetch.c: ... this.  Enable test case for m4*.

Comments

Kaz Kojima April 7, 2012, 11:05 p.m. UTC | #1 
Oleg Endo <oleg.endo@t-online.de> wrote:
> The attached patch folds the prefetch insns for SH4 and SH2A.
> As far as I can see, there is no need to have two of them.
> The patch also adapts the sh2a-prefetch test case to be ran for SH4,
> too.
> 
> Tested by running said test case with 
> make check-gcc RUNTESTFLAGS="sh.exp=prefetch* --target_board=sh-sim
> \{-m2/-ml,-m2/-mb,-m2a/-mb,-m2a-single/-mb,-m4/-ml,-m4/-mb,
> -m4-single/-ml,-m4-single/-mb,-m4a-single/-ml,-m4a-single/-mb}"
> 
> OK?

OK.

Regards,
	kaz
diff mbox

Patch

Index: gcc/testsuite/gcc.target/sh/prefetch.c
===================================================================
--- gcc/testsuite/gcc.target/sh/prefetch.c	(revision 0)
+++ gcc/testsuite/gcc.target/sh/prefetch.c	(revision 0)
@@ -0,0 +1,35 @@ 
+/* Testcase to check generation of a SH4 and SH2A operand cache prefetch
+   instruction PREF @Rm.  */
+/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-options "-O0" }  */
+/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" "-m4*" } }  */
+/* { dg-final { scan-assembler "pref"} }  */
+
+void
+opt (void)
+{
+  int *p, wk;
+  int data[100];
+
+  /* data prefetch , instructions hit the cache. */
+
+  __builtin_prefetch (&data[0], 0, 0);
+  __builtin_prefetch (&data[0], 0, 1);
+  __builtin_prefetch (&data[0], 0, 2);
+  __builtin_prefetch (&data[0], 0, 3);
+  __builtin_prefetch (&data[0], 1, 0);
+  __builtin_prefetch (&data[0], 1, 1);
+  __builtin_prefetch (&data[0], 1, 2);
+  __builtin_prefetch (&data[0], 1, 3);
+
+
+  for (p = &data[0]; p < &data[9]; p++)
+    {
+      if (*p > *(p + 1))
+        {
+          wk = *p;
+          *p = *(p + 1);
+          *(p + 1) = wk;
+        }
+    }
+}
Index: gcc/testsuite/gcc.target/sh/sh2a-prefetch.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh2a-prefetch.c	(revision 186209)
+++ gcc/testsuite/gcc.target/sh/sh2a-prefetch.c	(working copy)
@@ -1,34 +0,0 @@ 
-/* Testcase to check generation of a SH2A specific instruction PREF @Rm.  */
-/* { dg-do assemble {target sh*-*-*}}  */
-/* { dg-options "-O0" }  */
-/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
-/* { dg-final { scan-assembler "pref"} }  */
-
-void
-opt (void)
-{
-  int *p, wk;
-  int data[100];
-
-  /* data prefetch , instructions hit the cache. */
-
-  __builtin_prefetch (&data[0], 0, 0);
-  __builtin_prefetch (&data[0], 0, 1);
-  __builtin_prefetch (&data[0], 0, 2);
-  __builtin_prefetch (&data[0], 0, 3);
-  __builtin_prefetch (&data[0], 1, 0);
-  __builtin_prefetch (&data[0], 1, 1);
-  __builtin_prefetch (&data[0], 1, 2);
-  __builtin_prefetch (&data[0], 1, 3);
-
-
-  for (p = &data[0]; p < &data[9]; p++)
-    {
-      if (*p > *(p + 1))
-        {
-          wk = *p;
-          *p = *(p + 1);
-          *(p + 1) = wk;
-        }
-    }
-}
Index: gcc/config/sh/sh.md
===================================================================
--- gcc/config/sh/sh.md	(revision 186212)
+++ gcc/config/sh/sh.md	(working copy)
@@ -13559,14 +13559,6 @@ 
 }
   [(set_attr "type" "other")])
 
-(define_insn "*prefetch_i4"
-  [(prefetch (match_operand:SI 0 "register_operand" "r")
-             (match_operand:SI 1 "const_int_operand" "n")
-             (match_operand:SI 2 "const_int_operand" "n"))]
-  "(TARGET_HARD_SH4 || TARGET_SHCOMPACT) && !TARGET_VXWORKS_RTP"
-  "pref	@%0";
-  [(set_attr "type" "other")])
-
 ;; In user mode, the "pref" instruction will raise a RADDERR exception
 ;; for accesses to [0x80000000,0xffffffff].  This makes it an unsuitable
 ;; implementation of __builtin_prefetch for VxWorks RTPs.
@@ -13585,12 +13577,12 @@ 
     operands[0] = force_reg (Pmode, operands[0]);
 })
 
-(define_insn "prefetch_m2a"
+(define_insn "*prefetch"
   [(prefetch (match_operand:SI 0 "register_operand" "r")
 	     (match_operand:SI 1 "const_int_operand" "n")
 	     (match_operand:SI 2 "const_int_operand" "n"))]
-  "TARGET_SH2A"
-  "pref\\t@%0"
+  "(TARGET_SH2A || TARGET_HARD_SH4 || TARGET_SHCOMPACT) && !TARGET_VXWORKS_RTP"
+  "pref	@%0"
   [(set_attr "type" "other")])
 
 (define_insn "alloco_i"