| Message ID | 4F5509A3.8050602@redhat.com |
|---|---|
| State | New |
| Headers | show |
On 03/05/2012 07:44 PM, Richard Henderson wrote: >> --- Comment #1 from Mikael Pettersson<mikpe at it dot uu.se> 2012-03-04 21:01:28 UTC --- >> Created attachment 26827 >> --> http://gcc.gnu.org/bugzilla/attachment.cgi?id=26827 >> reduced test case in C >> >> Depends on target CPU selection. -mcpu=680[012346]0 and -mcpu=cpu32 all work, >> but -mcpu=5206 (or apparently any other coldfire) ICEs. > > Indeed. Fixed by not trying to use negqi2 directly, but going > through the normal expanders which will DTRT for coldfire. > > Tested via cross-compile, committed to mainline and 4.7. This patch indeed helps me over the ICE from PR 52481, but now I am tripping over the next bootstrap breakdown (gcc-4_7-branch, --target=m68k-rtems4.11): /tmp/ccWpvRws.s: Assembler messages: /tmp/ccWpvRws.s:79: Error: invalid instruction for this architecture; needs 68000 [68ec000, 68hc000, 68hc001, 68008, 68302, 68306, 68307, 68322, 68356], 68010, 68020 [68k, 68ec020], 68030 [68ec030], 68040 [68ec040], 68060 [68ec060], cpu32 [68330, 68331, 68332, 68333, 68334, 68336, 68340, 68341, 68349, 68360], 51 [51ac, 51cn, 51em, 51jm, 51qe], 5407, 54418 [54410, 54415, 54416, 54417], 54455 [54450, 54451, 54452, 54453, ... -- statement `tas (%a0)' ignored /tmp/ccWpvRws.s:141: Error: invalid instruction for this architecture; needs 68000 [68ec000, 68hc000, 68hc001, 68008, 68302, 68306, 68307, 68322, 68356], 68010, 68020 [68k, 68ec020], 68030 [68ec030], 68040 [68ec040], 68060 [68ec060], cpu32 [68330, 68331, 68332, 68333, 68334, 68336, 68340, 68341, 68349, 68360], 51 [51ac, 51cn, 51em, 51jm, 51qe], 5407, 54418 [54410, 54415, 54416, 54417], 54455 [54450, 54451, 54452, 54453, ... -- statement `tas (%a0)' ignored make[9]: *** [compatibility-atomic-c++0x.lo] Error 1 * Incompatiblible/insufficient binutils (I am using binutils-2.22)? * Some as/ld-flags getting lost/improperly propagated during assembly/linking? * Bad/incompatible inline-asm hard-coded somewhere? Ralf
Ralf Corsepius <ralf.corsepius@rtems.org> writes: > * Incompatiblible/insufficient binutils (I am using binutils-2.22)? > * Some as/ld-flags getting lost/improperly propagated during > assembly/linking? > * Bad/incompatible inline-asm hard-coded somewhere? TAS needs at least ISA_B, ie. at least CFV4. Andreas.
On 03/06/12 02:13, Andreas Schwab wrote: > Ralf Corsepius <ralf.corsepius@rtems.org> writes: > >> * Incompatiblible/insufficient binutils (I am using binutils-2.22)? >> * Some as/ld-flags getting lost/improperly propagated during >> assembly/linking? >> * Bad/incompatible inline-asm hard-coded somewhere? > > TAS needs at least ISA_B, ie. at least CFV4. So... the correct test is what... #define ISA_HAS_TAS (!TARGET_COLDFIRE || TARGET_ISAB || TARGET_ISAC) ? r~
Richard Henderson <rth@redhat.com> writes: > On 03/06/12 02:13, Andreas Schwab wrote: >> Ralf Corsepius <ralf.corsepius@rtems.org> writes: >> >>> * Incompatiblible/insufficient binutils (I am using binutils-2.22)? >>> * Some as/ld-flags getting lost/improperly propagated during >>> assembly/linking? >>> * Bad/incompatible inline-asm hard-coded somewhere? >> >> TAS needs at least ISA_B, ie. at least CFV4. > > So... the correct test is what... > > #define ISA_HAS_TAS (!TARGET_COLDFIRE || TARGET_ISAB || TARGET_ISAC) Yes, that looks correct. Andreas.
diff --git a/gcc/config/m68k/sync.md b/gcc/config/m68k/sync.md index 5d5002a..6c840f5 100644 --- a/gcc/config/m68k/sync.md +++ b/gcc/config/m68k/sync.md @@ -62,8 +62,11 @@ (match_operand:SI 2 "const_int_operand" "")] ;; model "" { - emit_insn (gen_atomic_test_and_set_1 (operands[0], operands[1])); - emit_insn (gen_negqi2 (operands[0], operands[0])); + rtx t = gen_reg_rtx (QImode); + emit_insn (gen_atomic_test_and_set_1 (t, operands[1])); + t = expand_simple_unop (QImode, NEG, t, operands[0], 0); + if (t != operands[0]) + emit_move_insn (operands[0], t); DONE; })