diff mbox series

[2/2] target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+

Message ID 20221207090037.281452-2-bmeng@tinylab.org
State New
Headers show
Series [1/2] target/riscv: Simplify helper_sret() a little bit | expand

Commit Message

Bin Meng Dec. 7, 2022, 9 a.m. UTC
Since priv spec v1.12, MRET and SRET now clear mstatus.MPRV when
leaving M-mode.

Signed-off-by: Bin Meng <bmeng@tinylab.org>

---

 target/riscv/op_helper.c | 6 ++++++
 1 file changed, 6 insertions(+)

Comments

Alistair Francis Dec. 8, 2022, 4:17 a.m. UTC | #1
On Wed, Dec 7, 2022 at 7:11 PM Bin Meng <bmeng@tinylab.org> wrote:
>
> Since priv spec v1.12, MRET and SRET now clear mstatus.MPRV when
> leaving M-mode.
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

>
> ---
>
>  target/riscv/op_helper.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index a047d38152..878bcb03b8 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -154,6 +154,9 @@ target_ulong helper_sret(CPURISCVState *env)
>                          get_field(mstatus, MSTATUS_SPIE));
>      mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
>      mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
> +    if (env->priv_ver >= PRIV_VERSION_1_12_0) {
> +        mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
> +    }
>      env->mstatus = mstatus;
>
>      if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
> @@ -203,6 +206,9 @@ target_ulong helper_mret(CPURISCVState *env)
>      mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
>      mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
>      mstatus = set_field(mstatus, MSTATUS_MPV, 0);
> +    if ((env->priv_ver >= PRIV_VERSION_1_12_0) && (prev_priv != PRV_M)) {
> +        mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
> +    }
>      env->mstatus = mstatus;
>      riscv_cpu_set_mode(env, prev_priv);
>
> --
> 2.34.1
>
>
Alistair Francis Dec. 8, 2022, 5:43 a.m. UTC | #2
On Wed, Dec 7, 2022 at 7:11 PM Bin Meng <bmeng@tinylab.org> wrote:
>
> Since priv spec v1.12, MRET and SRET now clear mstatus.MPRV when
> leaving M-mode.
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>

Thanks!

Applied to riscv-to-apply.next

Alistair

>
> ---
>
>  target/riscv/op_helper.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index a047d38152..878bcb03b8 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -154,6 +154,9 @@ target_ulong helper_sret(CPURISCVState *env)
>                          get_field(mstatus, MSTATUS_SPIE));
>      mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
>      mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
> +    if (env->priv_ver >= PRIV_VERSION_1_12_0) {
> +        mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
> +    }
>      env->mstatus = mstatus;
>
>      if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
> @@ -203,6 +206,9 @@ target_ulong helper_mret(CPURISCVState *env)
>      mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
>      mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
>      mstatus = set_field(mstatus, MSTATUS_MPV, 0);
> +    if ((env->priv_ver >= PRIV_VERSION_1_12_0) && (prev_priv != PRV_M)) {
> +        mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
> +    }
>      env->mstatus = mstatus;
>      riscv_cpu_set_mode(env, prev_priv);
>
> --
> 2.34.1
>
>
diff mbox series

Patch

diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index a047d38152..878bcb03b8 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -154,6 +154,9 @@  target_ulong helper_sret(CPURISCVState *env)
                         get_field(mstatus, MSTATUS_SPIE));
     mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
     mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
+    if (env->priv_ver >= PRIV_VERSION_1_12_0) {
+        mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
+    }
     env->mstatus = mstatus;
 
     if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
@@ -203,6 +206,9 @@  target_ulong helper_mret(CPURISCVState *env)
     mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
     mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
     mstatus = set_field(mstatus, MSTATUS_MPV, 0);
+    if ((env->priv_ver >= PRIV_VERSION_1_12_0) && (prev_priv != PRV_M)) {
+        mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
+    }
     env->mstatus = mstatus;
     riscv_cpu_set_mode(env, prev_priv);