diff mbox

[i386] : Use reg_or_subregno in int->float splitters

Message ID CAFULd4YjyxM9G2sntpsnyZVHxPh-TjW2sRJKGHbJjfQgwMPT6A@mail.gmail.com
State New
Headers show

Commit Message

Uros Bizjak Nov. 1, 2011, 9:33 p.m. UTC 
Hello!

We have a nice utility function that can be used in int->float
splitter constraints.

2011-11-01  Uros Bizjak  <ubizjak@gmail.com>

	* config/i386/i386.md (splitters for int-float conversion): Use
	reg_or_subregno in splitter constraints.

Bootstrapped and regression tested on x86_64-pc-linux-gnu {,-m32},
committed to mainline SVN.

Uros.

Comments

Jakub Jelinek Nov. 1, 2011, 10 p.m. UTC | #1 
On Tue, Nov 01, 2011 at 10:33:07PM +0100, Uros Bizjak wrote:
> We have a nice utility function that can be used in int->float
> splitter constraints.
> 
> 2011-11-01  Uros Bizjak  <ubizjak@gmail.com>
> 
> 	* config/i386/i386.md (splitters for int-float conversion): Use
> 	reg_or_subregno in splitter constraints.
> 
> Bootstrapped and regression tested on x86_64-pc-linux-gnu {,-m32},
> committed to mainline SVN.

Unfortunately reg_or_subregno is an external non-inline function,
doesn't have pure attribute and SSE_REGNO_P macro evaluates its argument
twice, which means the function is called multiple times.

	Jakub
diff mbox

Patch

Index: i386.md
===================================================================
--- i386.md	(revision 180742)
+++ i386.md	(working copy)
@@ -4920,9 +4920,7 @@ 
    && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
    && TARGET_INTER_UNIT_CONVERSIONS
    && reload_completed
-   && (SSE_REG_P (operands[0])
-       || (GET_CODE (operands[0]) == SUBREG
-	   && SSE_REG_P (operands[0])))"
+   && SSE_REGNO_P (reg_or_subregno (operands[0]))"
   [(set (match_dup 0) (float:MODEF (match_dup 1)))])
 
 (define_split
@@ -4933,9 +4931,7 @@ 
    && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
    && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))
    && reload_completed
-   && (SSE_REG_P (operands[0])
-       || (GET_CODE (operands[0]) == SUBREG
-	   && SSE_REG_P (operands[0])))"
+   && SSE_REGNO_P (reg_or_subregno (operands[0]))"
   [(set (match_dup 2) (match_dup 1))
    (set (match_dup 0) (float:MODEF (match_dup 2)))])
 
@@ -5024,9 +5020,7 @@ 
   "TARGET_SSE2 && TARGET_SSE_MATH
    && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
    && reload_completed
-   && (SSE_REG_P (operands[0])
-       || (GET_CODE (operands[0]) == SUBREG
-	   && SSE_REG_P (operands[0])))"
+   && SSE_REGNO_P (reg_or_subregno (operands[0]))"
   [(const_int 0)]
 {
   rtx op1 = operands[1];
@@ -5067,9 +5061,7 @@ 
   "TARGET_SSE2 && TARGET_SSE_MATH
    && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
    && reload_completed
-   && (SSE_REG_P (operands[0])
-       || (GET_CODE (operands[0]) == SUBREG
-	   && SSE_REG_P (operands[0])))"
+   && SSE_REGNO_P (reg_or_subregno (operands[0]))"
   [(const_int 0)]
 {
   operands[3] = simplify_gen_subreg (<ssevecmode>mode, operands[0],
@@ -5091,9 +5083,7 @@ 
   "TARGET_SSE2 && TARGET_SSE_MATH
    && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
    && reload_completed
-   && (SSE_REG_P (operands[0])
-       || (GET_CODE (operands[0]) == SUBREG
-	   && SSE_REG_P (operands[0])))"
+   && SSE_REGNO_P (reg_or_subregno (operands[0]))"
   [(const_int 0)]
 {
   rtx op1 = operands[1];
@@ -5137,9 +5127,7 @@ 
   "TARGET_SSE2 && TARGET_SSE_MATH
    && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
    && reload_completed
-   && (SSE_REG_P (operands[0])
-       || (GET_CODE (operands[0]) == SUBREG
-	   && SSE_REG_P (operands[0])))"
+   && SSE_REGNO_P (reg_or_subregno (operands[0]))"
   [(const_int 0)]
 {
   operands[3] = simplify_gen_subreg (<ssevecmode>mode, operands[0],
@@ -5200,9 +5188,7 @@ 
    && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
    && (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))
    && reload_completed
-   && (SSE_REG_P (operands[0])
-       || (GET_CODE (operands[0]) == SUBREG
-	   && SSE_REG_P (operands[0])))"
+   && SSE_REGNO_P (reg_or_subregno (operands[0]))"
   [(set (match_dup 0) (float:MODEF (match_dup 1)))])
 
 (define_insn "*float<SWI48x:mode><MODEF:mode>2_sse_nointerunit"
@@ -5235,9 +5221,7 @@ 
    && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
    && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))
    && reload_completed
-   && (SSE_REG_P (operands[0])
-       || (GET_CODE (operands[0]) == SUBREG
-	   && SSE_REG_P (operands[0])))"
+   && SSE_REGNO_P (reg_or_subregno (operands[0]))"
   [(set (match_dup 2) (match_dup 1))
    (set (match_dup 0) (float:MODEF (match_dup 2)))])
 
@@ -5248,9 +5232,7 @@ 
   "(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
    && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
    && reload_completed
-   && (SSE_REG_P (operands[0])
-       || (GET_CODE (operands[0]) == SUBREG
-	   && SSE_REG_P (operands[0])))"
+   && SSE_REGNO_P (reg_or_subregno (operands[0]))"
   [(set (match_dup 0) (float:MODEF (match_dup 1)))])
 
 (define_insn "*float<SWI48x:mode><X87MODEF:mode>2_i387_with_temp"