| Message ID | 1311211654-14326-9-git-send-email-agraf@suse.de |
|---|---|
| State | New |
| Headers | show |
On 07/21/2011 03:27 AM, Alexander Graf wrote: > @@ -1288,7 +1288,7 @@ static void mpic_reset (void *opaque) > > mpp->glbc = 0x80000000; > /* Initialise controller registers */ > - mpp->frep = 0x004f0002; > + mpp->frep = 0x004f0002 | ((MAX_CPU - 1)<< 8); Should we really report the maximum supported number of CPUs or the actual number? Several processor manuals state that it is the number of physically present CPUs that is reported (-1 of course). In that case, the following would do? mpp->frep = 0x004f0002 | ((mpp->nb_cpus - 1)<< 8); > mpp->veni = VENI; > mpp->pint = 0x00000000; > mpp->spve = 0x0000FFFF; > @@ -1685,10 +1685,6 @@ qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus, > {mpic_cpu_read, mpic_cpu_write, MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE}, > }; > > - /* XXX: for now, only one CPU is supported */ > - if (nb_cpus != 1) > - return NULL; > - > mpp = qemu_mallocz(sizeof(openpic_t)); > > for (i = 0; i< sizeof(list)/sizeof(list[0]); i++) {
On 22.07.2011, at 16:10, Elie Richa wrote: > > On 07/21/2011 03:27 AM, Alexander Graf wrote: >> @@ -1288,7 +1288,7 @@ static void mpic_reset (void *opaque) >> >> mpp->glbc = 0x80000000; >> /* Initialise controller registers */ >> - mpp->frep = 0x004f0002; >> + mpp->frep = 0x004f0002 | ((MAX_CPU - 1)<< 8); > > Should we really report the maximum supported number of CPUs or the actual number? > Several processor manuals state that it is the number of physically present CPUs that is reported (-1 of course). > In that case, the following would do? > mpp->frep = 0x004f0002 | ((mpp->nb_cpus - 1)<< 8); Good idea. Will change :) Alex
diff --git a/hw/openpic.c b/hw/openpic.c index 6630206..a8d7824 100644 --- a/hw/openpic.c +++ b/hw/openpic.c @@ -63,7 +63,7 @@ #elif defined(USE_MPCxxx) -#define MAX_CPU 2 +#define MAX_CPU 32 #define MAX_IRQ 128 #define MAX_DBL 0 #define MAX_MBX 0 @@ -507,7 +507,7 @@ static inline void write_IRQreg (openpic_t *opp, int n_IRQ, break; case IRQ_IDE: tmp = val & 0xC0000000; - tmp |= val & ((1 << MAX_CPU) - 1); + tmp |= val & ((1ULL << MAX_CPU) - 1); opp->src[n_IRQ].ide = tmp; DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ, opp->src[n_IRQ].ide); break; @@ -1288,7 +1288,7 @@ static void mpic_reset (void *opaque) mpp->glbc = 0x80000000; /* Initialise controller registers */ - mpp->frep = 0x004f0002; + mpp->frep = 0x004f0002 | ((MAX_CPU - 1) << 8); mpp->veni = VENI; mpp->pint = 0x00000000; mpp->spve = 0x0000FFFF; @@ -1685,10 +1685,6 @@ qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus, {mpic_cpu_read, mpic_cpu_write, MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE}, }; - /* XXX: for now, only one CPU is supported */ - if (nb_cpus != 1) - return NULL; - mpp = qemu_mallocz(sizeof(openpic_t)); for (i = 0; i < sizeof(list)/sizeof(list[0]); i++) {
The MPIC emulation is now capable of handling up to 32 CPUs. Reflect that in the code exporting the numbers out and fix an integer overflow while at it. Signed-off-by: Alexander Graf <agraf@suse.de> --- hw/openpic.c | 10 +++------- 1 files changed, 3 insertions(+), 7 deletions(-)