| Message ID | 20200213163959.819733-1-thierry.reding@gmail.com |
|---|---|
| Headers | show |
| Series | memory: Introduce memory controller mini-framework | expand |
[+ Maxime] On 13/02/2020 4:39 pm, Thierry Reding wrote: > From: Thierry Reding <treding@nvidia.com> > > Hi, > > this set of patches adds a new binding that allows device tree nodes to > explicitly define the DMA parent for a given device. This supplements > the existing interconnect bindings and is useful to disambiguate in the > case where a device has multiple paths to system memory. Beyond that it > can also be useful when there aren't any actual interconnect paths that > can be controlled, so in simple cases this can serve as a simpler > variant of interconnect paths. Isn't that still squarely the intent of the "dma-mem" binding, though? i.e. it's not meant to be a 'real' interconnect provider, but a very simple way to encode DMA parentage piggybacked onto a more general binding (with the *option* of being a full-blown interconnect if it wants to, but certainly no expectation). Robin. > One other case where this is useful is to describe the relationship > between devices such as the memory controller and an IOMMU, for example. > On Tegra186 and later, the memory controller is programmed with a set of > stream IDs that are to be associated with each memory client. This > programming needs to happen before translations through the IOMMU start, > otherwise the used stream IDs may deviate from the expected values. The > memory-controllers property is used in this case to ensure that the > memory controller driver has been probed (and hence has programmed the > stream ID mappings) before the IOMMU becomes available. > > Patch 1 introduces the memory controller bindings, both from the > perspective of the provider and the consumer. Patch 2 makes use of a > memory-controllers property to determine the DMA parent for the purpose > of setting up DMA masks (based on the dma-ranges property of the DMA > parent). Patch 3 introduces a minimalistic framework that is used to > register memory controllers with along with a set of helpers to look up > the memory controller from device tree. > > An example of how to register a memory controller is shown in patch 4 > for Tegra186 (and later) and finally the ARM SMMU driver is extended to > become a consumer of an (optional) memory controller. As described > above, the goal is to defer probe as long as the memory controller has > not yet programmed the stream ID mappings. > > Thierry > > Thierry Reding (5): > dt-bindings: Add memory controller bindings > of: Use memory-controllers property for DMA parent > memory: Introduce memory controller mini-framework > memory: tegra186: Register as memory controller > iommu: arm-smmu: Get reference to memory controller > > .../bindings/memory-controllers/consumer.yaml | 14 + > .../memory-controllers/memory-controller.yaml | 32 +++ > drivers/iommu/arm-smmu.c | 11 + > drivers/iommu/arm-smmu.h | 2 + > drivers/memory/Makefile | 1 + > drivers/memory/core.c | 248 ++++++++++++++++++ > drivers/memory/tegra/tegra186.c | 9 +- > drivers/of/address.c | 25 +- > include/linux/memory-controller.h | 34 +++ > 9 files changed, 366 insertions(+), 10 deletions(-) > create mode 100644 Documentation/devicetree/bindings/memory-controllers/consumer.yaml > create mode 100644 Documentation/devicetree/bindings/memory-controllers/memory-controller.yaml > create mode 100644 drivers/memory/core.c > create mode 100644 include/linux/memory-controller.h >
On Thu, Feb 13, 2020 at 05:23:23PM +0000, Robin Murphy wrote: > [+ Maxime] > > On 13/02/2020 4:39 pm, Thierry Reding wrote: > > From: Thierry Reding <treding@nvidia.com> > > > > Hi, > > > > this set of patches adds a new binding that allows device tree nodes to > > explicitly define the DMA parent for a given device. This supplements > > the existing interconnect bindings and is useful to disambiguate in the > > case where a device has multiple paths to system memory. Beyond that it > > can also be useful when there aren't any actual interconnect paths that > > can be controlled, so in simple cases this can serve as a simpler > > variant of interconnect paths. > > Isn't that still squarely the intent of the "dma-mem" binding, though? i.e. > it's not meant to be a 'real' interconnect provider, but a very simple way > to encode DMA parentage piggybacked onto a more general binding (with the > *option* of being a full-blown interconnect if it wants to, but certainly no > expectation). The way that this works on Tegra is that we want to describe multiple interconnect paths. A typical device will have a read and a write memory client, which can be separately "tuned". Both of these paths will target system memory, so they would both technically be "dma-mem" paths. But that would make it impossible to treat them separately elsewhere. So we could choose any of them to be the "dma-mem" path, but then we need to be very careful about defining which one that is, so that drivers know how to look them up, which is also not really desirable. One other things we could do is to duplicate one of the entries, so that we'd have "read", "write" and "dma-mem" interconnect paths, with "dma-mem" referencing the same path as "read" or "write". That doesn't sound *too* bad, but it's still a bit of a hack. Having an explicit description for this sounds much clearer and less error prone to me. Thierry > > One other case where this is useful is to describe the relationship > > between devices such as the memory controller and an IOMMU, for example. > > On Tegra186 and later, the memory controller is programmed with a set of > > stream IDs that are to be associated with each memory client. This > > programming needs to happen before translations through the IOMMU start, > > otherwise the used stream IDs may deviate from the expected values. The > > memory-controllers property is used in this case to ensure that the > > memory controller driver has been probed (and hence has programmed the > > stream ID mappings) before the IOMMU becomes available. > > > > Patch 1 introduces the memory controller bindings, both from the > > perspective of the provider and the consumer. Patch 2 makes use of a > > memory-controllers property to determine the DMA parent for the purpose > > of setting up DMA masks (based on the dma-ranges property of the DMA > > parent). Patch 3 introduces a minimalistic framework that is used to > > register memory controllers with along with a set of helpers to look up > > the memory controller from device tree. > > > > An example of how to register a memory controller is shown in patch 4 > > for Tegra186 (and later) and finally the ARM SMMU driver is extended to > > become a consumer of an (optional) memory controller. As described > > above, the goal is to defer probe as long as the memory controller has > > not yet programmed the stream ID mappings. > > > > Thierry > > > > Thierry Reding (5): > > dt-bindings: Add memory controller bindings > > of: Use memory-controllers property for DMA parent > > memory: Introduce memory controller mini-framework > > memory: tegra186: Register as memory controller > > iommu: arm-smmu: Get reference to memory controller > > > > .../bindings/memory-controllers/consumer.yaml | 14 + > > .../memory-controllers/memory-controller.yaml | 32 +++ > > drivers/iommu/arm-smmu.c | 11 + > > drivers/iommu/arm-smmu.h | 2 + > > drivers/memory/Makefile | 1 + > > drivers/memory/core.c | 248 ++++++++++++++++++ > > drivers/memory/tegra/tegra186.c | 9 +- > > drivers/of/address.c | 25 +- > > include/linux/memory-controller.h | 34 +++ > > 9 files changed, 366 insertions(+), 10 deletions(-) > > create mode 100644 Documentation/devicetree/bindings/memory-controllers/consumer.yaml > > create mode 100644 Documentation/devicetree/bindings/memory-controllers/memory-controller.yaml > > create mode 100644 drivers/memory/core.c > > create mode 100644 include/linux/memory-controller.h > >
On Thu, Feb 13, 2020 at 07:15:55PM +0100, Thierry Reding wrote: > On Thu, Feb 13, 2020 at 05:23:23PM +0000, Robin Murphy wrote: > > [+ Maxime] > > > > On 13/02/2020 4:39 pm, Thierry Reding wrote: > > > From: Thierry Reding <treding@nvidia.com> > > > > > > Hi, > > > > > > this set of patches adds a new binding that allows device tree nodes to > > > explicitly define the DMA parent for a given device. This supplements > > > the existing interconnect bindings and is useful to disambiguate in the > > > case where a device has multiple paths to system memory. Beyond that it > > > can also be useful when there aren't any actual interconnect paths that > > > can be controlled, so in simple cases this can serve as a simpler > > > variant of interconnect paths. > > > > Isn't that still squarely the intent of the "dma-mem" binding, though? i.e. > > it's not meant to be a 'real' interconnect provider, but a very simple way > > to encode DMA parentage piggybacked onto a more general binding (with the > > *option* of being a full-blown interconnect if it wants to, but certainly no > > expectation). > > The way that this works on Tegra is that we want to describe multiple > interconnect paths. A typical device will have a read and a write memory > client, which can be separately "tuned". Both of these paths will target > system memory, so they would both technically be "dma-mem" paths. But > that would make it impossible to treat them separately elsewhere. > > So we could choose any of them to be the "dma-mem" path, but then we > need to be very careful about defining which one that is, so that > drivers know how to look them up, which is also not really desirable. > > One other things we could do is to duplicate one of the entries, so that > we'd have "read", "write" and "dma-mem" interconnect paths, with > "dma-mem" referencing the same path as "read" or "write". That doesn't > sound *too* bad, but it's still a bit of a hack. Having an explicit > description for this sounds much clearer and less error prone to me. IIRC the dmaengine binding allows to do that, so it would make sense to me to have the same thing allowed for interconnects. Maxime
From: Thierry Reding <treding@nvidia.com> Hi, this set of patches adds a new binding that allows device tree nodes to explicitly define the DMA parent for a given device. This supplements the existing interconnect bindings and is useful to disambiguate in the case where a device has multiple paths to system memory. Beyond that it can also be useful when there aren't any actual interconnect paths that can be controlled, so in simple cases this can serve as a simpler variant of interconnect paths. One other case where this is useful is to describe the relationship between devices such as the memory controller and an IOMMU, for example. On Tegra186 and later, the memory controller is programmed with a set of stream IDs that are to be associated with each memory client. This programming needs to happen before translations through the IOMMU start, otherwise the used stream IDs may deviate from the expected values. The memory-controllers property is used in this case to ensure that the memory controller driver has been probed (and hence has programmed the stream ID mappings) before the IOMMU becomes available. Patch 1 introduces the memory controller bindings, both from the perspective of the provider and the consumer. Patch 2 makes use of a memory-controllers property to determine the DMA parent for the purpose of setting up DMA masks (based on the dma-ranges property of the DMA parent). Patch 3 introduces a minimalistic framework that is used to register memory controllers with along with a set of helpers to look up the memory controller from device tree. An example of how to register a memory controller is shown in patch 4 for Tegra186 (and later) and finally the ARM SMMU driver is extended to become a consumer of an (optional) memory controller. As described above, the goal is to defer probe as long as the memory controller has not yet programmed the stream ID mappings. Thierry Thierry Reding (5): dt-bindings: Add memory controller bindings of: Use memory-controllers property for DMA parent memory: Introduce memory controller mini-framework memory: tegra186: Register as memory controller iommu: arm-smmu: Get reference to memory controller .../bindings/memory-controllers/consumer.yaml | 14 + .../memory-controllers/memory-controller.yaml | 32 +++ drivers/iommu/arm-smmu.c | 11 + drivers/iommu/arm-smmu.h | 2 + drivers/memory/Makefile | 1 + drivers/memory/core.c | 248 ++++++++++++++++++ drivers/memory/tegra/tegra186.c | 9 +- drivers/of/address.c | 25 +- include/linux/memory-controller.h | 34 +++ 9 files changed, 366 insertions(+), 10 deletions(-) create mode 100644 Documentation/devicetree/bindings/memory-controllers/consumer.yaml create mode 100644 Documentation/devicetree/bindings/memory-controllers/memory-controller.yaml create mode 100644 drivers/memory/core.c create mode 100644 include/linux/memory-controller.h