| Message ID | 157623843543.360005.13996472463887521794.stgit@bahia.lan |
|---|---|
| State | New |
| Headers | show |
| Series | ppc/pnv: Get rid of chip_type attributes | expand |
On 13/12/2019 13:00, Greg Kurz wrote: > The XSCOM bus is implemented with a QOM interface, which is mostly > generic from a CPU type standpoint, except for the computation of > addresses on the Pervasize Connect Bus (PCB) network. This is handled Pervasive > by the pnv_xscom_pcba() function with a switch statement based on > the chip_type class level attribute of the CPU chip. > > This can be achieved using QOM. Also the address argument is masked with > PNV_XSCOM_SIZE - 1, which is for POWER8 only. Addresses may have different > sizes with other CPU types. Have each CPU chip type handle the appropriate > computation with a QOM xscom_pcba() method. PnvXscom model ? :) > Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> > --- > hw/ppc/pnv.c | 23 +++++++++++++++++++++++ > hw/ppc/pnv_xscom.c | 14 +------------- > include/hw/ppc/pnv.h | 1 + > 3 files changed, 25 insertions(+), 13 deletions(-) > > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index 0447b534b8c5..cc40b90e9cd2 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -1121,6 +1121,12 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) > &chip8->homer.regs); > } > > +static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) > +{ > + addr &= (PNV_XSCOM_SIZE - 1); > + return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); > +} > + > static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) > { > DeviceClass *dc = DEVICE_CLASS(klass); > @@ -1138,6 +1144,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) > k->dt_populate = pnv_chip_power8_dt_populate; > k->pic_print_info = pnv_chip_power8_pic_print_info; > k->xscom_core_base = pnv_chip_power8_xscom_core_base; > + k->xscom_pcba = pnv_chip_power8_xscom_pcba; > dc->desc = "PowerNV Chip POWER8E"; > > device_class_set_parent_realize(dc, pnv_chip_power8_realize, > @@ -1161,6 +1168,7 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) > k->dt_populate = pnv_chip_power8_dt_populate; > k->pic_print_info = pnv_chip_power8_pic_print_info; > k->xscom_core_base = pnv_chip_power8_xscom_core_base; > + k->xscom_pcba = pnv_chip_power8_xscom_pcba; > dc->desc = "PowerNV Chip POWER8"; > > device_class_set_parent_realize(dc, pnv_chip_power8_realize, > @@ -1184,6 +1192,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) > k->dt_populate = pnv_chip_power8_dt_populate; > k->pic_print_info = pnv_chip_power8_pic_print_info; > k->xscom_core_base = pnv_chip_power8_xscom_core_base; > + k->xscom_pcba = pnv_chip_power8_xscom_pcba; > dc->desc = "PowerNV Chip POWER8NVL"; > > device_class_set_parent_realize(dc, pnv_chip_power8_realize, > @@ -1340,6 +1349,12 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) > &chip9->homer.regs); > } > > +static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) > +{ > + addr &= (PNV9_XSCOM_SIZE - 1); > + return addr >> 3; > +} > + > static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) > { > DeviceClass *dc = DEVICE_CLASS(klass); > @@ -1357,6 +1372,7 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) > k->dt_populate = pnv_chip_power9_dt_populate; > k->pic_print_info = pnv_chip_power9_pic_print_info; > k->xscom_core_base = pnv_chip_power9_xscom_core_base; > + k->xscom_pcba = pnv_chip_power9_xscom_pcba; > dc->desc = "PowerNV Chip POWER9"; > > device_class_set_parent_realize(dc, pnv_chip_power9_realize, > @@ -1422,6 +1438,12 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) > (uint64_t) PNV10_LPCM_BASE(chip)); > } > > +static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) > +{ > + addr &= (PNV10_XSCOM_SIZE - 1); > + return addr >> 3; > +} > + > static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) > { > DeviceClass *dc = DEVICE_CLASS(klass); > @@ -1439,6 +1461,7 @@ static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) > k->dt_populate = pnv_chip_power10_dt_populate; > k->pic_print_info = pnv_chip_power10_pic_print_info; > k->xscom_core_base = pnv_chip_power10_xscom_core_base; > + k->xscom_pcba = pnv_chip_power10_xscom_pcba; > dc->desc = "PowerNV Chip POWER10"; > > device_class_set_parent_realize(dc, pnv_chip_power10_realize, > diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c > index 5ae9dfbb88ad..b681c72575b2 100644 > --- a/hw/ppc/pnv_xscom.c > +++ b/hw/ppc/pnv_xscom.c > @@ -57,19 +57,7 @@ static void xscom_complete(CPUState *cs, uint64_t hmer_bits) > > static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr) > { > - addr &= (PNV_XSCOM_SIZE - 1); > - > - switch (PNV_CHIP_GET_CLASS(chip)->chip_type) { > - case PNV_CHIP_POWER8E: > - case PNV_CHIP_POWER8: > - case PNV_CHIP_POWER8NVL: > - return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); > - case PNV_CHIP_POWER9: > - case PNV_CHIP_POWER10: > - return addr >> 3; > - default: > - g_assert_not_reached(); > - } > + return PNV_CHIP_GET_CLASS(chip)->xscom_pcba(chip, addr); > } > > static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba) > diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h > index 7a134a15d3b5..4972e93c2619 100644 > --- a/include/hw/ppc/pnv.h > +++ b/include/hw/ppc/pnv.h > @@ -138,6 +138,7 @@ typedef struct PnvChipClass { > void (*dt_populate)(PnvChip *chip, void *fdt); > void (*pic_print_info)(PnvChip *chip, Monitor *mon); > uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); > + uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr); > } PnvChipClass; > > #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP >
On Fri, Dec 13, 2019 at 02:06:31PM +0100, Cédric Le Goater wrote: > On 13/12/2019 13:00, Greg Kurz wrote: > > The XSCOM bus is implemented with a QOM interface, which is mostly > > generic from a CPU type standpoint, except for the computation of > > addresses on the Pervasize Connect Bus (PCB) network. This is handled > > Pervasive I've fixed this typo in transit. > > > by the pnv_xscom_pcba() function with a switch statement based on > > the chip_type class level attribute of the CPU chip. > > > > This can be achieved using QOM. Also the address argument is masked with > > PNV_XSCOM_SIZE - 1, which is for POWER8 only. Addresses may have different > > sizes with other CPU types. Have each CPU chip type handle the appropriate > > computation with a QOM xscom_pcba() method. > > PnvXscom model ? :) > > > Signed-off-by: Greg Kurz <groug@kaod.org> > > Reviewed-by: Cédric Le Goater <clg@kaod.org> > > > --- > > hw/ppc/pnv.c | 23 +++++++++++++++++++++++ > > hw/ppc/pnv_xscom.c | 14 +------------- > > include/hw/ppc/pnv.h | 1 + > > 3 files changed, 25 insertions(+), 13 deletions(-) > > > > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > > index 0447b534b8c5..cc40b90e9cd2 100644 > > --- a/hw/ppc/pnv.c > > +++ b/hw/ppc/pnv.c > > @@ -1121,6 +1121,12 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) > > &chip8->homer.regs); > > } > > > > +static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) > > +{ > > + addr &= (PNV_XSCOM_SIZE - 1); > > + return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); > > +} > > + > > static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) > > { > > DeviceClass *dc = DEVICE_CLASS(klass); > > @@ -1138,6 +1144,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) > > k->dt_populate = pnv_chip_power8_dt_populate; > > k->pic_print_info = pnv_chip_power8_pic_print_info; > > k->xscom_core_base = pnv_chip_power8_xscom_core_base; > > + k->xscom_pcba = pnv_chip_power8_xscom_pcba; > > dc->desc = "PowerNV Chip POWER8E"; > > > > device_class_set_parent_realize(dc, pnv_chip_power8_realize, > > @@ -1161,6 +1168,7 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) > > k->dt_populate = pnv_chip_power8_dt_populate; > > k->pic_print_info = pnv_chip_power8_pic_print_info; > > k->xscom_core_base = pnv_chip_power8_xscom_core_base; > > + k->xscom_pcba = pnv_chip_power8_xscom_pcba; > > dc->desc = "PowerNV Chip POWER8"; > > > > device_class_set_parent_realize(dc, pnv_chip_power8_realize, > > @@ -1184,6 +1192,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) > > k->dt_populate = pnv_chip_power8_dt_populate; > > k->pic_print_info = pnv_chip_power8_pic_print_info; > > k->xscom_core_base = pnv_chip_power8_xscom_core_base; > > + k->xscom_pcba = pnv_chip_power8_xscom_pcba; > > dc->desc = "PowerNV Chip POWER8NVL"; > > > > device_class_set_parent_realize(dc, pnv_chip_power8_realize, > > @@ -1340,6 +1349,12 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) > > &chip9->homer.regs); > > } > > > > +static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) > > +{ > > + addr &= (PNV9_XSCOM_SIZE - 1); > > + return addr >> 3; > > +} > > + > > static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) > > { > > DeviceClass *dc = DEVICE_CLASS(klass); > > @@ -1357,6 +1372,7 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) > > k->dt_populate = pnv_chip_power9_dt_populate; > > k->pic_print_info = pnv_chip_power9_pic_print_info; > > k->xscom_core_base = pnv_chip_power9_xscom_core_base; > > + k->xscom_pcba = pnv_chip_power9_xscom_pcba; > > dc->desc = "PowerNV Chip POWER9"; > > > > device_class_set_parent_realize(dc, pnv_chip_power9_realize, > > @@ -1422,6 +1438,12 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) > > (uint64_t) PNV10_LPCM_BASE(chip)); > > } > > > > +static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) > > +{ > > + addr &= (PNV10_XSCOM_SIZE - 1); > > + return addr >> 3; > > +} > > + > > static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) > > { > > DeviceClass *dc = DEVICE_CLASS(klass); > > @@ -1439,6 +1461,7 @@ static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) > > k->dt_populate = pnv_chip_power10_dt_populate; > > k->pic_print_info = pnv_chip_power10_pic_print_info; > > k->xscom_core_base = pnv_chip_power10_xscom_core_base; > > + k->xscom_pcba = pnv_chip_power10_xscom_pcba; > > dc->desc = "PowerNV Chip POWER10"; > > > > device_class_set_parent_realize(dc, pnv_chip_power10_realize, > > diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c > > index 5ae9dfbb88ad..b681c72575b2 100644 > > --- a/hw/ppc/pnv_xscom.c > > +++ b/hw/ppc/pnv_xscom.c > > @@ -57,19 +57,7 @@ static void xscom_complete(CPUState *cs, uint64_t hmer_bits) > > > > static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr) > > { > > - addr &= (PNV_XSCOM_SIZE - 1); > > - > > - switch (PNV_CHIP_GET_CLASS(chip)->chip_type) { > > - case PNV_CHIP_POWER8E: > > - case PNV_CHIP_POWER8: > > - case PNV_CHIP_POWER8NVL: > > - return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); > > - case PNV_CHIP_POWER9: > > - case PNV_CHIP_POWER10: > > - return addr >> 3; > > - default: > > - g_assert_not_reached(); > > - } > > + return PNV_CHIP_GET_CLASS(chip)->xscom_pcba(chip, addr); > > } > > > > static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba) > > diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h > > index 7a134a15d3b5..4972e93c2619 100644 > > --- a/include/hw/ppc/pnv.h > > +++ b/include/hw/ppc/pnv.h > > @@ -138,6 +138,7 @@ typedef struct PnvChipClass { > > void (*dt_populate)(PnvChip *chip, void *fdt); > > void (*pic_print_info)(PnvChip *chip, Monitor *mon); > > uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); > > + uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr); > > } PnvChipClass; > > > > #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP > > >
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 0447b534b8c5..cc40b90e9cd2 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1121,6 +1121,12 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) &chip8->homer.regs); } +static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) +{ + addr &= (PNV_XSCOM_SIZE - 1); + return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); +} + static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -1138,6 +1144,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) k->dt_populate = pnv_chip_power8_dt_populate; k->pic_print_info = pnv_chip_power8_pic_print_info; k->xscom_core_base = pnv_chip_power8_xscom_core_base; + k->xscom_pcba = pnv_chip_power8_xscom_pcba; dc->desc = "PowerNV Chip POWER8E"; device_class_set_parent_realize(dc, pnv_chip_power8_realize, @@ -1161,6 +1168,7 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) k->dt_populate = pnv_chip_power8_dt_populate; k->pic_print_info = pnv_chip_power8_pic_print_info; k->xscom_core_base = pnv_chip_power8_xscom_core_base; + k->xscom_pcba = pnv_chip_power8_xscom_pcba; dc->desc = "PowerNV Chip POWER8"; device_class_set_parent_realize(dc, pnv_chip_power8_realize, @@ -1184,6 +1192,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) k->dt_populate = pnv_chip_power8_dt_populate; k->pic_print_info = pnv_chip_power8_pic_print_info; k->xscom_core_base = pnv_chip_power8_xscom_core_base; + k->xscom_pcba = pnv_chip_power8_xscom_pcba; dc->desc = "PowerNV Chip POWER8NVL"; device_class_set_parent_realize(dc, pnv_chip_power8_realize, @@ -1340,6 +1349,12 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) &chip9->homer.regs); } +static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) +{ + addr &= (PNV9_XSCOM_SIZE - 1); + return addr >> 3; +} + static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -1357,6 +1372,7 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) k->dt_populate = pnv_chip_power9_dt_populate; k->pic_print_info = pnv_chip_power9_pic_print_info; k->xscom_core_base = pnv_chip_power9_xscom_core_base; + k->xscom_pcba = pnv_chip_power9_xscom_pcba; dc->desc = "PowerNV Chip POWER9"; device_class_set_parent_realize(dc, pnv_chip_power9_realize, @@ -1422,6 +1438,12 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) (uint64_t) PNV10_LPCM_BASE(chip)); } +static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) +{ + addr &= (PNV10_XSCOM_SIZE - 1); + return addr >> 3; +} + static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -1439,6 +1461,7 @@ static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) k->dt_populate = pnv_chip_power10_dt_populate; k->pic_print_info = pnv_chip_power10_pic_print_info; k->xscom_core_base = pnv_chip_power10_xscom_core_base; + k->xscom_pcba = pnv_chip_power10_xscom_pcba; dc->desc = "PowerNV Chip POWER10"; device_class_set_parent_realize(dc, pnv_chip_power10_realize, diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c index 5ae9dfbb88ad..b681c72575b2 100644 --- a/hw/ppc/pnv_xscom.c +++ b/hw/ppc/pnv_xscom.c @@ -57,19 +57,7 @@ static void xscom_complete(CPUState *cs, uint64_t hmer_bits) static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr) { - addr &= (PNV_XSCOM_SIZE - 1); - - switch (PNV_CHIP_GET_CLASS(chip)->chip_type) { - case PNV_CHIP_POWER8E: - case PNV_CHIP_POWER8: - case PNV_CHIP_POWER8NVL: - return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); - case PNV_CHIP_POWER9: - case PNV_CHIP_POWER10: - return addr >> 3; - default: - g_assert_not_reached(); - } + return PNV_CHIP_GET_CLASS(chip)->xscom_pcba(chip, addr); } static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 7a134a15d3b5..4972e93c2619 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -138,6 +138,7 @@ typedef struct PnvChipClass { void (*dt_populate)(PnvChip *chip, void *fdt); void (*pic_print_info)(PnvChip *chip, Monitor *mon); uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); + uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr); } PnvChipClass; #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
The XSCOM bus is implemented with a QOM interface, which is mostly generic from a CPU type standpoint, except for the computation of addresses on the Pervasize Connect Bus (PCB) network. This is handled by the pnv_xscom_pcba() function with a switch statement based on the chip_type class level attribute of the CPU chip. This can be achieved using QOM. Also the address argument is masked with PNV_XSCOM_SIZE - 1, which is for POWER8 only. Addresses may have different sizes with other CPU types. Have each CPU chip type handle the appropriate computation with a QOM xscom_pcba() method. Signed-off-by: Greg Kurz <groug@kaod.org> --- hw/ppc/pnv.c | 23 +++++++++++++++++++++++ hw/ppc/pnv_xscom.c | 14 +------------- include/hw/ppc/pnv.h | 1 + 3 files changed, 25 insertions(+), 13 deletions(-)