diff mbox series

, V4, patch #3: Fix up mov<mode>_64bit_dm

Message ID 20190918235846.GC28484@ibm-toto.the-meissners.org
State New
Headers show
Series , V4, patch #3: Fix up mov<mode>_64bit_dm | expand

Commit Message

Michael Meissner Sept. 18, 2019, 11:58 p.m. UTC 
In doing the patches, I noticed that mov<mode>_64bit_dm had two alternatives
combined together.  This patch fixes the problem, before the next patch that
will need to modify mov<mode>_64bit_dm for prefixed addressing.

I have done a bootstrap build with all of the patches applied, and there were
no regressions in the test suite.  After posting these patches, I will start a
job to build each set of patches in turn just to make sure there are no extra
warnings.

Can I commit this patch to the trunk?

2019-09-18  Michael Meissner  <meissner@linux.ibm.com>

	* config/rs6000/rs6000.md (mov<mode>_64bit_dm): Split the
	alternatives for loading 0.0 to a GPR and loading a 128-bit
	floating point type to a GPR.

Comments

Segher Boessenkool Sept. 27, 2019, 11:33 p.m. UTC | #1 
On Wed, Sep 18, 2019 at 07:58:46PM -0400, Michael Meissner wrote:
> In doing the patches, I noticed that mov<mode>_64bit_dm had two alternatives
> combined together.  This patch fixes the problem, before the next patch that
> will need to modify mov<mode>_64bit_dm for prefixed addressing.

This is okay for trunk.  Thanks!


Segher


> 2019-09-18  Michael Meissner  <meissner@linux.ibm.com>
> 
> 	* config/rs6000/rs6000.md (mov<mode>_64bit_dm): Split the
> 	alternatives for loading 0.0 to a GPR and loading a 128-bit
> 	floating point type to a GPR.
diff mbox series

Patch

Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md	(revision 275816)
+++ gcc/config/rs6000/rs6000.md	(working copy)
@@ -7758,9 +7758,18 @@  (define_expand "mov<mode>"
 ;; not swapped like they are for TImode or TFmode.  Subregs therefore are
 ;; problematical.  Don't allow direct move for this case.
 
+;;		FPR load    FPR store   FPR move    FPR zero    GPR load
+;;		GPR zero    GPR store   GPR move    MFVSRD      MTVSRD
+
 (define_insn_and_split "*mov<mode>_64bit_dm"
-  [(set (match_operand:FMOVE128_FPR 0 "nonimmediate_operand" "=m,d,d,d,Y,r,r,r,d")
-	(match_operand:FMOVE128_FPR 1 "input_operand" "d,m,d,<zero_fp>,r,<zero_fp>Y,r,d,r"))]
+  [(set (match_operand:FMOVE128_FPR 0 "nonimmediate_operand"
+		"=m,        d,          d,          d,          Y,
+		 r,         r,          r,          r,          d")
+
+	(match_operand:FMOVE128_FPR 1 "input_operand"
+		"d,         m,          d,          <zero_fp>,  r,
+		 <zero_fp>, Y,          r,          d,          r"))]
+
   "TARGET_HARD_FLOAT && TARGET_POWERPC64 && FLOAT128_2REG_P (<MODE>mode)
    && (<MODE>mode != TDmode || WORDS_BIG_ENDIAN)
    && (gpc_reg_operand (operands[0], <MODE>mode)
@@ -7769,8 +7778,8 @@  (define_insn_and_split "*mov<mode>_64bit
   "&& reload_completed"
   [(pc)]
 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
-  [(set_attr "length" "8,8,8,8,12,12,8,8,8")
-   (set_attr "isa" "*,*,*,*,*,*,*,p8v,p8v")])
+  [(set_attr "length" "8")
+   (set_attr "isa" "*,*,*,*,*,*,*,*,p8v,p8v")])
 
 (define_insn_and_split "*movtd_64bit_nodm"
   [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r")