| Message ID | 20190712121401.28578-1-alexander.sverdlin@nokia.com |
|---|---|
| State | Accepted |
| Delegated to: | Ambarus Tudor |
| Headers | show |
| Series | spi-nor: intel-spi: Whitelist 4B read commands | expand |
Mika, Would you please review the patch from below? Thanks, ta On 07/12/2019 03:14 PM, Sverdlin, Alexander (Nokia - DE/Ulm) wrote: > External E-Mail > > > From: Alexander Sverdlin <alexander.sverdlin@nokia.com> > > spi-nor.c issues 4B commands for some Flash chips bigger than 16Mbytes. > Xeon(R) D-1500 documentation mentions its Integrated PCH Logic supports > Flash chips up to 64Mbytes. > D-1500 Integrated PCH documenation however has inconsistencies regarding > FADDR register width and says nothing about particular commands issued > to support 64Mbytes of Flash. > > Nevetheless the tests on Xeon(R) CPU D-1548 with 512Mbit Flash chips > Macronix MX25L51245G and Micron MT25QL512A showed that erase, write and > read operations work just fine after SPINOR_OP_READ_4B and > SPINOR_OP_READ_FAST_4B are white-listed (currently only > SPINOR_OP_READ_FAST_4B is used and only for Macronix). > > Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> > --- > drivers/mtd/spi-nor/intel-spi.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/mtd/spi-nor/intel-spi.c b/drivers/mtd/spi-nor/intel-spi.c > index 1ccf23f..43e55a2e 100644 > --- a/drivers/mtd/spi-nor/intel-spi.c > +++ b/drivers/mtd/spi-nor/intel-spi.c > @@ -621,6 +621,8 @@ static ssize_t intel_spi_read(struct spi_nor *nor, loff_t from, size_t len, > switch (nor->read_opcode) { > case SPINOR_OP_READ: > case SPINOR_OP_READ_FAST: > + case SPINOR_OP_READ_4B: > + case SPINOR_OP_READ_FAST_4B: > break; > default: > return -EINVAL; >
On Tue, Aug 20, 2019 at 03:24:37PM +0000, Tudor.Ambarus@microchip.com wrote: > Mika, > > Would you please review the patch from below? Sure. > > Thanks, > ta > > On 07/12/2019 03:14 PM, Sverdlin, Alexander (Nokia - DE/Ulm) wrote: > > External E-Mail > > > > > > From: Alexander Sverdlin <alexander.sverdlin@nokia.com> > > > > spi-nor.c issues 4B commands for some Flash chips bigger than 16Mbytes. > > Xeon(R) D-1500 documentation mentions its Integrated PCH Logic supports > > Flash chips up to 64Mbytes. > > D-1500 Integrated PCH documenation however has inconsistencies regarding > > FADDR register width and says nothing about particular commands issued > > to support 64Mbytes of Flash. Unfortunately I don't have any additional documentation that could help. > > Nevetheless the tests on Xeon(R) CPU D-1548 with 512Mbit Flash chips > > Macronix MX25L51245G and Micron MT25QL512A showed that erase, write and > > read operations work just fine after SPINOR_OP_READ_4B and > > SPINOR_OP_READ_FAST_4B are white-listed (currently only > > SPINOR_OP_READ_FAST_4B is used and only for Macronix). If it works in your testing I don't see why we would not support them especially since these are just reads. > > Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> The patch itself is trivial enough and looks fine to me. Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> > > --- > > drivers/mtd/spi-nor/intel-spi.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/drivers/mtd/spi-nor/intel-spi.c b/drivers/mtd/spi-nor/intel-spi.c > > index 1ccf23f..43e55a2e 100644 > > --- a/drivers/mtd/spi-nor/intel-spi.c > > +++ b/drivers/mtd/spi-nor/intel-spi.c > > @@ -621,6 +621,8 @@ static ssize_t intel_spi_read(struct spi_nor *nor, loff_t from, size_t len, > > switch (nor->read_opcode) { > > case SPINOR_OP_READ: > > case SPINOR_OP_READ_FAST: > > + case SPINOR_OP_READ_4B: > > + case SPINOR_OP_READ_FAST_4B: > > break; > > default: > > return -EINVAL; > >
On 07/12/2019 03:14 PM, Sverdlin, Alexander (Nokia - DE/Ulm) wrote: > External E-Mail > > > From: Alexander Sverdlin <alexander.sverdlin@nokia.com> > > spi-nor.c issues 4B commands for some Flash chips bigger than 16Mbytes. > Xeon(R) D-1500 documentation mentions its Integrated PCH Logic supports > Flash chips up to 64Mbytes. > D-1500 Integrated PCH documenation however has inconsistencies regarding > FADDR register width and says nothing about particular commands issued > to support 64Mbytes of Flash. > > Nevetheless the tests on Xeon(R) CPU D-1548 with 512Mbit Flash chips > Macronix MX25L51245G and Micron MT25QL512A showed that erase, write and > read operations work just fine after SPINOR_OP_READ_4B and > SPINOR_OP_READ_FAST_4B are white-listed (currently only > SPINOR_OP_READ_FAST_4B is used and only for Macronix). > > Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> > --- > drivers/mtd/spi-nor/intel-spi.c | 2 ++ > 1 file changed, 2 insertions(+) > Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git, spi-nor/next branch. Thanks, ta
diff --git a/drivers/mtd/spi-nor/intel-spi.c b/drivers/mtd/spi-nor/intel-spi.c index 1ccf23f..43e55a2e 100644 --- a/drivers/mtd/spi-nor/intel-spi.c +++ b/drivers/mtd/spi-nor/intel-spi.c @@ -621,6 +621,8 @@ static ssize_t intel_spi_read(struct spi_nor *nor, loff_t from, size_t len, switch (nor->read_opcode) { case SPINOR_OP_READ: case SPINOR_OP_READ_FAST: + case SPINOR_OP_READ_4B: + case SPINOR_OP_READ_FAST_4B: break; default: return -EINVAL;