diff mbox

ARM: More reorganization of extend patterns (PR43137)

Message ID 4C914925.1030003@codesourcery.com
State New
Headers show

Commit Message

Bernd Schmidt Sept. 15, 2010, 10:31 p.m. UTC 
On 09/01/2010 05:52 PM, Richard Earnshaw wrote:
> On Tue, 2010-07-13 at 10:56 +0100, Bernd Schmidt wrote:
>> This patch merges a number of different extend:DI patterns by using a
>> QHSI mode_iterator.  It also removes separate patterns from thumb2.md
>> as
>> we can just set attr ce_count for ARM patterns as well.  I've
>> completed
>> what I'd partially done in my previous patch, which is to remove
>> unnecessary constant pool handling from these patterns - none of them
>> accept constants.

> The define_mode_attrs need to be moved to iterators.md.  Also, a number
> of patterns have been changed (inconsistently with the rest of arm.md)
> to not have the terminating ')' in column 1.
>
> Otherwise, OK.

This had one undesirable side effect.  The extendsidi patterns now 
accept memory arguments, which can make it impossible for the combiner 
to generate adddi_[zs]esidi patterns.  Fixed with this patch, regression 
tested in the same way as the previous one.  Ok?


Bernd
* config/arm/iterators.md (qhs_extenddi_op): New mode_attr.
	* config/arm/arm.md (zero_extend<mode>di2, extend<mode>di2): Use it
	for the source operand.

Comments

Richard Earnshaw Sept. 16, 2010, 10:04 a.m. UTC | #1 
On Thu, 2010-09-16 at 00:31 +0200, Bernd Schmidt wrote:
> On 09/01/2010 05:52 PM, Richard Earnshaw wrote:
> > On Tue, 2010-07-13 at 10:56 +0100, Bernd Schmidt wrote:
> >> This patch merges a number of different extend:DI patterns by using a
> >> QHSI mode_iterator.  It also removes separate patterns from thumb2.md
> >> as
> >> we can just set attr ce_count for ARM patterns as well.  I've
> >> completed
> >> what I'd partially done in my previous patch, which is to remove
> >> unnecessary constant pool handling from these patterns - none of them
> >> accept constants.
> 
> > The define_mode_attrs need to be moved to iterators.md.  Also, a number
> > of patterns have been changed (inconsistently with the rest of arm.md)
> > to not have the terminating ')' in column 1.
> >
> > Otherwise, OK.
> 
> This had one undesirable side effect.  The extendsidi patterns now 
> accept memory arguments, which can make it impossible for the combiner 
> to generate adddi_[zs]esidi patterns.  Fixed with this patch, regression 
> tested in the same way as the previous one.  Ok?
> 
> 
> Bernd

So as Uros points out, the constraints also need a macro substitution
(or you'll end up with a potentially invalid insn during reload).

Otherwise, OK.

R.
diff mbox

Patch

Index: gcc/config/arm/iterators.md
===================================================================
--- gcc/config/arm/iterators.md	(revision 163935)
+++ gcc/config/arm/iterators.md	(working copy)
@@ -374,6 +374,9 @@  (define_mode_attr V_unpack   [(V16QI "V8
 (define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")])
 (define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6")
 				      (QI "&& arm_arch6")])
+(define_mode_attr qhs_extenddi_op [(SI "s_register_operand")
+				   (HI "nonimmediate_operand")
+				   (QI "nonimmediate_operand")])
 
 ;;----------------------------------------------------------------------------
 ;; Code attributes
Index: gcc/config/arm/arm.md
===================================================================
--- gcc/config/arm/arm.md	(revision 163935)
+++ gcc/config/arm/arm.md	(working copy)
@@ -4039,7 +4039,7 @@  (define_expand "truncdfhf2"
 
 (define_insn "zero_extend<mode>di2"
   [(set (match_operand:DI 0 "s_register_operand" "=r")
-        (zero_extend:DI (match_operand:QHSI 1 "nonimmediate_operand" "rm")))]
+        (zero_extend:DI (match_operand:QHSI 1 "<qhs_extenddi_op>" "rm")))]
   "TARGET_32BIT <qhs_zextenddi_cond>"
   "#"
   [(set_attr "length" "8")
@@ -4049,7 +4049,7 @@  (define_insn "zero_extend<mode>di2"
 
 (define_insn "extend<mode>di2"
   [(set (match_operand:DI 0 "s_register_operand" "=r")
-        (sign_extend:DI (match_operand:QHSI 1 "nonimmediate_operand" "rm")))]
+        (sign_extend:DI (match_operand:QHSI 1 "<qhs_extenddi_op>" "rm")))]
   "TARGET_32BIT <qhs_sextenddi_cond>"
   "#"
   [(set_attr "length" "8")