| Message ID | 1460473007-11535-3-git-send-email-ldewangan@nvidia.com |
|---|---|
| State | New |
| Headers | show |
On Tue, Apr 12, 2016 at 08:26:42PM +0530, Laxman Dewangan wrote: > NVIDIA Tegra210 has extended the IO rails for new IO pads > and added some new IO rails on top of its previous SoC. > > Add all supported IO rails from Tegra210 to the Tegra PMC header. > > Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> > --- > include/soc/tegra/pmc.h | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/include/soc/tegra/pmc.h b/include/soc/tegra/pmc.h > index 07e332d..58fadc5 100644 > --- a/include/soc/tegra/pmc.h > +++ b/include/soc/tegra/pmc.h > @@ -90,22 +90,36 @@ int tegra_pmc_cpu_remove_clamping(unsigned int cpuid); > #define TEGRA_IO_RAIL_UART 14 > #define TEGRA_IO_RAIL_BB 15 > #define TEGRA_IO_RAIL_AUDIO 17 > +#define TEGRA_IO_RAIL_USB3 18 > #define TEGRA_IO_RAIL_HSIC 19 > #define TEGRA_IO_RAIL_COMP 22 > +#define TEGRA_IO_RAIL_DBG 25 > +#define TEGRA_IO_RAIL_DBG_NONAO 26 > +#define TEGRA_IO_RAIL_GPIO 27 > #define TEGRA_IO_RAIL_HDMI 28 > #define TEGRA_IO_RAIL_PEX_CNTRL 32 > #define TEGRA_IO_RAIL_SDMMC1 33 > #define TEGRA_IO_RAIL_SDMMC3 34 > #define TEGRA_IO_RAIL_SDMMC4 35 > +#define TEGRA_IO_RAIL_EMMC 35 > #define TEGRA_IO_RAIL_CAM 36 > #define TEGRA_IO_RAIL_RES 37 > +#define TEGRA_IO_RAIL_EMMC2 37 We have a duplicate entry for 37 now. The _RES might have meant "reserved", in which case maybe just replace it with the new symbolic name? Thierry
On Tuesday 12 April 2016 08:58 PM, Thierry Reding wrote: > * PGP Signed by an unknown key > > On Tue, Apr 12, 2016 at 08:26:42PM +0530, Laxman Dewangan wrote: >> NVIDIA Tegra210 has extended the IO rails for new IO pads >> and added some new IO rails on top of its previous SoC. >> >> Add all supported IO rails from Tegra210 to the Tegra PMC header. >> >> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> >> --- >> include/soc/tegra/pmc.h | 14 ++++++++++++++ >> 1 file changed, 14 insertions(+) >> >> diff --git a/include/soc/tegra/pmc.h b/include/soc/tegra/pmc.h >> index 07e332d..58fadc5 100644 >> --- a/include/soc/tegra/pmc.h >> +++ b/include/soc/tegra/pmc.h >> @@ -90,22 +90,36 @@ int tegra_pmc_cpu_remove_clamping(unsigned int cpuid); >> #define TEGRA_IO_RAIL_UART 14 >> #define TEGRA_IO_RAIL_BB 15 >> #define TEGRA_IO_RAIL_AUDIO 17 >> +#define TEGRA_IO_RAIL_USB3 18 >> #define TEGRA_IO_RAIL_HSIC 19 >> #define TEGRA_IO_RAIL_COMP 22 >> +#define TEGRA_IO_RAIL_DBG 25 >> +#define TEGRA_IO_RAIL_DBG_NONAO 26 >> +#define TEGRA_IO_RAIL_GPIO 27 >> #define TEGRA_IO_RAIL_HDMI 28 >> #define TEGRA_IO_RAIL_PEX_CNTRL 32 >> #define TEGRA_IO_RAIL_SDMMC1 33 >> #define TEGRA_IO_RAIL_SDMMC3 34 >> #define TEGRA_IO_RAIL_SDMMC4 35 >> +#define TEGRA_IO_RAIL_EMMC 35 >> #define TEGRA_IO_RAIL_CAM 36 >> #define TEGRA_IO_RAIL_RES 37 >> +#define TEGRA_IO_RAIL_EMMC2 37 > We have a duplicate entry for 37 now. The _RES might have meant > "reserved", in which case maybe just replace it with the new symbolic > name? OK, then make sense to replace RES with EMMC2. -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Tuesday 12 April 2016 11:33 PM, Jon Hunter wrote: > On 12/04/16 17:59, Laxman Dewangan wrote: >> On Tuesday 12 April 2016 08:58 PM, Thierry Reding wrote: >>> * PGP Signed by an unknown key >>> >>> On Tue, Apr 12, 2016 at 08:26:42PM +0530, Laxman Dewangan wrote: >>>> +#define TEGRA_IO_RAIL_EMMC 35 >>>> #define TEGRA_IO_RAIL_CAM 36 >>>> #define TEGRA_IO_RAIL_RES 37 >>>> +#define TEGRA_IO_RAIL_EMMC2 37 >>> We have a duplicate entry for 37 now. The _RES might have meant >>> "reserved", in which case maybe just replace it with the new symbolic >>> name? >> OK, then make sense to replace RES with EMMC2. > Looking at the Tegra124 TRM it was reserved and so renaming makes sense > here. However, that also prompts the question how do we check to ensure > that the IO rail is valid for a given SoC? > > Should we define a 'valid' mask for IO_DPD_STATUS and IO_DPD2_STATUS > registers in the SoC data so we can check if the rail is valid? > Yes, that is good idea. Infact, we should decouple RAIL_ID with the bit location of register. This will help on mapping any rail ID to SoC specific bit location and need not to worry if bit location of rail get changed on any generation. Local lookup table from ID to bit location can make validation as well as the decoupling. -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 12/04/16 17:59, Laxman Dewangan wrote: > > On Tuesday 12 April 2016 08:58 PM, Thierry Reding wrote: >> * PGP Signed by an unknown key >> >> On Tue, Apr 12, 2016 at 08:26:42PM +0530, Laxman Dewangan wrote: >>> NVIDIA Tegra210 has extended the IO rails for new IO pads >>> and added some new IO rails on top of its previous SoC. >>> >>> Add all supported IO rails from Tegra210 to the Tegra PMC header. >>> >>> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> >>> --- >>> include/soc/tegra/pmc.h | 14 ++++++++++++++ >>> 1 file changed, 14 insertions(+) >>> >>> diff --git a/include/soc/tegra/pmc.h b/include/soc/tegra/pmc.h >>> index 07e332d..58fadc5 100644 >>> --- a/include/soc/tegra/pmc.h >>> +++ b/include/soc/tegra/pmc.h >>> @@ -90,22 +90,36 @@ int tegra_pmc_cpu_remove_clamping(unsigned int >>> cpuid); >>> #define TEGRA_IO_RAIL_UART 14 >>> #define TEGRA_IO_RAIL_BB 15 >>> #define TEGRA_IO_RAIL_AUDIO 17 >>> +#define TEGRA_IO_RAIL_USB3 18 >>> #define TEGRA_IO_RAIL_HSIC 19 >>> #define TEGRA_IO_RAIL_COMP 22 >>> +#define TEGRA_IO_RAIL_DBG 25 >>> +#define TEGRA_IO_RAIL_DBG_NONAO 26 >>> +#define TEGRA_IO_RAIL_GPIO 27 >>> #define TEGRA_IO_RAIL_HDMI 28 >>> #define TEGRA_IO_RAIL_PEX_CNTRL 32 >>> #define TEGRA_IO_RAIL_SDMMC1 33 >>> #define TEGRA_IO_RAIL_SDMMC3 34 >>> #define TEGRA_IO_RAIL_SDMMC4 35 >>> +#define TEGRA_IO_RAIL_EMMC 35 >>> #define TEGRA_IO_RAIL_CAM 36 >>> #define TEGRA_IO_RAIL_RES 37 >>> +#define TEGRA_IO_RAIL_EMMC2 37 >> We have a duplicate entry for 37 now. The _RES might have meant >> "reserved", in which case maybe just replace it with the new symbolic >> name? > > OK, then make sense to replace RES with EMMC2. Looking at the Tegra124 TRM it was reserved and so renaming makes sense here. However, that also prompts the question how do we check to ensure that the IO rail is valid for a given SoC? Should we define a 'valid' mask for IO_DPD_STATUS and IO_DPD2_STATUS registers in the SoC data so we can check if the rail is valid? Cheers Jon -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/include/soc/tegra/pmc.h b/include/soc/tegra/pmc.h index 07e332d..58fadc5 100644 --- a/include/soc/tegra/pmc.h +++ b/include/soc/tegra/pmc.h @@ -90,22 +90,36 @@ int tegra_pmc_cpu_remove_clamping(unsigned int cpuid); #define TEGRA_IO_RAIL_UART 14 #define TEGRA_IO_RAIL_BB 15 #define TEGRA_IO_RAIL_AUDIO 17 +#define TEGRA_IO_RAIL_USB3 18 #define TEGRA_IO_RAIL_HSIC 19 #define TEGRA_IO_RAIL_COMP 22 +#define TEGRA_IO_RAIL_DBG 25 +#define TEGRA_IO_RAIL_DBG_NONAO 26 +#define TEGRA_IO_RAIL_GPIO 27 #define TEGRA_IO_RAIL_HDMI 28 #define TEGRA_IO_RAIL_PEX_CNTRL 32 #define TEGRA_IO_RAIL_SDMMC1 33 #define TEGRA_IO_RAIL_SDMMC3 34 #define TEGRA_IO_RAIL_SDMMC4 35 +#define TEGRA_IO_RAIL_EMMC 35 #define TEGRA_IO_RAIL_CAM 36 #define TEGRA_IO_RAIL_RES 37 +#define TEGRA_IO_RAIL_EMMC2 37 #define TEGRA_IO_RAIL_HV 38 #define TEGRA_IO_RAIL_DSIB 39 #define TEGRA_IO_RAIL_DSIC 40 #define TEGRA_IO_RAIL_DSID 41 +#define TEGRA_IO_RAIL_CSIC 42 +#define TEGRA_IO_RAIL_CSID 43 #define TEGRA_IO_RAIL_CSIE 44 +#define TEGRA_IO_RAIL_CSIF 45 +#define TEGRA_IO_RAIL_SPI 46 +#define TEGRA_IO_RAIL_SPI_HV 47 +#define TEGRA_IO_RAIL_DMIC 50 +#define TEGRA_IO_RAIL_DP 51 #define TEGRA_IO_RAIL_LVDS 57 #define TEGRA_IO_RAIL_SYS_DDC 58 +#define TEGRA_IO_RAIL_AUDIO_HV 61 #ifdef CONFIG_ARCH_TEGRA int tegra_powergate_is_powered(unsigned int id);
NVIDIA Tegra210 has extended the IO rails for new IO pads and added some new IO rails on top of its previous SoC. Add all supported IO rails from Tegra210 to the Tegra PMC header. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> --- include/soc/tegra/pmc.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+)