| Message ID | 20100309015644.133975091@redhat.com |
|---|---|
| State | New |
| Headers | show |
On 03/09/2010 03:53 AM, Marcelo Tosatti wrote: > Signed-off-by: Marcelo Tosatti<mtosatti@redhat.com> > > Index: qemu-kvm-uq/target-i386/helper.c > =================================================================== > --- qemu-kvm-uq.orig/target-i386/helper.c > +++ qemu-kvm-uq/target-i386/helper.c > @@ -1176,6 +1176,7 @@ void cpu_dump_state(CPUState *env, FILE > cpu_x86_dump_seg_cache(env, f, cpu_fprintf, "TR",&env->tr); > > #ifdef TARGET_X86_64 > + cpu_fprintf(f, "EFER= %016" PRIx64 "\n", env->efer); > if (env->hflags& HF_LMA_MASK) { > cpu_fprintf(f, "GDT= %016" PRIx64 " %08x\n", > env->gdt.base, env->gdt.limit); > > Better to do this for i386 too, no?
On Thu, Mar 11, 2010 at 10:35:21AM +0200, Avi Kivity wrote: > On 03/09/2010 03:53 AM, Marcelo Tosatti wrote: > >Signed-off-by: Marcelo Tosatti<mtosatti@redhat.com> > > > >Index: qemu-kvm-uq/target-i386/helper.c > >=================================================================== > >--- qemu-kvm-uq.orig/target-i386/helper.c > >+++ qemu-kvm-uq/target-i386/helper.c > >@@ -1176,6 +1176,7 @@ void cpu_dump_state(CPUState *env, FILE > > cpu_x86_dump_seg_cache(env, f, cpu_fprintf, "TR",&env->tr); > > > > #ifdef TARGET_X86_64 > >+ cpu_fprintf(f, "EFER= %016" PRIx64 "\n", env->efer); > > if (env->hflags& HF_LMA_MASK) { > > cpu_fprintf(f, "GDT= %016" PRIx64 " %08x\n", > > env->gdt.base, env->gdt.limit); > > > > Better to do this for i386 too, no? "On systems that support IA-32e mode, the extended feature enable register (IA32_EFER) is available. This model-specific register controls activation of IA-32e mode and other IA-32e mode operations." Can it be useful for i386 too?
On 03/11/2010 08:53 PM, Marcelo Tosatti wrote: > On Thu, Mar 11, 2010 at 10:35:21AM +0200, Avi Kivity wrote: > >> On 03/09/2010 03:53 AM, Marcelo Tosatti wrote: >> >>> Signed-off-by: Marcelo Tosatti<mtosatti@redhat.com> >>> >>> Index: qemu-kvm-uq/target-i386/helper.c >>> =================================================================== >>> --- qemu-kvm-uq.orig/target-i386/helper.c >>> +++ qemu-kvm-uq/target-i386/helper.c >>> @@ -1176,6 +1176,7 @@ void cpu_dump_state(CPUState *env, FILE >>> cpu_x86_dump_seg_cache(env, f, cpu_fprintf, "TR",&env->tr); >>> >>> #ifdef TARGET_X86_64 >>> + cpu_fprintf(f, "EFER= %016" PRIx64 "\n", env->efer); >>> if (env->hflags& HF_LMA_MASK) { >>> cpu_fprintf(f, "GDT= %016" PRIx64 " %08x\n", >>> env->gdt.base, env->gdt.limit); >>> >>> >> Better to do this for i386 too, no? >> > "On systems that support IA-32e mode, the extended feature enable > register (IA32_EFER) is available. This model-specific register controls > activation of IA-32e mode and other IA-32e mode operations." > > Can it be useful for i386 too? > That's on Intel. AMDs had EFER before 64-bit support (for syscall support, and nx), IIRC.
Index: qemu-kvm-uq/target-i386/helper.c =================================================================== --- qemu-kvm-uq.orig/target-i386/helper.c +++ qemu-kvm-uq/target-i386/helper.c @@ -1176,6 +1176,7 @@ void cpu_dump_state(CPUState *env, FILE cpu_x86_dump_seg_cache(env, f, cpu_fprintf, "TR", &env->tr); #ifdef TARGET_X86_64 + cpu_fprintf(f, "EFER= %016" PRIx64 "\n", env->efer); if (env->hflags & HF_LMA_MASK) { cpu_fprintf(f, "GDT= %016" PRIx64 " %08x\n", env->gdt.base, env->gdt.limit);
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>