commit 4b59da521f7e0aedff75c2aa90b6a653727cdf7f
Author: Guenter Roeck <linux@roeck-us.net>
Date: Tue Jul 7 11:11:20 2015 -0700
The PCI subsystem always assumes that I/O is supported on PCIe bridges and
tries to assign an I/O window to each child bus even if that is not the
case.
This may result in messages such as:
pcieport 0000:02:00.0: res[7]=[io 0x1000-0x0fff] get_res_add_size add_size 1000
pcieport 0000:02:00.0: BAR 7: no space for [io size 0x1000]
pcieport 0000:02:00.0: BAR 7: failed to assign [io size 0x1000]
for each bridge port, even if a bus or its parent does not support I/O in
the first place.
To avoid this message, check if a bus supports I/O before trying to enable
it. Also check if the root bus has an IO window assigned; if not, it does
not make sense to try to assign one to any of its child busses.
[bhelgaas: reverse sense of new pci_bus_flags_t value]
[yinghai: simplify root bus flag check, fix flags initial setting, change to bool]
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
drivers/pci/probe.c | 51 ++++++++++++++++++++++++++++++++++++++++++++++++
drivers/pci/setup-bus.c | 11 ++--------
include/linux/pci.h | 1
3 files changed, 55 insertions(+), 8 deletions(-)
===================================================================
@@ -332,6 +332,32 @@ static void pci_read_bases(struct pci_de
}
}
+static bool pci_bridge_supports_io(struct pci_dev *bridge)
+{
+ u16 io;
+
+ pci_read_config_word(bridge, PCI_IO_BASE, &io);
+ if (io)
+ return true;
+
+ /* IO_BASE/LIMIT is either hard-wired to zero or programmed to zero */
+ pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
+ pci_read_config_word(bridge, PCI_IO_BASE, &io);
+ pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
+ if (io)
+ return true;
+
+ return false;
+}
+
+static bool pci_root_has_io_resource(struct pci_bus *bus)
+{
+ while (bus->parent)
+ bus = bus->parent;
+
+ return !!(bus->bus_flags & PCI_BUS_FLAGS_SUPPORTS_IO);
+}
+
static void pci_read_bridge_io(struct pci_bus *child)
{
struct pci_dev *dev = child->self;
@@ -340,6 +366,21 @@ static void pci_read_bridge_io(struct pc
struct pci_bus_region region;
struct resource *res;
+ if (!(child->bus_flags & PCI_BUS_FLAGS_SUPPORTS_IO))
+ return;
+
+ if (!pci_bridge_supports_io(dev)) {
+ dev_printk(KERN_DEBUG, &dev->dev, " no I/O window\n");
+ child->bus_flags &= ~PCI_BUS_FLAGS_SUPPORTS_IO;
+ return;
+ }
+
+ if (!pci_root_has_io_resource(child)) {
+ dev_printk(KERN_DEBUG, &dev->dev, " no I/O resource on root bus\n");
+ child->bus_flags &= ~PCI_BUS_FLAGS_SUPPORTS_IO;
+ return;
+ }
+
io_mask = PCI_IO_RANGE_MASK;
io_granularity = 0x1000;
if (dev->io_window_1k) {
@@ -496,6 +537,7 @@ static struct pci_bus *pci_alloc_bus(str
INIT_LIST_HEAD(&b->resources);
b->max_bus_speed = PCI_SPEED_UNKNOWN;
b->cur_bus_speed = PCI_SPEED_UNKNOWN;
+ b->bus_flags |= PCI_BUS_FLAGS_SUPPORTS_IO;
#ifdef CONFIG_PCI_DOMAINS_GENERIC
if (parent)
b->domain_nr = parent->domain_nr;
@@ -2058,6 +2100,15 @@ int pci_bus_insert_busn_res(struct pci_b
res->flags |= IORESOURCE_PCI_FIXED;
}
+ b->bus_flags &= ~PCI_BUS_FLAGS_SUPPORTS_IO;
+ resource_list_for_each_entry(window, &bridge->windows) {
+ res = window->res;
+ if (resource_type(res) == IORESOURCE_IO) {
+ b->bus_flags |= PCI_BUS_FLAGS_SUPPORTS_IO;
+ break;
+ }
+ }
+
conflict = request_resource_conflict(parent_res, res);
if (conflict)
===================================================================
@@ -744,7 +744,6 @@ int pci_claim_bridge_resource(struct pci
base/limit registers must be read-only and read as 0. */
static void pci_bridge_check_ranges(struct pci_bus *bus)
{
- u16 io;
u32 pmem;
struct pci_dev *bridge = bus->self;
struct resource *b_res;
@@ -752,14 +751,10 @@ static void pci_bridge_check_ranges(stru
b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
b_res[1].flags |= IORESOURCE_MEM;
- pci_read_config_word(bridge, PCI_IO_BASE, &io);
- if (!io) {
- pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
- pci_read_config_word(bridge, PCI_IO_BASE, &io);
- pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
- }
- if (io)
+ if (bus->bus_flags & PCI_BUS_FLAGS_SUPPORTS_IO)
b_res[0].flags |= IORESOURCE_IO;
+ else
+ b_res[0].flags &= ~IORESOURCE_IO;
/* DECchip 21050 pass 2 errata: the bridge may miss an address
disconnect boundary by one PCI data phase.
===================================================================
@@ -193,6 +193,7 @@ typedef unsigned short __bitwise pci_bus
enum pci_bus_flags {
PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
+ PCI_BUS_FLAGS_SUPPORTS_IO = (__force pci_bus_flags_t) 4,
};
/* These values come from the PCI Express Spec */