| Message ID | 1435569083-47502-1-git-send-email-yongbok.kim@imgtec.com |
|---|---|
| State | New |
| Headers | show |
On 29/06/2015 10:11, Yongbok Kim wrote: > Fix core configuration for MIPS64R6-generic to make it as close as > I6400. > I6400 core has 48-bit of Virtual Address available (SEGBITS). > MIPS SIMD Architecture is available. > Rearrange order of bits to match the specification. > > Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> > --- > target-mips/mips-defs.h | 2 +- > target-mips/translate_init.c | 18 +++++++++--------- > 2 files changed, 10 insertions(+), 10 deletions(-) Applied to mips-next, thanks. Leon
On 2015-06-29 10:11, Yongbok Kim wrote: > Fix core configuration for MIPS64R6-generic to make it as close as > I6400. > I6400 core has 48-bit of Virtual Address available (SEGBITS). > MIPS SIMD Architecture is available. > Rearrange order of bits to match the specification. > > Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> > --- > target-mips/mips-defs.h | 2 +- > target-mips/translate_init.c | 18 +++++++++--------- > 2 files changed, 10 insertions(+), 10 deletions(-) Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> That said given we are getting closer to the I6400 CPU model, shouldn't we try to directly model a I6400 core (even if we have to disable some features like IEEE 754-2008 FP) instead of a generic MIPS64R6 core? > diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h > index 20aa87c..53b185e 100644 > --- a/target-mips/mips-defs.h > +++ b/target-mips/mips-defs.h > @@ -11,7 +11,7 @@ > #if defined(TARGET_MIPS64) > #define TARGET_LONG_BITS 64 > #define TARGET_PHYS_ADDR_SPACE_BITS 48 > -#define TARGET_VIRT_ADDR_SPACE_BITS 42 > +#define TARGET_VIRT_ADDR_SPACE_BITS 48 > #else > #define TARGET_LONG_BITS 32 > #define TARGET_PHYS_ADDR_SPACE_BITS 40 > diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c > index ddfaff8..9304e74 100644 > --- a/target-mips/translate_init.c > +++ b/target-mips/translate_init.c > @@ -655,14 +655,14 @@ static const mips_def_t mips_defs[] = > (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | > (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), > .CP0_Config2 = MIPS_CONFIG2, > - .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_RXI) | (1 << CP0C3_BP) | > - (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | (1 << CP0C3_LPA) | > - (1U << CP0C3_M), > - .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) | > - (3 << CP0C4_IE) | (1 << CP0C4_M), > + .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) | > + (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | > + (1 << CP0C3_RXI) | (1 << CP0C3_LPA), > + .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) | > + (0xfc << CP0C4_KScrExist), > .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_LLB), > - .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) | > - (1 << CP0C5_UFE), > + .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) | > + (1 << CP0C5_FRE) | (1 << CP0C5_UFE), > .CP0_LLAddr_rw_bitmask = 0, > .CP0_LLAddr_shift = 0, > .SYNCI_Step = 32, > @@ -674,9 +674,9 @@ static const mips_def_t mips_defs[] = > .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_F64) | (1 << FCR0_L) | > (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | > (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), > - .SEGBITS = 42, > + .SEGBITS = 48, > .PABITS = 48, > - .insn_flags = CPU_MIPS64R6, > + .insn_flags = CPU_MIPS64R6 | ASE_MSA, > .mmu_type = MMU_TYPE_R4000, > }, > { > -- > 1.7.5.4 > >
On 01/07/2015 14:48, Aurelien Jarno wrote: > On 2015-06-29 10:11, Yongbok Kim wrote: >> Fix core configuration for MIPS64R6-generic to make it as close as >> I6400. >> I6400 core has 48-bit of Virtual Address available (SEGBITS). >> MIPS SIMD Architecture is available. >> Rearrange order of bits to match the specification. >> >> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> >> --- >> target-mips/mips-defs.h | 2 +- >> target-mips/translate_init.c | 18 +++++++++--------- >> 2 files changed, 10 insertions(+), 10 deletions(-) > > Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> > > That said given we are getting closer to the I6400 CPU model, shouldn't > we try to directly model a I6400 core (even if we have to disable some > features like IEEE 754-2008 FP) instead of a generic MIPS64R6 core? > I fully agree with that but detailed specification of I6400 has not been published yet, therefore for the time being we will need to use the generic core name. However we could rename mips32r5-generic into P5600 with such restrictions - Hardware page table walk, Virtualization, EVA. What do you think? Regards, Yongbok
On 2015-07-01 14:57, Yongbok Kim wrote: > On 01/07/2015 14:48, Aurelien Jarno wrote: > > On 2015-06-29 10:11, Yongbok Kim wrote: > >> Fix core configuration for MIPS64R6-generic to make it as close as > >> I6400. > >> I6400 core has 48-bit of Virtual Address available (SEGBITS). > >> MIPS SIMD Architecture is available. > >> Rearrange order of bits to match the specification. > >> > >> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> > >> --- > >> target-mips/mips-defs.h | 2 +- > >> target-mips/translate_init.c | 18 +++++++++--------- > >> 2 files changed, 10 insertions(+), 10 deletions(-) > > > > Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> > > > > That said given we are getting closer to the I6400 CPU model, shouldn't > > we try to directly model a I6400 core (even if we have to disable some > > features like IEEE 754-2008 FP) instead of a generic MIPS64R6 core? > > > > I fully agree with that but detailed specification of I6400 has not been > published yet, therefore for the time being we will need to use the generic Oh ok. > core name. However we could rename mips32r5-generic into P5600 with such > restrictions - Hardware page table walk, Virtualization, EVA. > What do you think? I think it's a good idea, as long as we keep the config register in sync with what is actually implemented. That also reminds me that we should look at implementing hardware page table walk. That should be relatively easy to implement, and provide a huge performance boost (exceptions cost a lot on QEMU).
On 01/07/2015 15:06, Aurelien Jarno wrote: > On 2015-07-01 14:57, Yongbok Kim wrote: >> On 01/07/2015 14:48, Aurelien Jarno wrote: >>> On 2015-06-29 10:11, Yongbok Kim wrote: >>>> Fix core configuration for MIPS64R6-generic to make it as close as >>>> I6400. >>>> I6400 core has 48-bit of Virtual Address available (SEGBITS). >>>> MIPS SIMD Architecture is available. >>>> Rearrange order of bits to match the specification. >>>> >>>> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> >>>> --- >>>> target-mips/mips-defs.h | 2 +- >>>> target-mips/translate_init.c | 18 +++++++++--------- >>>> 2 files changed, 10 insertions(+), 10 deletions(-) >>> >>> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> >>> >>> That said given we are getting closer to the I6400 CPU model, shouldn't >>> we try to directly model a I6400 core (even if we have to disable some >>> features like IEEE 754-2008 FP) instead of a generic MIPS64R6 core? >>> >> >> I fully agree with that but detailed specification of I6400 has not been >> published yet, therefore for the time being we will need to use the generic > > Oh ok. > >> core name. However we could rename mips32r5-generic into P5600 with such >> restrictions - Hardware page table walk, Virtualization, EVA. >> What do you think? > > I think it's a good idea, as long as we keep the config register in sync > with what is actually implemented. > I will form a patch to do that. > That also reminds me that we should look at implementing hardware page > table walk. That should be relatively easy to implement, and provide a > huge performance boost (exceptions cost a lot on QEMU). > Actually I have implemented HTW (for MIPS32 only) but due to lack of resources, I couldn't upstream it for 2.4. Please have a look at below commits. https://github.com/yongbok/prpl-qemu/commit/b39e60b4039bb72ab5eccabfb75f6e6389d89bfd https://github.com/yongbok/prpl-qemu/commit/4fd75126c1d78d84a91c659de17a5bc45efdef27 Regards, Yongbok
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h index 20aa87c..53b185e 100644 --- a/target-mips/mips-defs.h +++ b/target-mips/mips-defs.h @@ -11,7 +11,7 @@ #if defined(TARGET_MIPS64) #define TARGET_LONG_BITS 64 #define TARGET_PHYS_ADDR_SPACE_BITS 48 -#define TARGET_VIRT_ADDR_SPACE_BITS 42 +#define TARGET_VIRT_ADDR_SPACE_BITS 48 #else #define TARGET_LONG_BITS 32 #define TARGET_PHYS_ADDR_SPACE_BITS 40 diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index ddfaff8..9304e74 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -655,14 +655,14 @@ static const mips_def_t mips_defs[] = (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_RXI) | (1 << CP0C3_BP) | - (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | (1 << CP0C3_LPA) | - (1U << CP0C3_M), - .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) | - (3 << CP0C4_IE) | (1 << CP0C4_M), + .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) | + (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | + (1 << CP0C3_RXI) | (1 << CP0C3_LPA), + .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) | + (0xfc << CP0C4_KScrExist), .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_LLB), - .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) | - (1 << CP0C5_UFE), + .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) | + (1 << CP0C5_FRE) | (1 << CP0C5_UFE), .CP0_LLAddr_rw_bitmask = 0, .CP0_LLAddr_shift = 0, .SYNCI_Step = 32, @@ -674,9 +674,9 @@ static const mips_def_t mips_defs[] = .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), - .SEGBITS = 42, + .SEGBITS = 48, .PABITS = 48, - .insn_flags = CPU_MIPS64R6, + .insn_flags = CPU_MIPS64R6 | ASE_MSA, .mmu_type = MMU_TYPE_R4000, }, {
Fix core configuration for MIPS64R6-generic to make it as close as I6400. I6400 core has 48-bit of Virtual Address available (SEGBITS). MIPS SIMD Architecture is available. Rearrange order of bits to match the specification. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> --- target-mips/mips-defs.h | 2 +- target-mips/translate_init.c | 18 +++++++++--------- 2 files changed, 10 insertions(+), 10 deletions(-)