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{ "id": 990094, "url": "http://patchwork.ozlabs.org/api/patches/990094/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1540804794-23269-1-git-send-email-priyanka.jain@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1540804794-23269-1-git-send-email-priyanka.jain@nxp.com>", "list_archive_url": null, "date": "2018-10-29T09:21:42", "name": "[U-Boot,v2] armv8: lx2160ardb : Add support for LX2160ARDB platform", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "9fe346411b6bac137a300fe18cbc719d81b5599a", "submitter": { "id": 70194, "url": "http://patchwork.ozlabs.org/api/people/70194/?format=api", "name": "Priyanka Jain", "email": "priyanka.jain@nxp.com" }, "delegate": { "id": 2666, "url": "http://patchwork.ozlabs.org/api/users/2666/?format=api", "username": "yorksun", "first_name": "York", "last_name": "Sun", "email": "yorksun@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1540804794-23269-1-git-send-email-priyanka.jain@nxp.com/mbox/", "series": [ { "id": 72965, "url": "http://patchwork.ozlabs.org/api/series/72965/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=72965", "date": "2018-10-29T09:21:42", "name": "[U-Boot,v2] armv8: lx2160ardb : Add support for LX2160ARDB platform", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/72965/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/990094/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/990094/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "LX2160ARDB is an evaluation board that supports LX2160A\nfamily SoCs. This patch add base support for this board.\n\nSigned-off-by: Wasim Khan <wasim.khan@nxp.com>\nSigned-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>\nSigned-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>\nSigned-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>\nSigned-off-by: Sriram Dash <sriram.dash@nxp.com>\nSigned-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>\nSigned-off-by: Pankit Garg <pankit.garg@nxp.com>\nSigned-off-by: Priyanka Jain <priyanka.jain@nxp.com>\n---\nChanges for v2:\n Rebased on top of test_qoriq branch of u-boot-fsl-qoriq.git\n\n Corrected line\n\tseria01.clock = get_serial_clock -> serial1.clock = get_serial_clock();\n\n Corrected CONFIG_ENV_OFFSET to 0x500000 [Thanks to Ashish K for pointing this]\n\n Depends on below patches[sequence in increasing order]\n 1)https://patchwork.ozlabs.org/patch/982258/\n 2)https://patchwork.ozlabs.org/patch/975541/\n 3)https://patchwork.ozlabs.org/patch/962408/\n 4)https://patchwork.ozlabs.org/patch/982259/\n 5)https://patchwork.ozlabs.org/patch/982237/\n 6)https://patchwork.ozlabs.org/patch/990088/\n 7)https://patchwork.ozlabs.org/patch/990093/\n\n arch/arm/Kconfig | 14 ++\n arch/arm/cpu/armv8/Kconfig | 2 +-\n arch/arm/dts/Makefile | 3 +-\n arch/arm/dts/fsl-lx2160a-rdb.dts | 20 +++\n board/freescale/common/qixis.c | 4 +\n board/freescale/lx2160a/Kconfig | 16 ++\n board/freescale/lx2160a/MAINTAINERS | 8 +\n board/freescale/lx2160a/Makefile | 9 +\n board/freescale/lx2160a/README | 79 +++++++++\n board/freescale/lx2160a/ddr.c | 20 +++\n board/freescale/lx2160a/eth_lx2160ardb.c | 210 +++++++++++++++++++++++\n board/freescale/lx2160a/lx2160a.c | 279 +++++++++++++++++++++++++++++++\n configs/lx2160ardb_tfa_defconfig | 74 ++++++++\n include/configs/lx2160a_common.h | 214 ++++++++++++++++++++++++\n include/configs/lx2160ardb.h | 102 +++++++++++\n 15 files changed, 1052 insertions(+), 2 deletions(-)\n create mode 100644 arch/arm/dts/fsl-lx2160a-rdb.dts\n create mode 100644 board/freescale/lx2160a/Kconfig\n create mode 100644 board/freescale/lx2160a/MAINTAINERS\n create mode 100644 board/freescale/lx2160a/Makefile\n create mode 100644 board/freescale/lx2160a/README\n create mode 100644 board/freescale/lx2160a/ddr.c\n create mode 100644 board/freescale/lx2160a/eth_lx2160ardb.c\n create mode 100644 board/freescale/lx2160a/lx2160a.c\n create mode 100644 configs/lx2160ardb_tfa_defconfig\n create mode 100644 include/configs/lx2160a_common.h\n create mode 100644 include/configs/lx2160ardb.h", "diff": "diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig\nindex ccf2a84..28a81e7 100644\n--- a/arch/arm/Kconfig\n+++ b/arch/arm/Kconfig\n@@ -1027,6 +1027,19 @@ config TARGET_LS2081ARDB\n \t development platform that supports the QorIQ LS2081A/LS2041A\n \t Layerscape Architecture processor.\n \n+config TARGET_LX2160ARDB\n+\tbool \"Support lx2160ardb\"\n+\tselect ARCH_LX2160A\n+\tselect ARCH_MISC_INIT\n+\tselect ARM64\n+\tselect ARMV8_MULTIENTRY\n+\tselect BOARD_LATE_INIT\n+\thelp\n+\t Support for NXP LX2160ARDB platform.\n+\t The lx2160ardb (LX2160A Reference design board (RDB)\n+\t is a high-performance development platform that supports the\n+\t QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.\n+\n config TARGET_HIKEY\n \tbool \"Support HiKey 96boards Consumer Edition Platform\"\n \tselect ARM64\n@@ -1488,6 +1501,7 @@ source \"board/freescale/ls1046ardb/Kconfig\"\n source \"board/freescale/ls1012aqds/Kconfig\"\n source \"board/freescale/ls1012ardb/Kconfig\"\n source \"board/freescale/ls1012afrdm/Kconfig\"\n+source \"board/freescale/lx2160a/Kconfig\"\n source \"board/freescale/mx35pdk/Kconfig\"\n source \"board/freescale/s32v234evb/Kconfig\"\n source \"board/grinn/chiliboard/Kconfig\"\ndiff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig\nindex c8bebab..aac3aeb 100644\n--- a/arch/arm/cpu/armv8/Kconfig\n+++ b/arch/arm/cpu/armv8/Kconfig\n@@ -105,7 +105,7 @@ config PSCI_RESET\n \t\t !TARGET_LS1012AFRWY && \\\n \t\t !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \\\n \t\t !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \\\n-\t\t !TARGET_LS2081ARDB && \\\n+\t\t !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \\\n \t\t !ARCH_UNIPHIER && !TARGET_S32V234EVB\n \thelp\n \t Most armv8 systems have PSCI support enabled in EL3, either through\ndiff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\nindex 44ebc50..25cd773 100644\n--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -226,7 +226,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \\\n \tfsl-ls2081a-rdb.dtb \\\n \tfsl-ls2088a-rdb-qspi.dtb \\\n \tfsl-ls1088a-rdb.dtb \\\n-\tfsl-ls1088a-qds.dtb\n+\tfsl-ls1088a-qds.dtb \\\n+\tfsl-lx2160a-rdb.dtb\n dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \\\n \tfsl-ls1043a-qds-lpuart.dtb \\\n \tfsl-ls1043a-rdb.dtb \\\ndiff --git a/arch/arm/dts/fsl-lx2160a-rdb.dts b/arch/arm/dts/fsl-lx2160a-rdb.dts\nnew file mode 100644\nindex 0000000..08201b5\n--- /dev/null\n+++ b/arch/arm/dts/fsl-lx2160a-rdb.dts\n@@ -0,0 +1,20 @@\n+// SPDX-License-Identifier: GPL-2.0+ OR X11\n+/*\n+ * NXP LX2160ARDB device tree source\n+ *\n+ * Author:\tPriyanka Jain <priyanka.jain@nxp.com>\n+ *\t\tSriram Dash <sriram.dash@nxp.com>\n+ *\n+ * Copyright 2018 NXP\n+ *\n+ */\n+\n+/dts-v1/;\n+\n+#include \"fsl-lx2160a.dtsi\"\n+\n+/ {\n+\tmodel = \"NXP Layerscape LX2160ARDB Board\";\n+\tcompatible = \"fsl,lx2160ardb\", \"fsl,lx2160a\";\n+\n+};\ndiff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c\nindex af3dc59..f1b98bc 100644\n--- a/board/freescale/common/qixis.c\n+++ b/board/freescale/common/qixis.c\n@@ -227,8 +227,12 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar\n #ifdef QIXIS_LBMAP_SD\n \t\tQIXIS_WRITE(rst_ctl, 0x30);\n \t\tQIXIS_WRITE(rcfg_ctl, 0);\n+#ifdef NON_EXTENDED_DUTCFG\n+\t\tQIXIS_WRITE(dutcfg[0], QIXIS_RCW_SRC_SD);\n+#else\n \t\tset_lbmap(QIXIS_LBMAP_SD);\n \t\tset_rcw_src(QIXIS_RCW_SRC_SD);\n+#endif\n \t\tQIXIS_WRITE(rcfg_ctl, 0x20);\n \t\tQIXIS_WRITE(rcfg_ctl, 0x21);\n #else\ndiff --git a/board/freescale/lx2160a/Kconfig b/board/freescale/lx2160a/Kconfig\nnew file mode 100644\nindex 0000000..5562c3e\n--- /dev/null\n+++ b/board/freescale/lx2160a/Kconfig\n@@ -0,0 +1,16 @@\n+if TARGET_LX2160ARDB\n+\n+config SYS_BOARD\n+\tdefault \"lx2160a\"\n+\n+config SYS_VENDOR\n+\tdefault \"freescale\"\n+\n+config SYS_SOC\n+\tdefault \"fsl-layerscape\"\n+\n+config SYS_CONFIG_NAME\n+\tdefault \"lx2160ardb\"\n+\n+source \"board/freescale/common/Kconfig\"\n+endif\ndiff --git a/board/freescale/lx2160a/MAINTAINERS b/board/freescale/lx2160a/MAINTAINERS\nnew file mode 100644\nindex 0000000..b4dd842\n--- /dev/null\n+++ b/board/freescale/lx2160a/MAINTAINERS\n@@ -0,0 +1,8 @@\n+LX2160ARDB BOARD\n+M:\tPriyanka Jain <priyanka.jain@nxp.com>\n+S:\tMaintained\n+F:\tboard/freescale/lx2160a/\n+F:\tinclude/configs/lx2160a_common.h\n+F:\tinclude/configs/lx2160ardb.h\n+F:\tconfigs/lx2160ardb_defconfig\n+F:\tarch/arm/dts/fsl-lx2160a-rdb.dts\ndiff --git a/board/freescale/lx2160a/Makefile b/board/freescale/lx2160a/Makefile\nnew file mode 100644\nindex 0000000..be3709d\n--- /dev/null\n+++ b/board/freescale/lx2160a/Makefile\n@@ -0,0 +1,9 @@\n+#\n+# Copyright 2018 Freescale Semiconductor\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+obj-y += lx2160a.o\n+obj-y += ddr.o\n+obj-$(CONFIG_TARGET_LX2160ARDB) += eth_lx2160ardb.o\ndiff --git a/board/freescale/lx2160a/README b/board/freescale/lx2160a/README\nnew file mode 100644\nindex 0000000..618c40b\n--- /dev/null\n+++ b/board/freescale/lx2160a/README\n@@ -0,0 +1,79 @@\n+Overview\n+--------\n+The LX2160A Reference Design (RDB) is a high-performance computing,\n+evaluation, and development platform that supports the QorIQ LX2160A\n+Layerscape Architecture processor and its personalities.\n+\n+LX2160A SoC Overview\n+--------------------------------------\n+For details, please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc\n+\n+LX2160ARDB board Overview\n+----------------------\n+DDR Memory\n+\tTwo ports of 72-bits (8-bits ECC) DDR4.\n+\tEach port supports four chip-selects and two DIMM\n+\tconnectors. Data rate upto 3.2 GT/s.\n+\n+SERDES ports\n+\tThress serdes controllers (24 lanes)\n+\tSerdes1: Supports two USXGMII connectors, each connected through\n+\tAquantia AQR107 phy, two 25GbE SFP+ modules connected through an Inphi\n+\tIN112525 phy and one 40 GbE QSFP+ module connected through an Inphi\n+\tCS4223 phy.\n+\n+\tSerdes2: Supports one PCIe x4 (Gen1/2/3/4) connector, four SATA 3.0\n+\tconnectors\n+\n+\tSerdes3: Supports one PCIe x8 (Gen1/2/3/4) connector\n+\n+eSDHC\n+\teSDHC1: Supports a SD connector for connecting SD cards\n+\teSDHC2: Supports 128GB Micron MTFC128GAJAECE-IT eMMC\n+\n+Octal SPI (XSPI)\n+\tSupports two 64 MB onbpard octal SPI flash memories, one SPI emulator\n+\tfor off-board emulation\n+\n+I2C\tAll system devices on I2C1 multiplexed using PCA9547 multiplexer\n+\tSerial Ports\n+\n+USB 3.0\n+\tTwo high speed USB 3.0 ports. First USB 3.0 port configured as\n+\tHost with Type-A connector, second USB 3.0 port configured as OTG\n+\twith micro-AB connector\n+\n+Serial Ports\tTwo UART ports\n+Ethernet\tTwo RGMII interfaces\n+Debug\t\tARM JTAG support\n+\n+Booting Options\n+---------------\n+a) Flexspi boot\n+b) SD boot\n+\n+Memory map for Flexspi flash\n+----------------------------\n+Image\t\t\t\t\t\t\tFlash Offset\n+bl2_flexspi_nor.pbl (RCW+PBI+bl2.pbl)\t\t\t0x00000000\n+fip.bin (bl31 + bl33(u-boot) +\n+\t header for Secure-boot(secure-boot only))\t0x00100000\n+Boot firmware Environment\t\t\t\t0x00500000\n+DDR PHY Firmware (fip_ddr_all.bin)\t\t\t0x00800000\n+DPAA2 MC Firmware\t\t\t\t\t0x00A00000\n+DPAA2 DPL\t\t\t\t\t\t0x00D00000\n+DPAA2 DPC\t\t\t\t\t\t0x00E00000\n+Kernel.itb\t\t\t\t\t\t0x01000000\n+\n+Memory map for sd card\n+----------------------------\n+Image\t\t\t\t\t\t\tSD card Offset\n+bl2_sd.pbl (RCW+PBI+bl2.pbl)\t\t\t\t0x00008\n+fip.bin (bl31 + bl33(u-boot) +\n+\t header for Secure-boot(secure-boot only))\t0x00800\n+Boot firmware Environment\t\t\t\t0x02800\n+DDR PHY Firmware (fip_ddr_all.bin)\t\t\t0x04000\n+DPAA2 MC Firmware\t\t\t\t\t0x05000\n+DPAA2 DPL\t\t\t\t\t\t0x06800\n+DPAA2 DPC\t\t\t\t\t\t0x07000\n+Kernel.itb\t\t\t\t\t\t0x08000\ndiff --git a/board/freescale/lx2160a/ddr.c b/board/freescale/lx2160a/ddr.c\nnew file mode 100644\nindex 0000000..cd422bf\n--- /dev/null\n+++ b/board/freescale/lx2160a/ddr.c\n@@ -0,0 +1,20 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright 2018 NXP\n+ */\n+\n+#include <common.h>\n+#include <fsl_ddr_sdram.h>\n+#include <fsl_ddr_dimm_params.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+int fsl_initdram(void)\n+{\n+\tgd->ram_size = tfa_get_dram_size();\n+\n+\tif (!gd->ram_size)\n+\t\tgd->ram_size = fsl_ddr_sdram_size();\n+\n+\treturn 0;\n+}\ndiff --git a/board/freescale/lx2160a/eth_lx2160ardb.c b/board/freescale/lx2160a/eth_lx2160ardb.c\nnew file mode 100644\nindex 0000000..ab75582\n--- /dev/null\n+++ b/board/freescale/lx2160a/eth_lx2160ardb.c\n@@ -0,0 +1,210 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright 2018 NXP\n+ *\n+ */\n+\n+#include <common.h>\n+#include <command.h>\n+#include <netdev.h>\n+#include <malloc.h>\n+#include <fsl_mdio.h>\n+#include <miiphy.h>\n+#include <phy.h>\n+#include <fm_eth.h>\n+#include <asm/io.h>\n+#include <exports.h>\n+#include <asm/arch/fsl_serdes.h>\n+#include <fsl-mc/fsl_mc.h>\n+#include <fsl-mc/ldpaa_wriop.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+static bool get_inphi_phy_id(struct mii_dev *bus, int addr, int devad)\n+{\n+\tint phy_reg;\n+\tu32 phy_id;\n+\n+\tphy_reg = bus->read(bus, addr, devad, MII_PHYSID1);\n+\tphy_id = (phy_reg & 0xffff) << 16;\n+\n+\tphy_reg = bus->read(bus, addr, devad, MII_PHYSID2);\n+\tphy_id |= (phy_reg & 0xffff);\n+\n+\tif (phy_id == PHY_UID_IN112525_S03)\n+\t\treturn true;\n+\telse\n+\t\treturn false;\n+}\n+\n+int board_eth_init(bd_t *bis)\n+{\n+#if defined(CONFIG_FSL_MC_ENET)\n+\tstruct memac_mdio_info mdio_info;\n+\tstruct memac_mdio_controller *reg;\n+\tint i, interface;\n+\tstruct mii_dev *dev;\n+\tstruct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);\n+\tu32 srds_s1;\n+\n+\tsrds_s1 = in_le32(&gur->rcwsr[28]) &\n+\t\t\t\tFSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;\n+\tsrds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;\n+\n+\treg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;\n+\tmdio_info.regs = reg;\n+\tmdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;\n+\n+\t/* Register the EMI 1 */\n+\tfm_memac_mdio_init(bis, &mdio_info);\n+\n+\treg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;\n+\tmdio_info.regs = reg;\n+\tmdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;\n+\n+\t/* Register the EMI 2 */\n+\tfm_memac_mdio_init(bis, &mdio_info);\n+\n+\tdev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);\n+\tswitch (srds_s1) {\n+\tcase 19:\n+\t\twriop_set_phy_address(WRIOP1_DPMAC2,\n+\t\t\t\t CORTINA_PHY_ADDR1);\n+\t\twriop_set_phy_address(WRIOP1_DPMAC3,\n+\t\t\t\t AQR107_PHY_ADDR1);\n+\t\twriop_set_phy_address(WRIOP1_DPMAC4,\n+\t\t\t\t AQR107_PHY_ADDR2);\n+\t\tif (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {\n+\t\t\twriop_set_phy_address(WRIOP1_DPMAC5,\n+\t\t\t\t\t INPHI_PHY_ADDR1);\n+\t\t\twriop_set_phy_address(WRIOP1_DPMAC6,\n+\t\t\t\t\t INPHI_PHY_ADDR1);\n+\t\t}\n+\t\twriop_set_phy_address(WRIOP1_DPMAC17,\n+\t\t\t\t RGMII_PHY_ADDR1);\n+\t\twriop_set_phy_address(WRIOP1_DPMAC18,\n+\t\t\t\t RGMII_PHY_ADDR2);\n+\t\tbreak;\n+\n+\tcase 18:\n+\t\twriop_set_phy_address(WRIOP1_DPMAC7,\n+\t\t\t\t CORTINA_PHY_ADDR1);\n+\t\twriop_set_phy_address(WRIOP1_DPMAC8,\n+\t\t\t\t CORTINA_PHY_ADDR1);\n+\t\twriop_set_phy_address(WRIOP1_DPMAC9,\n+\t\t\t\t CORTINA_PHY_ADDR1);\n+\t\twriop_set_phy_address(WRIOP1_DPMAC10,\n+\t\t\t\t CORTINA_PHY_ADDR1);\n+\t\twriop_set_phy_address(WRIOP1_DPMAC3,\n+\t\t\t\t AQR107_PHY_ADDR1);\n+\t\twriop_set_phy_address(WRIOP1_DPMAC4,\n+\t\t\t\t AQR107_PHY_ADDR2);\n+\t\tif (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {\n+\t\t\twriop_set_phy_address(WRIOP1_DPMAC5,\n+\t\t\t\t\t INPHI_PHY_ADDR1);\n+\t\t\twriop_set_phy_address(WRIOP1_DPMAC6,\n+\t\t\t\t\t INPHI_PHY_ADDR1);\n+\t\t}\n+\t\twriop_set_phy_address(WRIOP1_DPMAC17,\n+\t\t\t\t RGMII_PHY_ADDR1);\n+\t\twriop_set_phy_address(WRIOP1_DPMAC18,\n+\t\t\t\t RGMII_PHY_ADDR2);\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tprintf(\"SerDes1 protocol 0x%x is not supported on LX2160ARDB\\n\",\n+\t\t srds_s1);\n+\t\tgoto next;\n+\t}\n+\n+\tfor (i = WRIOP1_DPMAC2; i <= WRIOP1_DPMAC10; i++) {\n+\t\tinterface = wriop_get_enet_if(i);\n+\t\tswitch (interface) {\n+\t\tcase PHY_INTERFACE_MODE_XGMII:\n+\t\t\tdev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);\n+\t\t\twriop_set_mdio(i, dev);\n+\t\t\tbreak;\n+\t\tcase PHY_INTERFACE_MODE_25G_AUI:\n+\t\t\tdev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);\n+\t\t\twriop_set_mdio(i, dev);\n+\t\t\tbreak;\n+\t\tcase PHY_INTERFACE_MODE_XLAUI:\n+\t\t\tdev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);\n+\t\t\twriop_set_mdio(i, dev);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\tfor (i = WRIOP1_DPMAC17; i <= WRIOP1_DPMAC18; i++) {\n+\t\tinterface = wriop_get_enet_if(i);\n+\t\tswitch (interface) {\n+\t\tcase PHY_INTERFACE_MODE_RGMII:\n+\t\tcase PHY_INTERFACE_MODE_RGMII_ID:\n+\t\t\tdev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);\n+\t\t\twriop_set_mdio(i, dev);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+next:\n+\tcpu_eth_init(bis);\n+#endif /* CONFIG_FSL_MC_ENET */\n+\n+#ifdef CONFIG_PHY_AQUANTIA\n+\t/*\n+\t * Export functions to be used by AQ firmware\n+\t * upload application\n+\t */\n+\tgd->jt->strcpy = strcpy;\n+\tgd->jt->mdelay = mdelay;\n+\tgd->jt->mdio_get_current_dev = mdio_get_current_dev;\n+\tgd->jt->phy_find_by_mask = phy_find_by_mask;\n+\tgd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;\n+\tgd->jt->miiphy_set_current_dev = miiphy_set_current_dev;\n+#endif\n+\treturn pci_eth_init(bis);\n+}\n+\n+#if defined(CONFIG_RESET_PHY_R)\n+void reset_phy(void)\n+{\n+#if defined(CONFIG_FSL_MC_ENET)\n+\tmc_env_boot();\n+#endif\n+}\n+#endif /* CONFIG_RESET_PHY_R */\n+\n+int fdt_fixup_board_phy(void *fdt)\n+{\n+\tint mdio_offset;\n+\tint ret;\n+\tstruct mii_dev *dev;\n+\n+\tret = 0;\n+\n+\tdev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);\n+\tif (!get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {\n+\t\tmdio_offset = fdt_path_offset(fdt, \"/soc/mdio@0x8B97000\");\n+\n+\t\tif (mdio_offset < 0)\n+\t\t\tmdio_offset = fdt_path_offset(fdt, \"/mdio@0x8B97000\");\n+\n+\t\tif (mdio_offset < 0) {\n+\t\t\tprintf(\"mdio@0x8B9700 node not found in dts\\n\");\n+\t\t\treturn mdio_offset;\n+\t\t}\n+\n+\t\tret = fdt_setprop_string(fdt, mdio_offset, \"status\",\n+\t\t\t\t\t \"disabled\");\n+\t\tif (ret) {\n+\t\t\tprintf(\"Could not set disable mdio@0x8B97000 %s\\n\",\n+\t\t\t fdt_strerror(ret));\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\treturn ret;\n+}\ndiff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c\nnew file mode 100644\nindex 0000000..a62222e\n--- /dev/null\n+++ b/board/freescale/lx2160a/lx2160a.c\n@@ -0,0 +1,279 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright 2018 NXP\n+ */\n+\n+#include <common.h>\n+#include <dm.h>\n+#include <dm/platform_data/serial_pl01x.h>\n+#include <i2c.h>\n+#include <malloc.h>\n+#include <errno.h>\n+#include <netdev.h>\n+#include <fsl_ddr.h>\n+#include <fsl_sec.h>\n+#include <asm/io.h>\n+#include <fdt_support.h>\n+#include <linux/libfdt.h>\n+#include <fsl-mc/fsl_mc.h>\n+#include <environment.h>\n+#include <efi_loader.h>\n+#include <asm/arch/mmu.h>\n+#include <hwconfig.h>\n+#include <asm/arch/fsl_serdes.h>\n+#include <asm/arch/soc.h>\n+#include \"../common/qixis.h\"\n+#include \"../common/vid.h\"\n+#include <fsl_immap.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+static struct pl01x_serial_platdata serial0 = {\n+#if CONFIG_CONS_INDEX == 0\n+\t.base = CONFIG_SYS_SERIAL0,\n+#elif CONFIG_CONS_INDEX == 1\n+\t.base = CONFIG_SYS_SERIAL1,\n+#else\n+#error \"Unsupported console index value.\"\n+#endif\n+\t.type = TYPE_PL011,\n+};\n+\n+U_BOOT_DEVICE(nxp_serial0) = {\n+\t.name = \"serial_pl01x\",\n+\t.platdata = &serial0,\n+};\n+\n+static struct pl01x_serial_platdata serial1 = {\n+\t.base = CONFIG_SYS_SERIAL1,\n+\t.type = TYPE_PL011,\n+};\n+\n+U_BOOT_DEVICE(nxp_serial1) = {\n+\t.name = \"serial_pl01x\",\n+\t.platdata = &serial1,\n+};\n+\n+int select_i2c_ch_pca9547(u8 ch)\n+{\n+\tint ret;\n+\n+\tret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);\n+\tif (ret) {\n+\t\tputs(\"PCA: failed to select proper channel\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void uart_get_clock(void)\n+{\n+\tserial0.clock = get_serial_clock();\n+\tserial1.clock = get_serial_clock();\n+}\n+\n+int board_early_init_f(void)\n+{\n+#ifdef CONFIG_SYS_I2C_EARLY_INIT\n+\ti2c_early_init_f();\n+#endif\n+\t/* get required clock for UART IP */\n+\tuart_get_clock();\n+\n+\tfsl_lsch3_early_init_f();\n+\treturn 0;\n+}\n+\n+int esdhc_status_fixup(void *blob, const char *compat)\n+{\n+\t/* Enable both esdhc DT nodes for LX2160ARDB */\n+\tdo_fixup_by_compat(blob, compat, \"status\", \"okay\",\n+\t\t\t sizeof(\"okay\"), 1);\n+\n+\treturn 0;\n+}\n+\n+#if defined(CONFIG_VID)\n+int i2c_multiplexer_select_vid_channel(u8 channel)\n+{\n+\treturn select_i2c_ch_pca9547(channel);\n+}\n+\n+#endif\n+\n+int checkboard(void)\n+{\n+\tenum boot_src src = get_boot_src();\n+\tchar buf[64];\n+\tu8 sw;\n+\n+\tcpu_name(buf);\n+\tprintf(\"Board: %s-RDB, \", buf);\n+\n+\tsw = QIXIS_READ(arch);\n+\tprintf(\"Board version: %c, boot from \", (sw & 0xf) - 1 + 'A');\n+\n+\tif (src == BOOT_SOURCE_SD_MMC) {\n+\t\tputs(\"SD\\n\");\n+\t} else {\n+\t\tsw = QIXIS_READ(brdcfg[0]);\n+\t\tsw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;\n+\t\tswitch (sw) {\n+\t\tcase 0:\n+\t\tcase 4:\n+\t\t\tputs(\"FlexSPI DEV#0\\n\");\n+\t\t\tbreak;\n+\t\tcase 1:\n+\t\t\tputs(\"FlexSPI DEV#1\\n\");\n+\t\t\tbreak;\n+\t\tcase 2:\n+\t\tcase 3:\n+\t\t\tputs(\"FlexSPI EMU\\n\");\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tprintf(\"invalid setting, xmap: %d\\n\", sw);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\tprintf(\"FPGA: v%d.%d\\n\", QIXIS_READ(scver), QIXIS_READ(tagdata));\n+\n+\tputs(\"SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\\n\");\n+\tputs(\"SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\\n\");\n+\tputs(\"SERDES3 Reference: Clock1 = 100MHz Clock2 = 100Hz\\n\");\n+\treturn 0;\n+}\n+\n+unsigned long get_board_sys_clk(void)\n+{\n+\treturn 100000000;\n+}\n+\n+unsigned long get_board_ddr_clk(void)\n+{\n+\treturn 100000000;\n+}\n+\n+int board_init(void)\n+{\n+#ifdef CONFIG_ENV_IS_NOWHERE\n+\tgd->env_addr = (ulong)&default_environment[0];\n+#endif\n+\n+\tselect_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);\n+\n+#ifdef CONFIG_FSL_CAAM\n+\tsec_init();\n+#endif\n+\n+\treturn 0;\n+}\n+\n+void detail_board_ddr_info(void)\n+{\n+\tint i;\n+\tu64 ddr_size = 0;\n+\n+\tputs(\"\\nDDR \");\n+\tfor (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)\n+\t\tddr_size += gd->bd->bi_dram[i].size;\n+\tprint_size(ddr_size, \"\");\n+\tprint_ddr_info(0);\n+}\n+\n+#if defined(CONFIG_ARCH_MISC_INIT)\n+int arch_misc_init(void)\n+{\n+\treturn 0;\n+}\n+#endif\n+\n+#ifdef CONFIG_FSL_MC_ENET\n+extern int fdt_fixup_board_phy(void *fdt);\n+\n+void fdt_fixup_board_enet(void *fdt)\n+{\n+\tint offset;\n+\n+\toffset = fdt_path_offset(fdt, \"/soc/fsl-mc\");\n+\n+\tif (offset < 0)\n+\t\toffset = fdt_path_offset(fdt, \"/fsl-mc\");\n+\n+\tif (offset < 0) {\n+\t\tprintf(\"%s: fsl-mc node not found in device tree (error %d)\\n\",\n+\t\t __func__, offset);\n+\t\treturn;\n+\t}\n+\n+\tif ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0)) {\n+\t\tfdt_status_okay(fdt, offset);\n+\t\tfdt_fixup_board_phy(fdt);\n+\t} else {\n+\t\tfdt_status_fail(fdt, offset);\n+\t}\n+}\n+\n+void board_quiesce_devices(void)\n+{\n+\tfsl_mc_ldpaa_exit(gd->bd);\n+}\n+#endif\n+\n+#ifdef CONFIG_OF_BOARD_SETUP\n+\n+int ft_board_setup(void *blob, bd_t *bd)\n+{\n+\tint i;\n+\tu64 base[CONFIG_NR_DRAM_BANKS];\n+\tu64 size[CONFIG_NR_DRAM_BANKS];\n+\n+\tft_cpu_setup(blob, bd);\n+\n+\t/* fixup DT for the three GPP DDR banks */\n+\tfor (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {\n+\t\tbase[i] = gd->bd->bi_dram[i].start;\n+\t\tsize[i] = gd->bd->bi_dram[i].size;\n+\t}\n+\n+#ifdef CONFIG_RESV_RAM\n+\t/* reduce size if reserved memory is within this bank */\n+\tif (gd->arch.resv_ram >= base[0] &&\n+\t gd->arch.resv_ram < base[0] + size[0])\n+\t\tsize[0] = gd->arch.resv_ram - base[0];\n+\telse if (gd->arch.resv_ram >= base[1] &&\n+\t\t gd->arch.resv_ram < base[1] + size[1])\n+\t\tsize[1] = gd->arch.resv_ram - base[1];\n+\telse if (gd->arch.resv_ram >= base[2] &&\n+\t\t gd->arch.resv_ram < base[2] + size[2])\n+\t\tsize[2] = gd->arch.resv_ram - base[2];\n+#endif\n+\n+\tfdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);\n+\n+#ifdef CONFIG_USB\n+\tfsl_fdt_fixup_dr_usb(blob, bd);\n+#endif\n+\n+#ifdef CONFIG_FSL_MC_ENET\n+\tfdt_fsl_mc_fixup_iommu_map_entry(blob);\n+\tfdt_fixup_board_enet(blob);\n+#endif\n+\n+\treturn 0;\n+}\n+#endif\n+\n+void qixis_dump_switch(void)\n+{\n+\tint i, nr_of_cfgsw;\n+\n+\tQIXIS_WRITE(cms[0], 0x00);\n+\tnr_of_cfgsw = QIXIS_READ(cms[1]);\n+\n+\tputs(\"DIP switch settings dump:\\n\");\n+\tfor (i = 1; i <= nr_of_cfgsw; i++) {\n+\t\tQIXIS_WRITE(cms[0], i);\n+\t\tprintf(\"SW%d = (0x%02x)\\n\", i, QIXIS_READ(cms[1]));\n+\t}\n+}\ndiff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig\nnew file mode 100644\nindex 0000000..fb1102e\n--- /dev/null\n+++ b/configs/lx2160ardb_tfa_defconfig\n@@ -0,0 +1,74 @@\n+CONFIG_ARM=y\n+CONFIG_TARGET_LX2160ARDB=y\n+CONFIG_SYS_TEXT_BASE=0x82000000\n+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y\n+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y\n+CONFIG_DEFAULT_DEVICE_TREE=\"fsl-lx2160a-rdb\"\n+CONFIG_NR_DRAM_BANKS=3\n+CONFIG_DM=y\n+CONFIG_FIT=y\n+CONFIG_FIT_VERBOSE=y\n+CONFIG_OF_BOARD_SETUP=y\n+CONFIG_OF_STDOUT_VIA_ALIAS=y\n+CONFIG_TFABOOT=y\n+CONFIG_BOOTDELAY=10\n+CONFIG_USE_BOOTARGS=y\n+CONFIG_BOOTARGS=\"console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf\"\n+# CONFIG_CMD_IMLS is not set\n+CONFIG_CMD_GREPENV=y\n+CONFIG_CMD_EEPROM=y\n+CONFIG_CMD_GPT=y\n+CONFIG_CMD_I2C=y\n+CONFIG_CMD_MMC=y\n+CONFIG_CMD_SF=y\n+CONFIG_CMD_USB=y\n+CONFIG_CMD_CACHE=y\n+CONFIG_MP=y\n+CONFIG_OF_CONTROL=y\n+CONFIG_ENV_IS_IN_MMC=y\n+CONFIG_NET_RANDOM_ETHADDR=y\n+CONFIG_DM_SERIAL=y\n+CONFIG_CONS_INDEX=0\n+CONFIG_FSL_CAAM=y\n+CONFIG_FSL_ESDHC=y\n+CONFIG_SPI=y\n+CONFIG_DM_SPI=y\n+CONFIG_DM_SPI_FLASH=y\n+CONFIG_SPI_FLASH=y\n+CONFIG_SPI_FLASH_STMICRO=y\n+CONFIG_SPI_FLASH_USE_4K_SECTORS=n\n+CONFIG_SPI_FLASH_SPANSION=y\n+CONFIG_NXP_FSPI=y\n+CONFIG_FSPI_AHB_EN_4BYTE=y\n+CONFIG_SYS_FSPI_AHB_INIT=y\n+CONFIG_PHYLIB=y\n+CONFIG_NETDEVICES=y\n+CONFIG_PHY_GIGE=y\n+CONFIG_CMD_NET=y\n+CONFIG_CMD_PING=y\n+CONFIG_CMD_PXE=y\n+CONFIG_CMD_MII=y\n+CONFIG_CMD_DHCP=y\n+CONFIG_CMD_FAT=y\n+CONFIG_CMD_EXT2=y\n+CONFIG_NET=y\n+CONFIG_USB=y\n+CONFIG_DM_USB=y\n+CONFIG_USB_XHCI_HCD=y\n+CONFIG_USB_XHCI_DWC3=y\n+CONFIG_USB_STORAGE=y\n+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y\n+CONFIG_SCSI_AHCI=y\n+CONFIG_SCSI=y\n+# CONFIG_SYS_FSL_DDR_PHY is not set\n+CONFIG_SYS_GEN2_DDR_PHY=y\n+CONFIG_SYS_MALLOC_F=y\n+CONFIG_SYS_MALLOC_F_LEN=0x6000\n+CONFIG_PHYLIB_10G=y\n+CONFIG_PHY_AQUANTIA=y\n+CONFIG_PHY_CORTINA=y\n+CONFIG_PHY_ATHEROS=y\n+CONFIG_PHY_INPHI=y\n+CONFIG_INPHI_25G=y\n+CONFIG_HUSH_PARSER=y\n+CONFIG_EMC2305=y\ndiff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h\nnew file mode 100644\nindex 0000000..5c08c87\n--- /dev/null\n+++ b/include/configs/lx2160a_common.h\n@@ -0,0 +1,214 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * Copyright 2018 NXP\n+ */\n+\n+#ifndef __LX2_COMMON_H\n+#define __LX2_COMMON_H\n+\n+#include <asm/arch/stream_id_lsch3.h>\n+#include <asm/arch/config.h>\n+#include <asm/arch/soc.h>\n+\n+#define CONFIG_REMAKE_ELF\n+#define CONFIG_FSL_LAYERSCAPE\n+#define CONFIG_GICV3\n+#define CONFIG_FSL_TZPC_BP147\n+#define CONFIG_FSL_MEMAC\n+\n+#define CONFIG_SYS_INIT_SP_ADDR\t\tCONFIG_SYS_TEXT_BASE\n+#define CONFIG_SYS_FLASH_BASE\t\t0x20000000\n+\n+#define CONFIG_SKIP_LOWLEVEL_INIT\n+#define CONFIG_BOARD_EARLY_INIT_F\t1\n+\n+/* DDR */\n+#define CONFIG_FSL_DDR_INTERACTIVE\t/* Interactive debugging */\n+#define CONFIG_SYS_FSL_DDR_INTLV_256B\t/* force 256 byte interleaving */\n+#define CONFIG_VERY_BIG_RAM\n+#define CONFIG_SYS_DDR_SDRAM_BASE\t\t0x80000000UL\n+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY\t0\n+#define CONFIG_SYS_DDR_BLOCK2_BASE\t\t0x2080000000ULL\n+#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS\t2\n+#define CONFIG_SYS_SDRAM_SIZE\t\t\t0x200000000UL\n+#define CONFIG_DDR_SPD\n+#define CONFIG_DDR_ECC\n+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER\n+#define CONFIG_SYS_SDRAM_BASE\t\tCONFIG_SYS_DDR_SDRAM_BASE\n+#define CONFIG_MEM_INIT_VALUE\t\t0xdeadbeef\n+#define SPD_EEPROM_ADDRESS1\t\t0x51\n+#define SPD_EEPROM_ADDRESS2\t\t0x52\n+#define SPD_EEPROM_ADDRESS3\t\t0x53\n+#define SPD_EEPROM_ADDRESS4\t\t0x54\n+#define SPD_EEPROM_ADDRESS5\t\t0x55\n+#define SPD_EEPROM_ADDRESS6\t\t0x56\n+#define SPD_EEPROM_ADDRESS\t\tSPD_EEPROM_ADDRESS1\n+#define CONFIG_SYS_SPD_BUS_NUM\t\t0\t/* SPD on I2C bus 0 */\n+#define CONFIG_DIMM_SLOTS_PER_CTLR\t2\n+#define CONFIG_CHIP_SELECTS_PER_CTRL\t4\n+#define CONFIG_FSL_DDR_BIST\t/* enable built-in memory test */\n+#define CONFIG_SYS_MONITOR_LEN\t\t(936 * 1024)\n+\n+/* Miscellaneous configurable options */\n+#define CONFIG_SYS_LOAD_ADDR\t(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)\n+\n+/* SMP Definitinos */\n+#define CPU_RELEASE_ADDR\t\tsecondary_boot_func\n+\n+/* Generic Timer Definitions */\n+/*\n+ * This is not an accurate number. It is used in start.S. The frequency\n+ * will be udpated later when get_bus_freq(0) is available.\n+ */\n+\n+#define COUNTER_FREQUENCY\t\t25000000\t/* 25MHz */\n+\n+/* Size of malloc() pool */\n+#define CONFIG_SYS_MALLOC_LEN\t\t(CONFIG_ENV_SIZE + 2048 * 1024)\n+\n+/* Serial Port */\n+#define CONFIG_PL01X_SERIAL\n+#define CONFIG_PL011_CLOCK\t\t(get_bus_freq(0) / 4)\n+#define CONFIG_SYS_SERIAL0\t\t0x21c0000\n+#define CONFIG_SYS_SERIAL1\t\t0x21d0000\n+#define CONFIG_SYS_SERIAL2\t\t0x21e0000\n+#define CONFIG_SYS_SERIAL3\t\t0x21f0000\n+/*below might needs to be removed*/\n+#define CONFIG_PL01x_PORTS\t\t{(void *)CONFIG_SYS_SERIAL0, \\\n+\t\t\t\t\t(void *)CONFIG_SYS_SERIAL1, \\\n+\t\t\t\t\t(void *)CONFIG_SYS_SERIAL2, \\\n+\t\t\t\t\t(void *)CONFIG_SYS_SERIAL3 }\n+#define CONFIG_BAUDRATE\t\t\t115200\n+#define CONFIG_SYS_BAUDRATE_TABLE\t{ 9600, 19200, 38400, 57600, 115200 }\n+\n+/* MC firmware */\n+#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH\t\t0x20000\n+#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET\t0x00F00000\n+#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH\t\t0x20000\n+#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET\t0x00F20000\n+#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS\t5000\n+\n+/* Define phy_reset function to boot the MC based on mcinitcmd.\n+ * This happens late enough to properly fixup u-boot env MAC addresses.\n+ */\n+#define CONFIG_RESET_PHY_R\n+\n+/*\n+ * Carve out a DDR region which will not be used by u-boot/Linux\n+ *\n+ * It will be used by MC and Debug Server. The MC region must be\n+ * 512MB aligned, so the min size to hide is 512MB.\n+ */\n+#ifdef CONFIG_FSL_MC_ENET\n+#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE\t(512UL * 1024 * 1024)\n+#endif\n+\n+/* I2C bus multiplexer */\n+#define I2C_MUX_PCA_ADDR_PRI\t\t0x77 /* Primary Mux*/\n+#define I2C_MUX_CH_DEFAULT\t\t0x8\n+\n+/* RTC */\n+#define RTC\n+#define CONFIG_SYS_I2C_RTC_ADDR\t\t0x51 /* Channel 3*/\n+\n+/* EEPROM */\n+#define CONFIG_ID_EEPROM\n+#define CONFIG_SYS_I2C_EEPROM_NXID\n+#define CONFIG_SYS_EEPROM_BUS_NUM\t\t0\n+#define CONFIG_SYS_I2C_EEPROM_ADDR\t\t0x57\n+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN\t\t1\n+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS\t3\n+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS\t5\n+\n+/* Qixis */\n+#define CONFIG_FSL_QIXIS\n+#define CONFIG_QIXIS_I2C_ACCESS\n+#define CONFIG_SYS_I2C_FPGA_ADDR\t\t0x66\n+\n+/* PCI */\n+#ifdef CONFIG_PCI\n+#define CONFIG_SYS_PCI_64BIT\n+#define CONFIG_PCI_SCAN_SHOW\n+#endif\n+\n+/* MMC */\n+#ifdef CONFIG_MMC\n+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33\n+#endif\n+\n+/* SATA */\n+\n+#ifdef CONFIG_SCSI\n+#define CONFIG_SCSI_AHCI_PLAT\n+#define CONFIG_SYS_SATA1\t\tAHCI_BASE_ADDR1\n+#define CONFIG_SYS_SATA2\t\tAHCI_BASE_ADDR2\n+#define CONFIG_SYS_SCSI_MAX_SCSI_ID\t1\n+#define CONFIG_SYS_SCSI_MAX_LUN\t\t1\n+#define CONFIG_SYS_SCSI_MAX_DEVICE\t(CONFIG_SYS_SCSI_MAX_SCSI_ID * \\\n+\t\t\t\t\tCONFIG_SYS_SCSI_MAX_LUN)\n+#endif\n+\n+/* USB */\n+#ifdef CONFIG_USB\n+#define CONFIG_HAS_FSL_XHCI_USB\n+#define CONFIG_USB_MAX_CONTROLLER_COUNT\t2\n+#endif\n+\n+/* FlexSPI */\n+#ifdef CONFIG_NXP_FSPI\n+#define NXP_FSPI_FLASH_SIZE\t\tSZ_64M\n+#define NXP_FSPI_FLASH_NUM\t\t1\n+#endif\n+\n+#ifndef __ASSEMBLY__\n+unsigned long get_board_sys_clk(void);\n+unsigned long get_board_ddr_clk(void);\n+#endif\n+\n+#define CONFIG_SYS_CLK_FREQ\t\tget_board_sys_clk()\n+#define CONFIG_DDR_CLK_FREQ\t\tget_board_ddr_clk()\n+#define COUNTER_FREQUENCY_REAL\t\t(CONFIG_SYS_CLK_FREQ / 4)\n+\n+#define CONFIG_HWCONFIG\n+#define HWCONFIG_BUFFER_SIZE\t\t128\n+\n+#define CONFIG_SYS_MMC_ENV_DEV 0\n+#define CONFIG_ENV_SIZE\t\t\t0x2000 /* 8KB */\n+#define CONFIG_ENV_SECT_SIZE\t\t0x20000\n+#define CONFIG_ENV_OFFSET\t\t0x500000\n+#define CONFIG_ENV_ADDR\t\t\t(CONFIG_SYS_FLASH_BASE + \\\n+\t\t\t\t\t CONFIG_ENV_OFFSET)\n+\n+/* Allow to overwrite serial and ethaddr */\n+#define CONFIG_ENV_OVERWRITE\n+\n+/* Monitor Command Prompt */\n+#define CONFIG_SYS_CBSIZE\t\t512\t/* Console I/O Buffer Size */\n+#define CONFIG_SYS_PBSIZE\t\t(CONFIG_SYS_CBSIZE + \\\n+\t\t\t\t\tsizeof(CONFIG_SYS_PROMPT) + 16)\n+#define CONFIG_SYS_BARGSIZE\t\tCONFIG_SYS_CBSIZE /* Boot args buffer */\n+#define CONFIG_CMDLINE_EDITING\t\t1\n+#define CONFIG_SYS_MAXARGS\t\t64\t/* max command args */\n+\n+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */\n+\n+/* Initial environment variables */\n+#define XSPI_NOR_BOOTCOMMAND\t\"fsl_mc apply dpl 0x20d00000;\" \\\n+\t\t\t\t\"sf probe 0:0;\" \\\n+\t\t\t\t\"sf read 0xa0000000 0x1000000 0x3000000;\" \\\n+\t\t\t\t\"bootm 0xa0000000\"\n+\n+#define SD_BOOTCOMMAND\t\t\"mmc read 0xa0000000 0x6800 0xA0;\" \\\n+\t\t\t\t\"fsl_mc apply dpl 0xa0000000;\" \\\n+\t\t\t\t\"mmc read 0xb0000000 0x8000 0x1d000;\" \\\n+\t\t\t\t\"bootm 0xb0000000\"\n+\n+#define XSPI_MC_INIT_CMD\t\t\t\\\n+\t\"fsl_mc start mc 0x20a00000 0x20e00000\\0\"\n+\n+#define SD_MC_INIT_CMD\t\t\t\t\\\n+\t\"mmc read 0x80000000 0x5000 0x800;\"\t\\\n+\t\"mmc read 0x80100000 0x7000 0x800;\"\t\\\n+\t\"fsl_mc start mc 0x80000000 0x80100000\\0\"\n+\n+#endif /* __LX2_COMMON_H */\ndiff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h\nnew file mode 100644\nindex 0000000..67d214d\n--- /dev/null\n+++ b/include/configs/lx2160ardb.h\n@@ -0,0 +1,102 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * Copyright 2018 NXP\n+ */\n+\n+#ifndef __LX2_RDB_H\n+#define __LX2_RDB_H\n+\n+#include \"lx2160a_common.h\"\n+\n+/* Qixis */\n+#define QIXIS_XMAP_MASK\t\t\t0x07\n+#define QIXIS_XMAP_SHIFT\t\t5\n+#define QIXIS_RST_CTL_RESET_EN\t\t0x30\n+#define QIXIS_LBMAP_DFLTBANK\t\t0x00\n+#define QIXIS_LBMAP_ALTBANK\t\t0x20\n+#define QIXIS_LBMAP_QSPI\t\t0x00\n+#define QIXIS_RCW_SRC_QSPI\t\t0xff\n+#define QIXIS_RST_CTL_RESET\t\t0x31\n+#define QIXIS_RCFG_CTL_RECONFIG_IDLE\t0x20\n+#define QIXIS_RCFG_CTL_RECONFIG_START\t0x21\n+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE\t0x08\n+#define QIXIS_LBMAP_MASK\t\t0x0f\n+#define QIXIS_LBMAP_SD\n+#define QIXIS_RCW_SRC_SD 0x08\n+#define NON_EXTENDED_DUTCFG\n+\n+/* VID */\n+\n+#define I2C_MUX_CH_VOL_MONITOR\t\t0xA\n+/* Voltage monitor on channel 2*/\n+#define I2C_VOL_MONITOR_ADDR\t\t0x63\n+#define I2C_VOL_MONITOR_BUS_V_OFFSET\t0x2\n+#define I2C_VOL_MONITOR_BUS_V_OVF\t0x1\n+#define I2C_VOL_MONITOR_BUS_V_SHIFT\t3\n+#define CONFIG_VID_FLS_ENV\t\t\"lx2160ardb_vdd_mv\"\n+#define CONFIG_VID\n+\n+/* The lowest and highest voltage allowed*/\n+#define VDD_MV_MIN\t\t\t775\n+#define VDD_MV_MAX\t\t\t855\n+\n+/* PM Bus commands code for LTC3882*/\n+#define PMBUS_CMD_PAGE 0x0\n+#define PMBUS_CMD_READ_VOUT 0x8B\n+#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05\n+#define PMBUS_CMD_VOUT_COMMAND 0x21\n+#define PWM_CHANNEL0 0x0\n+\n+#define CONFIG_VOL_MONITOR_LTC3882_SET\n+#define CONFIG_VOL_MONITOR_LTC3882_READ\n+\n+/* RTC */\n+#define CONFIG_SYS_RTC_BUS_NUM\t\t4\n+\n+/* MAC/PHY configuration */\n+#if defined(CONFIG_FSL_MC_ENET)\n+#define CONFIG_MII\n+#define CONFIG_ETHPRIME\t\t\"DPMAC1@xgmii\"\n+\n+#define AQR107_PHY_ADDR1\t0x04\n+#define AQR107_PHY_ADDR2\t0x05\n+\n+#define CORTINA_NO_FW_UPLOAD\n+#define CORTINA_PHY_ADDR1\t0x0\n+#define INPHI_PHY_ADDR1\t\t0x0\n+\n+#define RGMII_PHY_ADDR1\t\t0x01\n+#define RGMII_PHY_ADDR2\t\t0x02\n+\n+#endif\n+\n+/* EEPROM */\n+#define CONFIG_ID_EEPROM\n+#define CONFIG_SYS_I2C_EEPROM_NXID\n+#define CONFIG_SYS_EEPROM_BUS_NUM\t 0\n+#define CONFIG_SYS_I2C_EEPROM_ADDR\t 0x57\n+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN\t 1\n+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3\n+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5\n+\n+/* Initial environment variables */\n+#define CONFIG_EXTRA_ENV_SETTINGS\t\t\\\n+\t\"hwconfig=fsl_ddr:bank_intlv=auto\\0\"\t\\\n+\t\"scriptaddr=0x80800000\\0\"\t\t\\\n+\t\"kernel_addr_r=0x81000000\\0\"\t\t\\\n+\t\"pxefile_addr_r=0x81000000\\0\"\t\t\\\n+\t\"fdt_addr_r=0x88000000\\0\"\t\t\\\n+\t\"ramdisk_addr_r=0x89000000\\0\"\t\t\\\n+\t\"loadaddr=0x80100000\\0\"\t\t\t\\\n+\t\"kernel_addr=0x100000\\0\"\t\t\\\n+\t\"ramdisk_addr=0x800000\\0\"\t\t\\\n+\t\"ramdisk_size=0x2000000\\0\"\t\t\\\n+\t\"fdt_high=0xa0000000\\0\"\t\t\t\\\n+\t\"initrd_high=0xffffffffffffffff\\0\"\t\\\n+\t\"kernel_start=0x21000000\\0\"\t\t\\\n+\t\"lx2160ardb_vdd_mv=800\\0\"\t\t\\\n+\t\"mcmemsize=0x40000000\\0\"\n+\n+#include <asm/fsl_secure_boot.h>\n+\n+#endif /* __LX2_RDB_H */\n", "prefixes": [ "U-Boot", "v2" ] }