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GET /api/patches/989736/?format=api
{ "id": 989736, "url": "http://patchwork.ozlabs.org/api/patches/989736/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20181026184447.13547-8-anirudh.venkataramanan@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20181026184447.13547-8-anirudh.venkataramanan@intel.com>", "list_archive_url": null, "date": "2018-10-26T18:44:39", "name": "[S9,07/15] ice: Cleanup duplicate control queue code", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "2e9071b794f6e43a7de34d0c1efd49e4b93839b7", "submitter": { "id": 73601, "url": "http://patchwork.ozlabs.org/api/people/73601/?format=api", "name": "Anirudh Venkataramanan", "email": "anirudh.venkataramanan@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20181026184447.13547-8-anirudh.venkataramanan@intel.com/mbox/", "series": [ { "id": 72801, "url": "http://patchwork.ozlabs.org/api/series/72801/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=72801", "date": "2018-10-26T18:44:32", "name": "Bug fixes for ice, set 2/2", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/72801/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/989736/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/989736/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.137; helo=fraxinus.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 42hXwm4h6kz9sDX\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 27 Oct 2018 05:44:56 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 0A3B18770B;\n\tFri, 26 Oct 2018 18:44:55 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id v9xis0rk7cyu; Fri, 26 Oct 2018 18:44:53 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id A21B78713F;\n\tFri, 26 Oct 2018 18:44:53 +0000 (UTC)", "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\tby ash.osuosl.org (Postfix) with ESMTP id 07EF61BF30E\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 26 Oct 2018 18:44:51 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 05DBC887DC\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 26 Oct 2018 18:44:51 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id vZqAXEVKBMdB for <intel-wired-lan@lists.osuosl.org>;\n\tFri, 26 Oct 2018 18:44:49 +0000 (UTC)", "from mga06.intel.com (mga06.intel.com [134.134.136.31])\n\tby hemlock.osuosl.org (Postfix) with ESMTPS id B6D6E8833A\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 26 Oct 2018 18:44:49 +0000 (UTC)", "from orsmga005.jf.intel.com ([10.7.209.41])\n\tby orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t26 Oct 2018 11:44:47 -0700", "from shasta.jf.intel.com ([10.166.241.11])\n\tby orsmga005.jf.intel.com with ESMTP; 26 Oct 2018 11:44:47 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.54,428,1534834800\"; d=\"scan'208\";a=\"269078856\"", "From": "Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Fri, 26 Oct 2018 11:44:39 -0700", "Message-Id": "<20181026184447.13547-8-anirudh.venkataramanan@intel.com>", "X-Mailer": "git-send-email 2.14.3", "In-Reply-To": "<20181026184447.13547-1-anirudh.venkataramanan@intel.com>", "References": "<20181026184447.13547-1-anirudh.venkataramanan@intel.com>", "Subject": "[Intel-wired-lan] [PATCH S9 07/15] ice: Cleanup duplicate control\n\tqueue code", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "From: Bruce Allan <bruce.w.allan@intel.com>\n\n1. Assigning the register offset and mask values contains duplicate code\n that can easily be replaced with a macro.\n\n2. Separate functions for freeing send queue and receive queue rings are\n not needed; replace with a single function that uses a pointer to the\n struct ice_ctl_q_ring structure as a parameter instead of a pointer to\n the struct ice_ctl_q_info structure.\n\n3. Initializing register settings for both send queue and receive queue\n contains duplicate code that can easily be replaced with a helper\n function.\n\n4. Separate functions for freeing send queue and receive queue buffers are\n not needed; duplicate code can easily be replaced with a macro.\n\nSigned-off-by: Bruce Allan <bruce.w.allan@intel.com>\nSigned-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>\n---\n[Anirudh Venkataramanan <anirudh.venkataramanan@intel.com> squashed mutiple commits]\n---\n drivers/net/ethernet/intel/ice/ice_controlq.c | 218 +++++++++-----------------\n 1 file changed, 76 insertions(+), 142 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/ice/ice_controlq.c b/drivers/net/ethernet/intel/ice/ice_controlq.c\nindex 84c967294eaf..b920403c6616 100644\n--- a/drivers/net/ethernet/intel/ice/ice_controlq.c\n+++ b/drivers/net/ethernet/intel/ice/ice_controlq.c\n@@ -3,6 +3,26 @@\n \n #include \"ice_common.h\"\n \n+#define ICE_CQ_INIT_REGS(qinfo, prefix)\t\t\t\t\\\n+do {\t\t\t\t\t\t\t\t\\\n+\t(qinfo)->sq.head = prefix##_ATQH;\t\t\t\\\n+\t(qinfo)->sq.tail = prefix##_ATQT;\t\t\t\\\n+\t(qinfo)->sq.len = prefix##_ATQLEN;\t\t\t\\\n+\t(qinfo)->sq.bah = prefix##_ATQBAH;\t\t\t\\\n+\t(qinfo)->sq.bal = prefix##_ATQBAL;\t\t\t\\\n+\t(qinfo)->sq.len_mask = prefix##_ATQLEN_ATQLEN_M;\t\\\n+\t(qinfo)->sq.len_ena_mask = prefix##_ATQLEN_ATQENABLE_M;\t\\\n+\t(qinfo)->sq.head_mask = prefix##_ATQH_ATQH_M;\t\t\\\n+\t(qinfo)->rq.head = prefix##_ARQH;\t\t\t\\\n+\t(qinfo)->rq.tail = prefix##_ARQT;\t\t\t\\\n+\t(qinfo)->rq.len = prefix##_ARQLEN;\t\t\t\\\n+\t(qinfo)->rq.bah = prefix##_ARQBAH;\t\t\t\\\n+\t(qinfo)->rq.bal = prefix##_ARQBAL;\t\t\t\\\n+\t(qinfo)->rq.len_mask = prefix##_ARQLEN_ARQLEN_M;\t\\\n+\t(qinfo)->rq.len_ena_mask = prefix##_ARQLEN_ARQENABLE_M;\t\\\n+\t(qinfo)->rq.head_mask = prefix##_ARQH_ARQH_M;\t\t\\\n+} while (0)\n+\n /**\n * ice_adminq_init_regs - Initialize AdminQ registers\n * @hw: pointer to the hardware structure\n@@ -13,23 +33,7 @@ static void ice_adminq_init_regs(struct ice_hw *hw)\n {\n \tstruct ice_ctl_q_info *cq = &hw->adminq;\n \n-\tcq->sq.head = PF_FW_ATQH;\n-\tcq->sq.tail = PF_FW_ATQT;\n-\tcq->sq.len = PF_FW_ATQLEN;\n-\tcq->sq.bah = PF_FW_ATQBAH;\n-\tcq->sq.bal = PF_FW_ATQBAL;\n-\tcq->sq.len_mask = PF_FW_ATQLEN_ATQLEN_M;\n-\tcq->sq.len_ena_mask = PF_FW_ATQLEN_ATQENABLE_M;\n-\tcq->sq.head_mask = PF_FW_ATQH_ATQH_M;\n-\n-\tcq->rq.head = PF_FW_ARQH;\n-\tcq->rq.tail = PF_FW_ARQT;\n-\tcq->rq.len = PF_FW_ARQLEN;\n-\tcq->rq.bah = PF_FW_ARQBAH;\n-\tcq->rq.bal = PF_FW_ARQBAL;\n-\tcq->rq.len_mask = PF_FW_ARQLEN_ARQLEN_M;\n-\tcq->rq.len_ena_mask = PF_FW_ARQLEN_ARQENABLE_M;\n-\tcq->rq.head_mask = PF_FW_ARQH_ARQH_M;\n+\tICE_CQ_INIT_REGS(cq, PF_FW);\n }\n \n /**\n@@ -42,24 +46,7 @@ static void ice_mailbox_init_regs(struct ice_hw *hw)\n {\n \tstruct ice_ctl_q_info *cq = &hw->mailboxq;\n \n-\t/* set head and tail registers in our local struct */\n-\tcq->sq.head = PF_MBX_ATQH;\n-\tcq->sq.tail = PF_MBX_ATQT;\n-\tcq->sq.len = PF_MBX_ATQLEN;\n-\tcq->sq.bah = PF_MBX_ATQBAH;\n-\tcq->sq.bal = PF_MBX_ATQBAL;\n-\tcq->sq.len_mask = PF_MBX_ATQLEN_ATQLEN_M;\n-\tcq->sq.len_ena_mask = PF_MBX_ATQLEN_ATQENABLE_M;\n-\tcq->sq.head_mask = PF_MBX_ATQH_ATQH_M;\n-\n-\tcq->rq.head = PF_MBX_ARQH;\n-\tcq->rq.tail = PF_MBX_ARQT;\n-\tcq->rq.len = PF_MBX_ARQLEN;\n-\tcq->rq.bah = PF_MBX_ARQBAH;\n-\tcq->rq.bal = PF_MBX_ARQBAL;\n-\tcq->rq.len_mask = PF_MBX_ARQLEN_ARQLEN_M;\n-\tcq->rq.len_ena_mask = PF_MBX_ARQLEN_ARQENABLE_M;\n-\tcq->rq.head_mask = PF_MBX_ARQH_ARQH_M;\n+\tICE_CQ_INIT_REGS(cq, PF_MBX);\n }\n \n /**\n@@ -131,37 +118,20 @@ ice_alloc_ctrlq_rq_ring(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n }\n \n /**\n- * ice_free_ctrlq_sq_ring - Free Control Transmit Queue (ATQ) rings\n- * @hw: pointer to the hardware structure\n- * @cq: pointer to the specific Control queue\n- *\n- * This assumes the posted send buffers have already been cleaned\n- * and de-allocated\n- */\n-static void ice_free_ctrlq_sq_ring(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n-{\n-\tdmam_free_coherent(ice_hw_to_dev(hw), cq->sq.desc_buf.size,\n-\t\t\t cq->sq.desc_buf.va, cq->sq.desc_buf.pa);\n-\tcq->sq.desc_buf.va = NULL;\n-\tcq->sq.desc_buf.pa = 0;\n-\tcq->sq.desc_buf.size = 0;\n-}\n-\n-/**\n- * ice_free_ctrlq_rq_ring - Free Control Receive Queue (ARQ) rings\n+ * ice_free_cq_ring - Free control queue ring\n * @hw: pointer to the hardware structure\n- * @cq: pointer to the specific Control queue\n+ * @ring: pointer to the specific control queue ring\n *\n- * This assumes the posted receive buffers have already been cleaned\n+ * This assumes the posted buffers have already been cleaned\n * and de-allocated\n */\n-static void ice_free_ctrlq_rq_ring(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n+static void ice_free_cq_ring(struct ice_hw *hw, struct ice_ctl_q_ring *ring)\n {\n-\tdmam_free_coherent(ice_hw_to_dev(hw), cq->rq.desc_buf.size,\n-\t\t\t cq->rq.desc_buf.va, cq->rq.desc_buf.pa);\n-\tcq->rq.desc_buf.va = NULL;\n-\tcq->rq.desc_buf.pa = 0;\n-\tcq->rq.desc_buf.size = 0;\n+\tdmam_free_coherent(ice_hw_to_dev(hw), ring->desc_buf.size,\n+\t\t\t ring->desc_buf.va, ring->desc_buf.pa);\n+\tring->desc_buf.va = NULL;\n+\tring->desc_buf.pa = 0;\n+\tring->desc_buf.size = 0;\n }\n \n /**\n@@ -280,54 +250,23 @@ ice_alloc_sq_bufs(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n \treturn ICE_ERR_NO_MEMORY;\n }\n \n-/**\n- * ice_free_rq_bufs - Free ARQ buffer info elements\n- * @hw: pointer to the hardware structure\n- * @cq: pointer to the specific Control queue\n- */\n-static void ice_free_rq_bufs(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n-{\n-\tint i;\n-\n-\t/* free descriptors */\n-\tfor (i = 0; i < cq->num_rq_entries; i++) {\n-\t\tdmam_free_coherent(ice_hw_to_dev(hw), cq->rq.r.rq_bi[i].size,\n-\t\t\t\t cq->rq.r.rq_bi[i].va, cq->rq.r.rq_bi[i].pa);\n-\t\tcq->rq.r.rq_bi[i].va = NULL;\n-\t\tcq->rq.r.rq_bi[i].pa = 0;\n-\t\tcq->rq.r.rq_bi[i].size = 0;\n-\t}\n-\n-\t/* free the dma header */\n-\tdevm_kfree(ice_hw_to_dev(hw), cq->rq.dma_head);\n-}\n-\n-/**\n- * ice_free_sq_bufs - Free ATQ buffer info elements\n- * @hw: pointer to the hardware structure\n- * @cq: pointer to the specific Control queue\n- */\n-static void ice_free_sq_bufs(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n+static enum ice_status\n+ice_cfg_cq_regs(struct ice_hw *hw, struct ice_ctl_q_ring *ring, u16 num_entries)\n {\n-\tint i;\n+\t/* Clear Head and Tail */\n+\twr32(hw, ring->head, 0);\n+\twr32(hw, ring->tail, 0);\n \n-\t/* only unmap if the address is non-NULL */\n-\tfor (i = 0; i < cq->num_sq_entries; i++)\n-\t\tif (cq->sq.r.sq_bi[i].pa) {\n-\t\t\tdmam_free_coherent(ice_hw_to_dev(hw),\n-\t\t\t\t\t cq->sq.r.sq_bi[i].size,\n-\t\t\t\t\t cq->sq.r.sq_bi[i].va,\n-\t\t\t\t\t cq->sq.r.sq_bi[i].pa);\n-\t\t\tcq->sq.r.sq_bi[i].va = NULL;\n-\t\t\tcq->sq.r.sq_bi[i].pa = 0;\n-\t\t\tcq->sq.r.sq_bi[i].size = 0;\n-\t\t}\n+\t/* set starting point */\n+\twr32(hw, ring->len, (num_entries | ring->len_ena_mask));\n+\twr32(hw, ring->bal, lower_32_bits(ring->desc_buf.pa));\n+\twr32(hw, ring->bah, upper_32_bits(ring->desc_buf.pa));\n \n-\t/* free the buffer info list */\n-\tdevm_kfree(ice_hw_to_dev(hw), cq->sq.cmd_buf);\n+\t/* Check one register to verify that config was applied */\n+\tif (rd32(hw, ring->bal) != lower_32_bits(ring->desc_buf.pa))\n+\t\treturn ICE_ERR_AQ_ERROR;\n \n-\t/* free the dma header */\n-\tdevm_kfree(ice_hw_to_dev(hw), cq->sq.dma_head);\n+\treturn 0;\n }\n \n /**\n@@ -340,23 +279,7 @@ static void ice_free_sq_bufs(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n static enum ice_status\n ice_cfg_sq_regs(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n {\n-\tu32 reg = 0;\n-\n-\t/* Clear Head and Tail */\n-\twr32(hw, cq->sq.head, 0);\n-\twr32(hw, cq->sq.tail, 0);\n-\n-\t/* set starting point */\n-\twr32(hw, cq->sq.len, (cq->num_sq_entries | cq->sq.len_ena_mask));\n-\twr32(hw, cq->sq.bal, lower_32_bits(cq->sq.desc_buf.pa));\n-\twr32(hw, cq->sq.bah, upper_32_bits(cq->sq.desc_buf.pa));\n-\n-\t/* Check one register to verify that config was applied */\n-\treg = rd32(hw, cq->sq.bal);\n-\tif (reg != lower_32_bits(cq->sq.desc_buf.pa))\n-\t\treturn ICE_ERR_AQ_ERROR;\n-\n-\treturn 0;\n+\treturn ice_cfg_cq_regs(hw, &cq->sq, cq->num_sq_entries);\n }\n \n /**\n@@ -369,25 +292,15 @@ ice_cfg_sq_regs(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n static enum ice_status\n ice_cfg_rq_regs(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n {\n-\tu32 reg = 0;\n-\n-\t/* Clear Head and Tail */\n-\twr32(hw, cq->rq.head, 0);\n-\twr32(hw, cq->rq.tail, 0);\n+\tenum ice_status status;\n \n-\t/* set starting point */\n-\twr32(hw, cq->rq.len, (cq->num_rq_entries | cq->rq.len_ena_mask));\n-\twr32(hw, cq->rq.bal, lower_32_bits(cq->rq.desc_buf.pa));\n-\twr32(hw, cq->rq.bah, upper_32_bits(cq->rq.desc_buf.pa));\n+\tstatus = ice_cfg_cq_regs(hw, &cq->rq, cq->num_rq_entries);\n+\tif (status)\n+\t\treturn status;\n \n \t/* Update tail in the HW to post pre-allocated buffers */\n \twr32(hw, cq->rq.tail, (u32)(cq->num_rq_entries - 1));\n \n-\t/* Check one register to verify that config was applied */\n-\treg = rd32(hw, cq->rq.bal);\n-\tif (reg != lower_32_bits(cq->rq.desc_buf.pa))\n-\t\treturn ICE_ERR_AQ_ERROR;\n-\n \treturn 0;\n }\n \n@@ -444,7 +357,7 @@ static enum ice_status ice_init_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n \tgoto init_ctrlq_exit;\n \n init_ctrlq_free_rings:\n-\tice_free_ctrlq_sq_ring(hw, cq);\n+\tice_free_cq_ring(hw, &cq->sq);\n \n init_ctrlq_exit:\n \treturn ret_code;\n@@ -503,12 +416,33 @@ static enum ice_status ice_init_rq(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n \tgoto init_ctrlq_exit;\n \n init_ctrlq_free_rings:\n-\tice_free_ctrlq_rq_ring(hw, cq);\n+\tice_free_cq_ring(hw, &cq->rq);\n \n init_ctrlq_exit:\n \treturn ret_code;\n }\n \n+#define ICE_FREE_CQ_BUFS(hw, qi, ring)\t\t\t\t\t\\\n+do {\t\t\t\t\t\t\t\t\t\\\n+\tint i;\t\t\t\t\t\t\t\t\\\n+\t/* free descriptors */\t\t\t\t\t\t\\\n+\tfor (i = 0; i < (qi)->num_##ring##_entries; i++)\t\t\\\n+\t\tif ((qi)->ring.r.ring##_bi[i].pa) {\t\t\t\\\n+\t\t\tdmam_free_coherent(ice_hw_to_dev(hw),\t\t\\\n+\t\t\t\t\t (qi)->ring.r.ring##_bi[i].size,\\\n+\t\t\t\t\t (qi)->ring.r.ring##_bi[i].va,\\\n+\t\t\t\t\t (qi)->ring.r.ring##_bi[i].pa);\\\n+\t\t\t(qi)->ring.r.ring##_bi[i].va = NULL;\t\t\\\n+\t\t\t(qi)->ring.r.ring##_bi[i].pa = 0;\t\t\\\n+\t\t\t(qi)->ring.r.ring##_bi[i].size = 0;\t\t\\\n+\t\t}\t\t\t\t\t\t\t\\\n+\t/* free the buffer info list */\t\t\t\t\t\\\n+\tif ((qi)->ring.cmd_buf)\t\t\t\t\t\t\\\n+\t\tdevm_kfree(ice_hw_to_dev(hw), (qi)->ring.cmd_buf);\t\\\n+\t/* free dma head */\t\t\t\t\t\t\\\n+\tdevm_kfree(ice_hw_to_dev(hw), (qi)->ring.dma_head);\t\t\\\n+} while (0)\n+\n /**\n * ice_shutdown_sq - shutdown the Control ATQ\n * @hw: pointer to the hardware structure\n@@ -538,8 +472,8 @@ ice_shutdown_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n \tcq->sq.count = 0;\t/* to indicate uninitialized queue */\n \n \t/* free ring buffers and the ring itself */\n-\tice_free_sq_bufs(hw, cq);\n-\tice_free_ctrlq_sq_ring(hw, cq);\n+\tICE_FREE_CQ_BUFS(hw, cq, sq);\n+\tice_free_cq_ring(hw, &cq->sq);\n \n shutdown_sq_out:\n \tmutex_unlock(&cq->sq_lock);\n@@ -606,8 +540,8 @@ ice_shutdown_rq(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n \tcq->rq.count = 0;\n \n \t/* free ring buffers and the ring itself */\n-\tice_free_rq_bufs(hw, cq);\n-\tice_free_ctrlq_rq_ring(hw, cq);\n+\tICE_FREE_CQ_BUFS(hw, cq, rq);\n+\tice_free_cq_ring(hw, &cq->rq);\n \n shutdown_rq_out:\n \tmutex_unlock(&cq->rq_lock);\n", "prefixes": [ "S9", "07/15" ] }