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GET /api/patches/982292/?format=api
{ "id": 982292, "url": "http://patchwork.ozlabs.org/api/patches/982292/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20181011071726.1848-1-sasha.neftin@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20181011071726.1848-1-sasha.neftin@intel.com>", "list_archive_url": null, "date": "2018-10-11T07:17:26", "name": "[v8,07/11] igc: Add HW initialization code", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "d579c31f3b9527a1951d037421d18ab8bb67d720", "submitter": { "id": 69860, "url": "http://patchwork.ozlabs.org/api/people/69860/?format=api", "name": "Sasha Neftin", "email": "sasha.neftin@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20181011071726.1848-1-sasha.neftin@intel.com/mbox/", "series": [ { "id": 70170, "url": "http://patchwork.ozlabs.org/api/series/70170/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=70170", "date": "2018-10-11T07:17:13", "name": "[v8,01/11] igc: Add skeletal frame for Intel(R) 2.5G Ethernet Controller support.", "version": 8, "mbox": "http://patchwork.ozlabs.org/series/70170/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/982292/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/982292/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.137; helo=fraxinus.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 42W2Nh4JcKz9s8F\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 11 Oct 2018 18:17:40 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id D766E85BDF;\n\tThu, 11 Oct 2018 07:17:38 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id knLDWeTr-v0p; Thu, 11 Oct 2018 07:17:36 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 71E6886992;\n\tThu, 11 Oct 2018 07:17:36 +0000 (UTC)", "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\tby ash.osuosl.org (Postfix) with ESMTP id 3054C1C1507\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 11 Oct 2018 07:17:35 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 2D7D7880C4\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 11 Oct 2018 07:17:35 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id s018HAz1oOj6 for <intel-wired-lan@lists.osuosl.org>;\n\tThu, 11 Oct 2018 07:17:31 +0000 (UTC)", "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n\tby hemlock.osuosl.org (Postfix) with ESMTPS id 70463880F7\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 11 Oct 2018 07:17:29 +0000 (UTC)", "from fmsmga006.fm.intel.com ([10.253.24.20])\n\tby fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t11 Oct 2018 00:17:29 -0700", "from ccdlinuxdev08.iil.intel.com ([143.185.161.150])\n\tby fmsmga006.fm.intel.com with ESMTP; 11 Oct 2018 00:17:26 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.54,367,1534834800\"; d=\"scan'208\";a=\"271434963\"", "From": "Sasha Neftin <sasha.neftin@intel.com>", "To": "sasha.neftin@intel.com,\n\tintel-wired-lan@lists.osuosl.org", "Date": "Thu, 11 Oct 2018 10:17:26 +0300", "Message-Id": "<20181011071726.1848-1-sasha.neftin@intel.com>", "X-Mailer": "git-send-email 2.11.0", "Subject": "[Intel-wired-lan] [PATCH v8 07/11] igc: Add HW initialization code", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "Add code for hw initialization and reset\nAdd code for semaphore handling\n\nSasha Neftin (v2):\nfix code indentation\nrefactor of igc_desc_unused method\n\nSasha Neftin (v3):\nclean code and remove unused methods\n\nSasha Neftin (v4):\naddress comments\nfix comments in e1000_i225.c and e1000_regs.h files\nfix xmas tree layout\nfix typos in e1000_mac.c file\nreplace e1000_ prefix with igc_ prefix\n\nSasha Neftin (v5):\nfix code indentation\n\nSasha Neftin (v6):\nfix code indentation\nremove unused defines\nminor cosmetic changes\n\nSasha Neftin (v7):\nfix kbuild test robot warning\nremove unneeded ret_val from igc_set_fc_watermarks method\n\nSasha Neftin (v8):\nfix whitespaces in comments\nremove unneeded blank lines\nremove unneeded forward declarations\nclean code\n\nSigned-off-by: Sasha Neftin <sasha.neftin@intel.com>\n---\n drivers/net/ethernet/intel/igc/Makefile | 2 +-\n drivers/net/ethernet/intel/igc/igc_base.c | 187 ++++++++++++++++\n drivers/net/ethernet/intel/igc/igc_base.h | 2 +\n drivers/net/ethernet/intel/igc/igc_defines.h | 36 +++\n drivers/net/ethernet/intel/igc/igc_hw.h | 85 ++++++++\n drivers/net/ethernet/intel/igc/igc_i225.c | 141 ++++++++++++\n drivers/net/ethernet/intel/igc/igc_mac.c | 315 +++++++++++++++++++++++++++\n drivers/net/ethernet/intel/igc/igc_mac.h | 11 +\n drivers/net/ethernet/intel/igc/igc_main.c | 21 ++\n drivers/net/ethernet/intel/igc/igc_regs.h | 20 ++\n 10 files changed, 819 insertions(+), 1 deletion(-)\n create mode 100644 drivers/net/ethernet/intel/igc/igc_i225.c", "diff": "diff --git a/drivers/net/ethernet/intel/igc/Makefile b/drivers/net/ethernet/intel/igc/Makefile\nindex c32c45300692..8b8022ea590a 100644\n--- a/drivers/net/ethernet/intel/igc/Makefile\n+++ b/drivers/net/ethernet/intel/igc/Makefile\n@@ -7,4 +7,4 @@\n \n obj-$(CONFIG_IGC) += igc.o\n \n-igc-objs := igc_main.o igc_mac.o igc_base.o\n+igc-objs := igc_main.o igc_mac.o igc_i225.o igc_base.o\ndiff --git a/drivers/net/ethernet/intel/igc/igc_base.c b/drivers/net/ethernet/intel/igc/igc_base.c\nindex 3425b7466017..4efb47497e6b 100644\n--- a/drivers/net/ethernet/intel/igc/igc_base.c\n+++ b/drivers/net/ethernet/intel/igc/igc_base.c\n@@ -5,6 +5,184 @@\n \n #include \"igc_hw.h\"\n #include \"igc_i225.h\"\n+#include \"igc_mac.h\"\n+#include \"igc_base.h\"\n+#include \"igc.h\"\n+\n+/**\n+ * igc_set_pcie_completion_timeout - set pci-e completion timeout\n+ * @hw: pointer to the HW structure\n+ */\n+static s32 igc_set_pcie_completion_timeout(struct igc_hw *hw)\n+{\n+\tu32 gcr = rd32(IGC_GCR);\n+\tu16 pcie_devctl2;\n+\ts32 ret_val = 0;\n+\n+\t/* only take action if timeout value is defaulted to 0 */\n+\tif (gcr & IGC_GCR_CMPL_TMOUT_MASK)\n+\t\tgoto out;\n+\n+\t/* if capabilities version is type 1 we can write the\n+\t * timeout of 10ms to 200ms through the GCR register\n+\t */\n+\tif (!(gcr & IGC_GCR_CAP_VER2)) {\n+\t\tgcr |= IGC_GCR_CMPL_TMOUT_10ms;\n+\t\tgoto out;\n+\t}\n+\n+\t/* for version 2 capabilities we need to write the config space\n+\t * directly in order to set the completion timeout value for\n+\t * 16ms to 55ms\n+\t */\n+\tret_val = igc_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,\n+\t\t\t\t\t&pcie_devctl2);\n+\tif (ret_val)\n+\t\tgoto out;\n+\n+\tpcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;\n+\n+\tret_val = igc_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,\n+\t\t\t\t\t &pcie_devctl2);\n+out:\n+\t/* disable completion timeout resend */\n+\tgcr &= ~IGC_GCR_CMPL_TMOUT_RESEND;\n+\n+\twr32(IGC_GCR, gcr);\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ * igc_reset_hw_base - Reset hardware\n+ * @hw: pointer to the HW structure\n+ *\n+ * This resets the hardware into a known state. This is a\n+ * function pointer entry point called by the api module.\n+ */\n+static s32 igc_reset_hw_base(struct igc_hw *hw)\n+{\n+\ts32 ret_val;\n+\tu32 ctrl;\n+\n+\t/* Prevent the PCI-E bus from sticking if there is no TLP connection\n+\t * on the last TLP read/write transaction when MAC is reset.\n+\t */\n+\tret_val = igc_disable_pcie_master(hw);\n+\tif (ret_val)\n+\t\thw_dbg(\"PCI-E Master disable polling has failed.\\n\");\n+\n+\t/* set the completion timeout for interface */\n+\tret_val = igc_set_pcie_completion_timeout(hw);\n+\tif (ret_val)\n+\t\thw_dbg(\"PCI-E Set completion timeout has failed.\\n\");\n+\n+\thw_dbg(\"Masking off all interrupts\\n\");\n+\twr32(IGC_IMC, 0xffffffff);\n+\n+\twr32(IGC_RCTL, 0);\n+\twr32(IGC_TCTL, IGC_TCTL_PSP);\n+\twrfl();\n+\n+\tusleep_range(10000, 20000);\n+\n+\tctrl = rd32(IGC_CTRL);\n+\n+\thw_dbg(\"Issuing a global reset to MAC\\n\");\n+\twr32(IGC_CTRL, ctrl | IGC_CTRL_RST);\n+\n+\tret_val = igc_get_auto_rd_done(hw);\n+\tif (ret_val) {\n+\t\t/* When auto config read does not complete, do not\n+\t\t * return with an error. This can happen in situations\n+\t\t * where there is no eeprom and prevents getting link.\n+\t\t */\n+\t\thw_dbg(\"Auto Read Done did not complete\\n\");\n+\t}\n+\n+\t/* Clear any pending interrupt events. */\n+\twr32(IGC_IMC, 0xffffffff);\n+\trd32(IGC_ICR);\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ * igc_init_mac_params_base - Init MAC func ptrs.\n+ * @hw: pointer to the HW structure\n+ */\n+static s32 igc_init_mac_params_base(struct igc_hw *hw)\n+{\n+\tstruct igc_mac_info *mac = &hw->mac;\n+\n+\t/* Set mta register count */\n+\tmac->mta_reg_count = 128;\n+\tmac->rar_entry_count = IGC_RAR_ENTRIES;\n+\n+\t/* reset */\n+\tmac->ops.reset_hw = igc_reset_hw_base;\n+\n+\tmac->ops.acquire_swfw_sync = igc_acquire_swfw_sync_i225;\n+\tmac->ops.release_swfw_sync = igc_release_swfw_sync_i225;\n+\n+\treturn 0;\n+}\n+\n+static s32 igc_get_invariants_base(struct igc_hw *hw)\n+{\n+\tu32 link_mode = 0;\n+\tu32 ctrl_ext = 0;\n+\ts32 ret_val = 0;\n+\n+\tctrl_ext = rd32(IGC_CTRL_EXT);\n+\tlink_mode = ctrl_ext & IGC_CTRL_EXT_LINK_MODE_MASK;\n+\n+\t/* mac initialization and operations */\n+\tret_val = igc_init_mac_params_base(hw);\n+\tif (ret_val)\n+\t\tgoto out;\n+\n+out:\n+\treturn ret_val;\n+}\n+\n+/**\n+ * igc_init_hw_base - Initialize hardware\n+ * @hw: pointer to the HW structure\n+ *\n+ * This inits the hardware readying it for operation.\n+ */\n+static s32 igc_init_hw_base(struct igc_hw *hw)\n+{\n+\tstruct igc_mac_info *mac = &hw->mac;\n+\tu16 i, rar_count = mac->rar_entry_count;\n+\ts32 ret_val = 0;\n+\n+\t/* Setup the receive address */\n+\tigc_init_rx_addrs(hw, rar_count);\n+\n+\t/* Zero out the Multicast HASH table */\n+\thw_dbg(\"Zeroing the MTA\\n\");\n+\tfor (i = 0; i < mac->mta_reg_count; i++)\n+\t\tarray_wr32(IGC_MTA, i, 0);\n+\n+\t/* Zero out the Unicast HASH table */\n+\thw_dbg(\"Zeroing the UTA\\n\");\n+\tfor (i = 0; i < mac->uta_reg_count; i++)\n+\t\tarray_wr32(IGC_UTA, i, 0);\n+\n+\t/* Setup link and flow control */\n+\tret_val = igc_setup_link(hw);\n+\n+\t/* Clear all of the statistics registers (clear on read). It is\n+\t * important that we do this after we have tried to establish link\n+\t * because the symbol error count will increment wildly if there\n+\t * is no link.\n+\t */\n+\tigc_clear_hw_cntrs_base(hw);\n+\n+\treturn ret_val;\n+}\n \n /**\n * igc_rx_fifo_flush_base - Clean rx fifo after Rx enable\n@@ -81,3 +259,12 @@ void igc_rx_fifo_flush_base(struct igc_hw *hw)\n \trd32(IGC_RNBC);\n \trd32(IGC_MPC);\n }\n+\n+static struct igc_mac_operations igc_mac_ops_base = {\n+\t.init_hw\t\t= igc_init_hw_base,\n+};\n+\n+const struct igc_info igc_base_info = {\n+\t.get_invariants\t\t= igc_get_invariants_base,\n+\t.mac_ops\t\t= &igc_mac_ops_base,\n+};\ndiff --git a/drivers/net/ethernet/intel/igc/igc_base.h b/drivers/net/ethernet/intel/igc/igc_base.h\nindex 3078a18f70a9..802a0cbd3123 100644\n--- a/drivers/net/ethernet/intel/igc/igc_base.h\n+++ b/drivers/net/ethernet/intel/igc/igc_base.h\n@@ -33,6 +33,8 @@ union igc_adv_tx_desc {\n #define IGC_ADVTXD_DCMD_TSE\t0x80000000 /* TCP Seg enable */\n #define IGC_ADVTXD_PAYLEN_SHIFT\t14 /* Adv desc PAYLEN shift */\n \n+#define IGC_RAR_ENTRIES\t\t16\n+\n struct igc_adv_data_desc {\n \t__le64 buffer_addr; /* Address of the descriptor's data buffer */\n \tunion {\ndiff --git a/drivers/net/ethernet/intel/igc/igc_defines.h b/drivers/net/ethernet/intel/igc/igc_defines.h\nindex c8a321358cf6..3d6c2cee0ad3 100644\n--- a/drivers/net/ethernet/intel/igc/igc_defines.h\n+++ b/drivers/net/ethernet/intel/igc/igc_defines.h\n@@ -10,6 +10,22 @@\n #define PCIE_DEVICE_CONTROL2\t\t0x28\n #define PCIE_DEVICE_CONTROL2_16ms\t0x0005\n \n+/* Physical Func Reset Done Indication */\n+#define IGC_CTRL_EXT_LINK_MODE_MASK\t0x00C00000\n+\n+/* Number of 100 microseconds we wait for PCI Express master disable */\n+#define MASTER_DISABLE_TIMEOUT\t\t800\n+/*Blocks new Master requests */\n+#define IGC_CTRL_GIO_MASTER_DISABLE\t0x00000004\n+/* Status of Master requests. */\n+#define IGC_STATUS_GIO_MASTER_ENABLE\t0x00080000\n+\n+/* PCI Express Control */\n+#define IGC_GCR_CMPL_TMOUT_MASK\t\t0x0000F000\n+#define IGC_GCR_CMPL_TMOUT_10ms\t\t0x00001000\n+#define IGC_GCR_CMPL_TMOUT_RESEND\t0x00010000\n+#define IGC_GCR_CAP_VER2\t\t0x00040000\n+\n /* Receive Address\n * Number of high/low register pairs in the RAR. The RAR (Receive Address\n * Registers) holds the directed and multicast addresses that we monitor.\n@@ -28,10 +44,23 @@\n #define IGC_ERR_PARAM\t\t\t4\n #define IGC_ERR_MAC_INIT\t\t5\n #define IGC_ERR_RESET\t\t\t9\n+#define IGC_ERR_MASTER_REQUESTS_PENDING\t10\n+#define IGC_ERR_SWFW_SYNC\t\t13\n+\n+/* Device Control */\n+#define IGC_CTRL_RST\t\t0x04000000 /* Global reset */\n \n /* PBA constants */\n #define IGC_PBA_34K\t\t0x0022\n \n+/* SW Semaphore Register */\n+#define IGC_SWSM_SMBI\t\t0x00000001 /* Driver Semaphore bit */\n+#define IGC_SWSM_SWESMBI\t0x00000002 /* FW Semaphore bit */\n+\n+/* Number of milliseconds for NVM auto read done after MAC reset. */\n+#define AUTO_READ_DONE_TIMEOUT\t\t10\n+#define IGC_EECD_AUTO_RD\t\t0x00000200 /* NVM Auto Read done */\n+\n /* Device Status */\n #define IGC_STATUS_FD\t\t0x00000001 /* Full duplex.0=half,1=full */\n #define IGC_STATUS_LU\t\t0x00000002 /* Link up.0=no,1=link */\n@@ -118,6 +147,13 @@\n #define IGC_CT_SHIFT\t\t\t4\n #define IGC_COLLISION_THRESHOLD\t\t15\n \n+/* Flow Control Constants */\n+#define FLOW_CONTROL_ADDRESS_LOW\t0x00C28001\n+#define FLOW_CONTROL_ADDRESS_HIGH\t0x00000100\n+#define FLOW_CONTROL_TYPE\t\t0x8808\n+/* Enable XON frame transmission */\n+#define IGC_FCRTL_XONE\t\t\t0x80000000\n+\n /* Management Control */\n #define IGC_MANC_RCV_TCO_EN\t0x00020000 /* Receive TCO Packets Enabled */\n \ndiff --git a/drivers/net/ethernet/intel/igc/igc_hw.h b/drivers/net/ethernet/intel/igc/igc_hw.h\nindex a032495a0479..e31d85f1ee12 100644\n--- a/drivers/net/ethernet/intel/igc/igc_hw.h\n+++ b/drivers/net/ethernet/intel/igc/igc_hw.h\n@@ -6,6 +6,8 @@\n \n #include <linux/types.h>\n #include <linux/if_ether.h>\n+#include <linux/netdevice.h>\n+\n #include \"igc_regs.h\"\n #include \"igc_defines.h\"\n #include \"igc_mac.h\"\n@@ -17,6 +19,16 @@\n \n /* Function pointers for the MAC. */\n struct igc_mac_operations {\n+\ts32 (*check_for_link)(struct igc_hw *hw);\n+\ts32 (*reset_hw)(struct igc_hw *hw);\n+\ts32 (*init_hw)(struct igc_hw *hw);\n+\ts32 (*setup_physical_interface)(struct igc_hw *hw);\n+\tvoid (*rar_set)(struct igc_hw *hw, u8 *address, u32 index);\n+\ts32 (*read_mac_addr)(struct igc_hw *hw);\n+\ts32 (*get_speed_and_duplex)(struct igc_hw *hw, u16 *speed,\n+\t\t\t\t u16 *duplex);\n+\ts32 (*acquire_swfw_sync)(struct igc_hw *hw, u16 mask);\n+\tvoid (*release_swfw_sync)(struct igc_hw *hw, u16 mask);\n };\n \n enum igc_mac_type {\n@@ -31,6 +43,19 @@ enum igc_phy_type {\n \tigc_phy_i225,\n };\n \n+enum igc_nvm_type {\n+\tigc_nvm_unknown = 0,\n+\tigc_nvm_flash_hw,\n+\tigc_nvm_invm,\n+};\n+\n+struct igc_info {\n+\ts32 (*get_invariants)(struct igc_hw *hw);\n+\tstruct igc_mac_operations *mac_ops;\n+\tconst struct igc_phy_operations *phy_ops;\n+\tstruct igc_nvm_operations *nvm_ops;\n+};\n+\n struct igc_mac_info {\n \tstruct igc_mac_operations ops;\n \n@@ -63,11 +88,61 @@ struct igc_mac_info {\n \tbool get_link_status;\n };\n \n+struct igc_nvm_operations {\n+\ts32 (*acquire)(struct igc_hw *hw);\n+\ts32 (*read)(struct igc_hw *hw, u16 offset, u16 i, u16 *data);\n+\tvoid (*release)(struct igc_hw *hw);\n+\ts32 (*write)(struct igc_hw *hw, u16 offset, u16 i, u16 *data);\n+\ts32 (*update)(struct igc_hw *hw);\n+\ts32 (*validate)(struct igc_hw *hw);\n+\ts32 (*valid_led_default)(struct igc_hw *hw, u16 *data);\n+};\n+\n+struct igc_nvm_info {\n+\tstruct igc_nvm_operations ops;\n+\tenum igc_nvm_type type;\n+\n+\tu32 flash_bank_size;\n+\tu32 flash_base_addr;\n+\n+\tu16 word_size;\n+\tu16 delay_usec;\n+\tu16 address_bits;\n+\tu16 opcode_bits;\n+\tu16 page_size;\n+};\n+\n struct igc_bus_info {\n \tu16 func;\n \tu16 pci_cmd_word;\n };\n \n+enum igc_fc_mode {\n+\tigc_fc_none = 0,\n+\tigc_fc_rx_pause,\n+\tigc_fc_tx_pause,\n+\tigc_fc_full,\n+\tigc_fc_default = 0xFF\n+};\n+\n+struct igc_fc_info {\n+\tu32 high_water; /* Flow control high-water mark */\n+\tu32 low_water; /* Flow control low-water mark */\n+\tu16 pause_time; /* Flow control pause timer */\n+\tbool send_xon; /* Flow control send XON */\n+\tbool strict_ieee; /* Strict IEEE mode */\n+\tenum igc_fc_mode current_mode; /* Type of flow control */\n+\tenum igc_fc_mode requested_mode;\n+};\n+\n+struct igc_dev_spec_base {\n+\tbool global_device_reset;\n+\tbool eee_disable;\n+\tbool clear_semaphore_once;\n+\tbool module_plugged;\n+\tu8 media_port;\n+};\n+\n struct igc_hw {\n \tvoid *back;\n \n@@ -75,9 +150,15 @@ struct igc_hw {\n \tunsigned long io_base;\n \n \tstruct igc_mac_info mac;\n+\tstruct igc_fc_info fc;\n+\tstruct igc_nvm_info nvm;\n \n \tstruct igc_bus_info bus;\n \n+\tunion {\n+\t\tstruct igc_dev_spec_base\t_base;\n+\t} dev_spec;\n+\n \tu16 device_id;\n \tu16 subsystem_vendor_id;\n \tu16 subsystem_device_id;\n@@ -170,6 +251,10 @@ struct igc_hw_stats {\n \tu64 b2ogprc;\n };\n \n+struct net_device *igc_get_hw_dev(struct igc_hw *hw);\n+#define hw_dbg(format, arg...) \\\n+\tnetdev_dbg(igc_get_hw_dev(hw), format, ##arg)\n+\n s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);\n s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);\n void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);\ndiff --git a/drivers/net/ethernet/intel/igc/igc_i225.c b/drivers/net/ethernet/intel/igc/igc_i225.c\nnew file mode 100644\nindex 000000000000..fb1487727d79\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/igc/igc_i225.c\n@@ -0,0 +1,141 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/* Copyright (c) 2018 Intel Corporation */\n+\n+#include <linux/delay.h>\n+\n+#include \"igc_hw.h\"\n+\n+/**\n+ * igc_get_hw_semaphore_i225 - Acquire hardware semaphore\n+ * @hw: pointer to the HW structure\n+ *\n+ * Acquire the HW semaphore to access the PHY or NVM\n+ */\n+static s32 igc_get_hw_semaphore_i225(struct igc_hw *hw)\n+{\n+\ts32 timeout = hw->nvm.word_size + 1;\n+\ts32 i = 0;\n+\tu32 swsm;\n+\n+\t/* Get the SW semaphore */\n+\twhile (i < timeout) {\n+\t\tswsm = rd32(IGC_SWSM);\n+\t\tif (!(swsm & IGC_SWSM_SMBI))\n+\t\t\tbreak;\n+\n+\t\tusleep_range(500, 600);\n+\t\ti++;\n+\t}\n+\n+\tif (i == timeout) {\n+\t\t/* In rare circumstances, the SW semaphore may already be held\n+\t\t * unintentionally. Clear the semaphore once before giving up.\n+\t\t */\n+\t\tif (hw->dev_spec._base.clear_semaphore_once) {\n+\t\t\thw->dev_spec._base.clear_semaphore_once = false;\n+\t\t\tigc_put_hw_semaphore(hw);\n+\t\t\tfor (i = 0; i < timeout; i++) {\n+\t\t\t\tswsm = rd32(IGC_SWSM);\n+\t\t\t\tif (!(swsm & IGC_SWSM_SMBI))\n+\t\t\t\t\tbreak;\n+\n+\t\t\t\tusleep_range(500, 600);\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* If we do not have the semaphore here, we have to give up. */\n+\t\tif (i == timeout) {\n+\t\t\thw_dbg(\"Driver can't access device - SMBI bit is set.\\n\");\n+\t\t\treturn -IGC_ERR_NVM;\n+\t\t}\n+\t}\n+\n+\t/* Get the FW semaphore. */\n+\tfor (i = 0; i < timeout; i++) {\n+\t\tswsm = rd32(IGC_SWSM);\n+\t\twr32(IGC_SWSM, swsm | IGC_SWSM_SWESMBI);\n+\n+\t\t/* Semaphore acquired if bit latched */\n+\t\tif (rd32(IGC_SWSM) & IGC_SWSM_SWESMBI)\n+\t\t\tbreak;\n+\n+\t\tusleep_range(500, 600);\n+\t}\n+\n+\tif (i == timeout) {\n+\t\t/* Release semaphores */\n+\t\tigc_put_hw_semaphore(hw);\n+\t\thw_dbg(\"Driver can't access the NVM\\n\");\n+\t\treturn -IGC_ERR_NVM;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * igc_acquire_swfw_sync_i225 - Acquire SW/FW semaphore\n+ * @hw: pointer to the HW structure\n+ * @mask: specifies which semaphore to acquire\n+ *\n+ * Acquire the SW/FW semaphore to access the PHY or NVM. The mask\n+ * will also specify which port we're acquiring the lock for.\n+ */\n+s32 igc_acquire_swfw_sync_i225(struct igc_hw *hw, u16 mask)\n+{\n+\ts32 i = 0, timeout = 200;\n+\tu32 fwmask = mask << 16;\n+\tu32 swmask = mask;\n+\ts32 ret_val = 0;\n+\tu32 swfw_sync;\n+\n+\twhile (i < timeout) {\n+\t\tif (igc_get_hw_semaphore_i225(hw)) {\n+\t\t\tret_val = -IGC_ERR_SWFW_SYNC;\n+\t\t\tgoto out;\n+\t\t}\n+\n+\t\tswfw_sync = rd32(IGC_SW_FW_SYNC);\n+\t\tif (!(swfw_sync & (fwmask | swmask)))\n+\t\t\tbreak;\n+\n+\t\t/* Firmware currently using resource (fwmask) */\n+\t\tigc_put_hw_semaphore(hw);\n+\t\tmdelay(5);\n+\t\ti++;\n+\t}\n+\n+\tif (i == timeout) {\n+\t\thw_dbg(\"Driver can't access resource, SW_FW_SYNC timeout.\\n\");\n+\t\tret_val = -IGC_ERR_SWFW_SYNC;\n+\t\tgoto out;\n+\t}\n+\n+\tswfw_sync |= swmask;\n+\twr32(IGC_SW_FW_SYNC, swfw_sync);\n+\n+\tigc_put_hw_semaphore(hw);\n+out:\n+\treturn ret_val;\n+}\n+\n+/**\n+ * igc_release_swfw_sync_i225 - Release SW/FW semaphore\n+ * @hw: pointer to the HW structure\n+ * @mask: specifies which semaphore to acquire\n+ *\n+ * Release the SW/FW semaphore used to access the PHY or NVM. The mask\n+ * will also specify which port we're releasing the lock for.\n+ */\n+void igc_release_swfw_sync_i225(struct igc_hw *hw, u16 mask)\n+{\n+\tu32 swfw_sync;\n+\n+\twhile (igc_get_hw_semaphore_i225(hw))\n+\t\t; /* Empty */\n+\n+\tswfw_sync = rd32(IGC_SW_FW_SYNC);\n+\tswfw_sync &= ~mask;\n+\twr32(IGC_SW_FW_SYNC, swfw_sync);\n+\n+\tigc_put_hw_semaphore(hw);\n+}\ndiff --git a/drivers/net/ethernet/intel/igc/igc_mac.c b/drivers/net/ethernet/intel/igc/igc_mac.c\nindex 9976943df51c..90a98ee14550 100644\n--- a/drivers/net/ethernet/intel/igc/igc_mac.c\n+++ b/drivers/net/ethernet/intel/igc/igc_mac.c\n@@ -2,4 +2,319 @@\n /* Copyright (c) 2018 Intel Corporation */\n \n #include <linux/pci.h>\n+#include <linux/delay.h>\n+\n+#include \"igc_mac.h\"\n #include \"igc_hw.h\"\n+\n+/* forward declaration */\n+static s32 igc_set_default_fc(struct igc_hw *hw);\n+static s32 igc_set_fc_watermarks(struct igc_hw *hw);\n+\n+/**\n+ * igc_disable_pcie_master - Disables PCI-express master access\n+ * @hw: pointer to the HW structure\n+ *\n+ * Returns 0 (0) if successful, else returns -10\n+ * (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused\n+ * the master requests to be disabled.\n+ *\n+ * Disables PCI-Express master access and verifies there are no pending\n+ * requests.\n+ */\n+s32 igc_disable_pcie_master(struct igc_hw *hw)\n+{\n+\ts32 timeout = MASTER_DISABLE_TIMEOUT;\n+\ts32 ret_val = 0;\n+\tu32 ctrl;\n+\n+\tctrl = rd32(IGC_CTRL);\n+\tctrl |= IGC_CTRL_GIO_MASTER_DISABLE;\n+\twr32(IGC_CTRL, ctrl);\n+\n+\twhile (timeout) {\n+\t\tif (!(rd32(IGC_STATUS) &\n+\t\t IGC_STATUS_GIO_MASTER_ENABLE))\n+\t\t\tbreak;\n+\t\tusleep_range(2000, 3000);\n+\t\ttimeout--;\n+\t}\n+\n+\tif (!timeout) {\n+\t\thw_dbg(\"Master requests are pending.\\n\");\n+\t\tret_val = -IGC_ERR_MASTER_REQUESTS_PENDING;\n+\t\tgoto out;\n+\t}\n+\n+out:\n+\treturn ret_val;\n+}\n+\n+/**\n+ * igc_init_rx_addrs - Initialize receive addresses\n+ * @hw: pointer to the HW structure\n+ * @rar_count: receive address registers\n+ *\n+ * Setup the receive address registers by setting the base receive address\n+ * register to the devices MAC address and clearing all the other receive\n+ * address registers to 0.\n+ */\n+void igc_init_rx_addrs(struct igc_hw *hw, u16 rar_count)\n+{\n+\tu8 mac_addr[ETH_ALEN] = {0};\n+\tu32 i;\n+\n+\t/* Setup the receive address */\n+\thw_dbg(\"Programming MAC Address into RAR[0]\\n\");\n+\n+\thw->mac.ops.rar_set(hw, hw->mac.addr, 0);\n+\n+\t/* Zero out the other (rar_entry_count - 1) receive addresses */\n+\thw_dbg(\"Clearing RAR[1-%u]\\n\", rar_count - 1);\n+\tfor (i = 1; i < rar_count; i++)\n+\t\thw->mac.ops.rar_set(hw, mac_addr, i);\n+}\n+\n+/**\n+ * igc_setup_link - Setup flow control and link settings\n+ * @hw: pointer to the HW structure\n+ *\n+ * Determines which flow control settings to use, then configures flow\n+ * control. Calls the appropriate media-specific link configuration\n+ * function. Assuming the adapter has a valid link partner, a valid link\n+ * should be established. Assumes the hardware has previously been reset\n+ * and the transmitter and receiver are not enabled.\n+ */\n+s32 igc_setup_link(struct igc_hw *hw)\n+{\n+\ts32 ret_val = 0;\n+\n+\t/* In the case of the phy reset being blocked, we already have a link.\n+\t * We do not need to set it up again.\n+\t */\n+\n+\t/* If requested flow control is set to default, set flow control\n+\t * based on the EEPROM flow control settings.\n+\t */\n+\tif (hw->fc.requested_mode == igc_fc_default) {\n+\t\tret_val = igc_set_default_fc(hw);\n+\t\tif (ret_val)\n+\t\t\tgoto out;\n+\t}\n+\n+\t/* We want to save off the original Flow Control configuration just\n+\t * in case we get disconnected and then reconnected into a different\n+\t * hub or switch with different Flow Control capabilities.\n+\t */\n+\thw->fc.current_mode = hw->fc.requested_mode;\n+\n+\thw_dbg(\"After fix-ups FlowControl is now = %x\\n\", hw->fc.current_mode);\n+\n+\t/* Call the necessary media_type subroutine to configure the link. */\n+\tret_val = hw->mac.ops.setup_physical_interface(hw);\n+\tif (ret_val)\n+\t\tgoto out;\n+\n+\t/* Initialize the flow control address, type, and PAUSE timer\n+\t * registers to their default values. This is done even if flow\n+\t * control is disabled, because it does not hurt anything to\n+\t * initialize these registers.\n+\t */\n+\thw_dbg(\"Initializing the Flow Control address, type and timer regs\\n\");\n+\twr32(IGC_FCT, FLOW_CONTROL_TYPE);\n+\twr32(IGC_FCAH, FLOW_CONTROL_ADDRESS_HIGH);\n+\twr32(IGC_FCAL, FLOW_CONTROL_ADDRESS_LOW);\n+\n+\twr32(IGC_FCTTV, hw->fc.pause_time);\n+\n+\tret_val = igc_set_fc_watermarks(hw);\n+\n+out:\n+\treturn ret_val;\n+}\n+\n+/**\n+ * igc_set_default_fc - Set flow control default values\n+ * @hw: pointer to the HW structure\n+ *\n+ * Read the EEPROM for the default values for flow control and store the\n+ * values.\n+ */\n+static s32 igc_set_default_fc(struct igc_hw *hw)\n+{\n+\treturn 0;\n+}\n+\n+/**\n+ * igc_set_fc_watermarks - Set flow control high/low watermarks\n+ * @hw: pointer to the HW structure\n+ *\n+ * Sets the flow control high/low threshold (watermark) registers. If\n+ * flow control XON frame transmission is enabled, then set XON frame\n+ * transmission as well.\n+ */\n+static s32 igc_set_fc_watermarks(struct igc_hw *hw)\n+{\n+\tu32 fcrtl = 0, fcrth = 0;\n+\n+\t/* Set the flow control receive threshold registers. Normally,\n+\t * these registers will be set to a default threshold that may be\n+\t * adjusted later by the driver's runtime code. However, if the\n+\t * ability to transmit pause frames is not enabled, then these\n+\t * registers will be set to 0.\n+\t */\n+\tif (hw->fc.current_mode & igc_fc_tx_pause) {\n+\t\t/* We need to set up the Receive Threshold high and low water\n+\t\t * marks as well as (optionally) enabling the transmission of\n+\t\t * XON frames.\n+\t\t */\n+\t\tfcrtl = hw->fc.low_water;\n+\t\tif (hw->fc.send_xon)\n+\t\t\tfcrtl |= IGC_FCRTL_XONE;\n+\n+\t\tfcrth = hw->fc.high_water;\n+\t}\n+\twr32(IGC_FCRTL, fcrtl);\n+\twr32(IGC_FCRTH, fcrth);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * igc_clear_hw_cntrs_base - Clear base hardware counters\n+ * @hw: pointer to the HW structure\n+ *\n+ * Clears the base hardware counters by reading the counter registers.\n+ */\n+void igc_clear_hw_cntrs_base(struct igc_hw *hw)\n+{\n+\trd32(IGC_CRCERRS);\n+\trd32(IGC_SYMERRS);\n+\trd32(IGC_MPC);\n+\trd32(IGC_SCC);\n+\trd32(IGC_ECOL);\n+\trd32(IGC_MCC);\n+\trd32(IGC_LATECOL);\n+\trd32(IGC_COLC);\n+\trd32(IGC_DC);\n+\trd32(IGC_SEC);\n+\trd32(IGC_RLEC);\n+\trd32(IGC_XONRXC);\n+\trd32(IGC_XONTXC);\n+\trd32(IGC_XOFFRXC);\n+\trd32(IGC_XOFFTXC);\n+\trd32(IGC_FCRUC);\n+\trd32(IGC_GPRC);\n+\trd32(IGC_BPRC);\n+\trd32(IGC_MPRC);\n+\trd32(IGC_GPTC);\n+\trd32(IGC_GORCL);\n+\trd32(IGC_GORCH);\n+\trd32(IGC_GOTCL);\n+\trd32(IGC_GOTCH);\n+\trd32(IGC_RNBC);\n+\trd32(IGC_RUC);\n+\trd32(IGC_RFC);\n+\trd32(IGC_ROC);\n+\trd32(IGC_RJC);\n+\trd32(IGC_TORL);\n+\trd32(IGC_TORH);\n+\trd32(IGC_TOTL);\n+\trd32(IGC_TOTH);\n+\trd32(IGC_TPR);\n+\trd32(IGC_TPT);\n+\trd32(IGC_MPTC);\n+\trd32(IGC_BPTC);\n+\n+\trd32(IGC_PRC64);\n+\trd32(IGC_PRC127);\n+\trd32(IGC_PRC255);\n+\trd32(IGC_PRC511);\n+\trd32(IGC_PRC1023);\n+\trd32(IGC_PRC1522);\n+\trd32(IGC_PTC64);\n+\trd32(IGC_PTC127);\n+\trd32(IGC_PTC255);\n+\trd32(IGC_PTC511);\n+\trd32(IGC_PTC1023);\n+\trd32(IGC_PTC1522);\n+\n+\trd32(IGC_ALGNERRC);\n+\trd32(IGC_RXERRC);\n+\trd32(IGC_TNCRS);\n+\trd32(IGC_CEXTERR);\n+\trd32(IGC_TSCTC);\n+\trd32(IGC_TSCTFC);\n+\n+\trd32(IGC_MGTPRC);\n+\trd32(IGC_MGTPDC);\n+\trd32(IGC_MGTPTC);\n+\n+\trd32(IGC_IAC);\n+\trd32(IGC_ICRXOC);\n+\n+\trd32(IGC_ICRXPTC);\n+\trd32(IGC_ICRXATC);\n+\trd32(IGC_ICTXPTC);\n+\trd32(IGC_ICTXATC);\n+\trd32(IGC_ICTXQEC);\n+\trd32(IGC_ICTXQMTC);\n+\trd32(IGC_ICRXDMTC);\n+\n+\trd32(IGC_CBTMPC);\n+\trd32(IGC_HTDPMC);\n+\trd32(IGC_CBRMPC);\n+\trd32(IGC_RPTHC);\n+\trd32(IGC_HGPTC);\n+\trd32(IGC_HTCBDPC);\n+\trd32(IGC_HGORCL);\n+\trd32(IGC_HGORCH);\n+\trd32(IGC_HGOTCL);\n+\trd32(IGC_HGOTCH);\n+\trd32(IGC_LENERRS);\n+}\n+\n+/**\n+ * igc_get_auto_rd_done - Check for auto read completion\n+ * @hw: pointer to the HW structure\n+ *\n+ * Check EEPROM for Auto Read done bit.\n+ */\n+s32 igc_get_auto_rd_done(struct igc_hw *hw)\n+{\n+\ts32 ret_val = 0;\n+\ts32 i = 0;\n+\n+\twhile (i < AUTO_READ_DONE_TIMEOUT) {\n+\t\tif (rd32(IGC_EECD) & IGC_EECD_AUTO_RD)\n+\t\t\tbreak;\n+\t\tusleep_range(1000, 2000);\n+\t\ti++;\n+\t}\n+\n+\tif (i == AUTO_READ_DONE_TIMEOUT) {\n+\t\thw_dbg(\"Auto read by HW from NVM has not completed.\\n\");\n+\t\tret_val = -IGC_ERR_RESET;\n+\t\tgoto out;\n+\t}\n+\n+out:\n+\treturn ret_val;\n+}\n+\n+/**\n+ * igc_put_hw_semaphore - Release hardware semaphore\n+ * @hw: pointer to the HW structure\n+ *\n+ * Release hardware semaphore used to access the PHY or NVM\n+ */\n+void igc_put_hw_semaphore(struct igc_hw *hw)\n+{\n+\tu32 swsm;\n+\n+\tswsm = rd32(IGC_SWSM);\n+\n+\tswsm &= ~(IGC_SWSM_SMBI | IGC_SWSM_SWESMBI);\n+\n+\twr32(IGC_SWSM, swsm);\n+}\ndiff --git a/drivers/net/ethernet/intel/igc/igc_mac.h b/drivers/net/ethernet/intel/igc/igc_mac.h\nindex 25b79a240d60..88bdb8dd6f3f 100644\n--- a/drivers/net/ethernet/intel/igc/igc_mac.h\n+++ b/drivers/net/ethernet/intel/igc/igc_mac.h\n@@ -4,8 +4,19 @@\n #ifndef _IGC_MAC_H_\n #define _IGC_MAC_H_\n \n+#include \"igc_hw.h\"\n+#include \"igc_defines.h\"\n+\n #ifndef IGC_REMOVED\n #define IGC_REMOVED(a) (0)\n #endif /* IGC_REMOVED */\n \n+/* forward declaration */\n+s32 igc_disable_pcie_master(struct igc_hw *hw);\n+void igc_init_rx_addrs(struct igc_hw *hw, u16 rar_count);\n+s32 igc_setup_link(struct igc_hw *hw);\n+void igc_clear_hw_cntrs_base(struct igc_hw *hw);\n+s32 igc_get_auto_rd_done(struct igc_hw *hw);\n+void igc_put_hw_semaphore(struct igc_hw *hw);\n+\n #endif\ndiff --git a/drivers/net/ethernet/intel/igc/igc_main.c b/drivers/net/ethernet/intel/igc/igc_main.c\nindex db7b6820e0f0..f2ad49fcd39b 100644\n--- a/drivers/net/ethernet/intel/igc/igc_main.c\n+++ b/drivers/net/ethernet/intel/igc/igc_main.c\n@@ -64,6 +64,14 @@ enum latency_range {\n \n static void igc_reset(struct igc_adapter *adapter)\n {\n+\tstruct pci_dev *pdev = adapter->pdev;\n+\tstruct igc_hw *hw = &adapter->hw;\n+\n+\thw->mac.ops.reset_hw(hw);\n+\n+\tif (hw->mac.ops.init_hw(hw))\n+\t\tdev_err(&pdev->dev, \"Hardware Error\\n\");\n+\n \tif (!netif_running(adapter->netdev))\n \t\tigc_power_down_link(adapter);\n }\n@@ -3556,6 +3564,19 @@ static int igc_sw_init(struct igc_adapter *adapter)\n }\n \n /**\n+ * igc_get_hw_dev - return device\n+ * @hw: pointer to hardware structure\n+ *\n+ * used by hardware layer to print debugging information\n+ */\n+struct net_device *igc_get_hw_dev(struct igc_hw *hw)\n+{\n+\tstruct igc_adapter *adapter = hw->back;\n+\n+\treturn adapter->netdev;\n+}\n+\n+/**\n * igc_init_module - Driver Registration Routine\n *\n * igc_init_module is the first routine called when the driver is\ndiff --git a/drivers/net/ethernet/intel/igc/igc_regs.h b/drivers/net/ethernet/intel/igc/igc_regs.h\nindex e268986eeb9f..c57f573fb864 100644\n--- a/drivers/net/ethernet/intel/igc/igc_regs.h\n+++ b/drivers/net/ethernet/intel/igc/igc_regs.h\n@@ -7,6 +7,7 @@\n /* General Register Descriptions */\n #define IGC_CTRL\t\t0x00000 /* Device Control - RW */\n #define IGC_STATUS\t\t0x00008 /* Device Status - RO */\n+#define IGC_EECD\t\t0x00010 /* EEPROM/Flash Control - RW */\n #define IGC_CTRL_EXT\t\t0x00018 /* Extended Device Control - RW */\n #define IGC_MDIC\t\t0x00020 /* MDI Control - RW */\n #define IGC_MDICNFG\t\t0x00E04 /* MDC/MDIO Configuration - RW */\n@@ -56,6 +57,23 @@\n #define IGC_IVAR_MISC\t\t0x01740 /* IVAR for \"other\" causes - RW */\n #define IGC_GPIE\t\t0x01514 /* General Purpose Intr Enable - RW */\n \n+/* Interrupt Cause */\n+#define IGC_ICRXPTC\t\t0x04104 /* Rx Packet Timer Expire Count */\n+#define IGC_ICRXATC\t\t0x04108 /* Rx Absolute Timer Expire Count */\n+#define IGC_ICTXPTC\t\t0x0410C /* Tx Packet Timer Expire Count */\n+#define IGC_ICTXATC\t\t0x04110 /* Tx Absolute Timer Expire Count */\n+#define IGC_ICTXQEC\t\t0x04118 /* Tx Queue Empty Count */\n+#define IGC_ICTXQMTC\t\t0x0411C /* Tx Queue Min Threshold Count */\n+#define IGC_ICRXDMTC\t\t0x04120 /* Rx Descriptor Min Threshold Count */\n+#define IGC_ICRXOC\t\t0x04124 /* Receiver Overrun Count */\n+\n+#define IGC_CBTMPC\t\t0x0402C /* Circuit Breaker TX Packet Count */\n+#define IGC_HTDPMC\t\t0x0403C /* Host Transmit Discarded Packets */\n+#define IGC_CBRMPC\t\t0x040FC /* Circuit Breaker RX Packet Count */\n+#define IGC_RPTHC\t\t0x04104 /* Rx Packets To Host */\n+#define IGC_HGPTC\t\t0x04118 /* Host Good Packets TX Count */\n+#define IGC_HTCBDPC\t\t0x04124 /* Host TX Circ.Breaker Drop Count */\n+\n /* MSI-X Table Register Descriptions */\n #define IGC_PBACL\t\t0x05B68 /* MSIx PBA Clear - R/W 1 to clear */\n \n@@ -73,6 +91,8 @@\n #define IGC_RXCSUM\t\t0x05000 /* Rx Checksum Control - RW */\n #define IGC_RLPML\t\t0x05004 /* Rx Long Packet Max Length */\n #define IGC_RFCTL\t\t0x05008 /* Receive Filter Control*/\n+#define IGC_MTA\t\t\t0x05200 /* Multicast Table Array - RW Array */\n+#define IGC_UTA\t\t\t0x0A000 /* Unicast Table Array - RW */\n #define IGC_RAL(_n)\t\t(0x05400 + ((_n) * 0x08))\n #define IGC_RAH(_n)\t\t(0x05404 + ((_n) * 0x08))\n \n", "prefixes": [ "v8", "07/11" ] }