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GET /api/patches/972079/?format=api
{ "id": 972079, "url": "http://patchwork.ozlabs.org/api/patches/972079/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20180920004308.13772-4-anirudh.venkataramanan@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20180920004308.13772-4-anirudh.venkataramanan@intel.com>", "list_archive_url": null, "date": "2018-09-20T00:42:55", "name": "[v2,03/16] ice: Add handler to configure SR-IOV", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "9fda2c47cbe4ee379fc98e315beef6c4fde36ae4", "submitter": { "id": 73601, "url": "http://patchwork.ozlabs.org/api/people/73601/?format=api", "name": "Anirudh Venkataramanan", "email": "anirudh.venkataramanan@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20180920004308.13772-4-anirudh.venkataramanan@intel.com/mbox/", "series": [ { "id": 66527, "url": "http://patchwork.ozlabs.org/api/series/66527/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=66527", "date": "2018-09-20T00:42:53", "name": "Add SR-IOV support, feature updates", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/66527/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/972079/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/972079/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.136; helo=silver.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 42Fydk1Wvcz9sBJ\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 20 Sep 2018 10:43:38 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id BB14B302BD;\n\tThu, 20 Sep 2018 00:43:36 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 7INuDkq+UTfE; Thu, 20 Sep 2018 00:43:25 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby silver.osuosl.org (Postfix) with ESMTP id 91BBC3096B;\n\tThu, 20 Sep 2018 00:43:21 +0000 (UTC)", "from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\tby ash.osuosl.org (Postfix) with ESMTP id 835571C08AF\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 20 Sep 2018 00:43:14 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 7F7D3876DB\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 20 Sep 2018 00:43:14 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id Cuj-kkIcm87H for <intel-wired-lan@lists.osuosl.org>;\n\tThu, 20 Sep 2018 00:43:09 +0000 (UTC)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n\tby fraxinus.osuosl.org (Postfix) with ESMTPS id D941787695\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 20 Sep 2018 00:43:09 +0000 (UTC)", "from orsmga004.jf.intel.com ([10.7.209.38])\n\tby fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t19 Sep 2018 17:43:09 -0700", "from shasta.jf.intel.com ([10.166.241.11])\n\tby orsmga004.jf.intel.com with ESMTP; 19 Sep 2018 17:43:08 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.53,396,1531810800\"; d=\"scan'208\";a=\"234371593\"", "From": "Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Wed, 19 Sep 2018 17:42:55 -0700", "Message-Id": "<20180920004308.13772-4-anirudh.venkataramanan@intel.com>", "X-Mailer": "git-send-email 2.14.3", "In-Reply-To": "<20180920004308.13772-1-anirudh.venkataramanan@intel.com>", "References": "<20180920004308.13772-1-anirudh.venkataramanan@intel.com>", "Subject": "[Intel-wired-lan] [PATCH v2 03/16] ice: Add handler to configure\n\tSR-IOV", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.24", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "This patch implements parts of ice_sriov_configure and VF reset flow.\n\nTo create virtual functions (VFs), the user sets a value in num_vfs\nthrough sysfs. This results in the kernel calling the handler for\n.sriov_configure which is ice_sriov_configure.\n\nVF setup first starts with a VF reset, followed by allocation of the VF\nVSI using ice_vf_vsi_setup. Once the VF setup is complete a state bit\nICE_VF_STATE_INIT is set in the vf->states bitmap to indicate that\nthe VF is ready to go.\n\nAlso for VF reset to go into effect, it's necessary to issue a disable\nqueue command (ice_aqc_opc_dis_txqs). So this patch updates multiple\nfunctions in the disable queue flow to take additional parameters that\ndistinguish if queues are being disabled due to VF reset.\n\nSigned-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>\n---\n drivers/net/ethernet/intel/ice/Makefile | 1 +\n drivers/net/ethernet/intel/ice/ice.h | 24 +\n drivers/net/ethernet/intel/ice/ice_common.c | 56 +-\n drivers/net/ethernet/intel/ice/ice_common.h | 4 +-\n drivers/net/ethernet/intel/ice/ice_hw_autogen.h | 38 +\n drivers/net/ethernet/intel/ice/ice_lib.c | 7 +-\n drivers/net/ethernet/intel/ice/ice_lib.h | 3 +-\n drivers/net/ethernet/intel/ice/ice_main.c | 6 +-\n drivers/net/ethernet/intel/ice/ice_type.h | 10 +\n drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c | 847 +++++++++++++++++++++++\n drivers/net/ethernet/intel/ice/ice_virtchnl_pf.h | 74 ++\n 11 files changed, 1061 insertions(+), 9 deletions(-)\n create mode 100644 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c\n create mode 100644 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.h", "diff": "diff --git a/drivers/net/ethernet/intel/ice/Makefile b/drivers/net/ethernet/intel/ice/Makefile\nindex 45125bd074d9..1999cd09239e 100644\n--- a/drivers/net/ethernet/intel/ice/Makefile\n+++ b/drivers/net/ethernet/intel/ice/Makefile\n@@ -16,3 +16,4 @@ ice-y := ice_main.o\t\\\n \t ice_lib.o\t\\\n \t ice_txrx.o\t\\\n \t ice_ethtool.o\n+ice-$(CONFIG_PCI_IOV) += ice_virtchnl_pf.o\ndiff --git a/drivers/net/ethernet/intel/ice/ice.h b/drivers/net/ethernet/intel/ice/ice.h\nindex 4deb6c88e199..89e6112bc819 100644\n--- a/drivers/net/ethernet/intel/ice/ice.h\n+++ b/drivers/net/ethernet/intel/ice/ice.h\n@@ -28,6 +28,7 @@\n #include <linux/ip.h>\n #include <linux/ipv6.h>\n #include <linux/if_bridge.h>\n+#include <linux/avf/virtchnl.h>\n #include <net/ipv6.h>\n #include \"ice_devids.h\"\n #include \"ice_type.h\"\n@@ -35,6 +36,7 @@\n #include \"ice_switch.h\"\n #include \"ice_common.h\"\n #include \"ice_sched.h\"\n+#include \"ice_virtchnl_pf.h\"\n \n extern const char ice_drv_ver[];\n #define ICE_BAR0\t\t0\n@@ -65,6 +67,12 @@ extern const char ice_drv_ver[];\n #define ICE_INVAL_Q_INDEX\t0xffff\n #define ICE_INVAL_VFID\t\t256\n #define ICE_MAX_VF_COUNT\t256\n+#define ICE_MAX_QS_PER_VF\t\t256\n+#define ICE_MIN_QS_PER_VF\t\t1\n+#define ICE_DFLT_QS_PER_VF\t\t4\n+#define ICE_MAX_INTR_PER_VF\t\t65\n+#define ICE_MIN_INTR_PER_VF\t\t(ICE_MIN_QS_PER_VF + 1)\n+#define ICE_DFLT_INTR_PER_VF\t\t(ICE_DFLT_QS_PER_VF + 1)\n \n #define ICE_VSIQF_HKEY_ARRAY_SIZE\t((VSIQF_HKEY_MAX_INDEX + 1) *\t4)\n \n@@ -135,10 +143,20 @@ enum ice_state {\n \t__ICE_EMPR_RECV,\t\t/* set by OICR handler */\n \t__ICE_SUSPENDED,\t\t/* set on module remove path */\n \t__ICE_RESET_FAILED,\t\t/* set by reset/rebuild */\n+\t/* When checking for the PF to be in a nominal operating state, the\n+\t * bits that are grouped at the beginning of the list need to be\n+\t * checked. Bits occurring before __ICE_STATE_NOMINAL_CHECK_BITS will\n+\t * be checked. If you need to add a bit into consideration for nominal\n+\t * operating state, it must be added before\n+\t * __ICE_STATE_NOMINAL_CHECK_BITS. Do not move this entry's position\n+\t * without appropriate consideration.\n+\t */\n+\t__ICE_STATE_NOMINAL_CHECK_BITS,\n \t__ICE_ADMINQ_EVENT_PENDING,\n \t__ICE_MAILBOXQ_EVENT_PENDING,\n \t__ICE_MDD_EVENT_PENDING,\n \t__ICE_FLTR_OVERFLOW_PROMISC,\n+\t__ICE_VF_DIS,\n \t__ICE_CFG_BUSY,\n \t__ICE_SERVICE_SCHED,\n \t__ICE_SERVICE_DIS,\n@@ -243,6 +261,7 @@ enum ice_pf_flags {\n \tICE_FLAG_MSIX_ENA,\n \tICE_FLAG_FLTR_SYNC,\n \tICE_FLAG_RSS_ENA,\n+\tICE_FLAG_SRIOV_ENA,\n \tICE_FLAG_SRIOV_CAPABLE,\n \tICE_PF_FLAGS_NBITS\t\t/* must be last */\n };\n@@ -259,7 +278,12 @@ struct ice_pf {\n \n \tstruct ice_vsi **vsi;\t\t/* VSIs created by the driver */\n \tstruct ice_sw *first_sw;\t/* first switch created by firmware */\n+\t/* Virtchnl/SR-IOV config info */\n+\tstruct ice_vf *vf;\n+\tint num_alloc_vfs;\t\t/* actual number of VFs allocated */\n \tu16 num_vfs_supported;\t\t/* num VFs supported for this PF */\n+\tu16 num_vf_qps;\t\t\t/* num queue pairs per VF */\n+\tu16 num_vf_msix;\t\t/* num vectors per VF */\n \tDECLARE_BITMAP(state, __ICE_STATE_NBITS);\n \tDECLARE_BITMAP(avail_txqs, ICE_MAX_TXQS);\n \tDECLARE_BITMAP(avail_rxqs, ICE_MAX_RXQS);\ndiff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c\nindex 4612d5fa9416..ec04bc21636f 100644\n--- a/drivers/net/ethernet/intel/ice/ice_common.c\n+++ b/drivers/net/ethernet/intel/ice/ice_common.c\n@@ -2287,6 +2287,8 @@ ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,\n * @num_qgrps: number of groups in the list\n * @qg_list: the list of groups to disable\n * @buf_size: the total size of the qg_list buffer in bytes\n+ * @rst_src: if called due to reset, specifies the rst source\n+ * @vmvf_num: the relative vm or vf number that is undergoing the reset\n * @cd: pointer to command details structure or NULL\n *\n * Disable LAN Tx queue (0x0C31)\n@@ -2294,6 +2296,7 @@ ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,\n static enum ice_status\n ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,\n \t\t struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,\n+\t\t enum ice_disq_rst_src rst_src, u16 vmvf_num,\n \t\t struct ice_sq_cd *cd)\n {\n \tstruct ice_aqc_dis_txqs *cmd;\n@@ -2303,14 +2306,45 @@ ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,\n \tcmd = &desc.params.dis_txqs;\n \tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);\n \n-\tif (!qg_list)\n+\t/* qg_list can be NULL only in VM/VF reset flow */\n+\tif (!qg_list && !rst_src)\n \t\treturn ICE_ERR_PARAM;\n \n \tif (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)\n \t\treturn ICE_ERR_PARAM;\n-\tdesc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);\n+\n \tcmd->num_entries = num_qgrps;\n \n+\tcmd->vmvf_and_timeout = cpu_to_le16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &\n+\t\t\t\t\t ICE_AQC_Q_DIS_TIMEOUT_M);\n+\n+\tswitch (rst_src) {\n+\tcase ICE_VM_RESET:\n+\t\tcmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;\n+\t\tcmd->vmvf_and_timeout |=\n+\t\t\tcpu_to_le16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);\n+\t\tbreak;\n+\tcase ICE_VF_RESET:\n+\t\tcmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET;\n+\t\t/* In this case, FW expects vmvf_num to be absolute VF id */\n+\t\tcmd->vmvf_and_timeout |=\n+\t\t\tcpu_to_le16((vmvf_num + hw->func_caps.vf_base_id) &\n+\t\t\t\t ICE_AQC_Q_DIS_VMVF_NUM_M);\n+\t\tbreak;\n+\tcase ICE_NO_RESET:\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\t/* If no queue group info, we are in a reset flow. Issue the AQ */\n+\tif (!qg_list)\n+\t\tgoto do_aq;\n+\n+\t/* set RD bit to indicate that command buffer is provided by the driver\n+\t * and it needs to be read by the firmware\n+\t */\n+\tdesc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);\n+\n \tfor (i = 0; i < num_qgrps; ++i) {\n \t\t/* Calculate the size taken up by the queue IDs in this group */\n \t\tsz += qg_list[i].num_qs * sizeof(qg_list[i].q_id);\n@@ -2326,6 +2360,7 @@ ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,\n \tif (buf_size != sz)\n \t\treturn ICE_ERR_PARAM;\n \n+do_aq:\n \treturn ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);\n }\n \n@@ -2632,13 +2667,16 @@ ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_qgrps,\n * @num_queues: number of queues\n * @q_ids: pointer to the q_id array\n * @q_teids: pointer to queue node teids\n+ * @rst_src: if called due to reset, specifies the rst source\n+ * @vmvf_num: the relative vm or vf number that is undergoing the reset\n * @cd: pointer to command details structure or NULL\n *\n * This function removes queues and their corresponding nodes in SW DB\n */\n enum ice_status\n ice_dis_vsi_txq(struct ice_port_info *pi, u8 num_queues, u16 *q_ids,\n-\t\tu32 *q_teids, struct ice_sq_cd *cd)\n+\t\tu32 *q_teids, enum ice_disq_rst_src rst_src, u16 vmvf_num,\n+\t\tstruct ice_sq_cd *cd)\n {\n \tenum ice_status status = ICE_ERR_DOES_NOT_EXIST;\n \tstruct ice_aqc_dis_txq_item qg_list;\n@@ -2647,6 +2685,15 @@ ice_dis_vsi_txq(struct ice_port_info *pi, u8 num_queues, u16 *q_ids,\n \tif (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)\n \t\treturn ICE_ERR_CFG;\n \n+\t/* if queue is disabled already yet the disable queue command has to be\n+\t * sent to complete the VF reset, then call ice_aq_dis_lan_txq without\n+\t * any queue information\n+\t */\n+\n+\tif (!num_queues && rst_src)\n+\t\treturn ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src, vmvf_num,\n+\t\t\t\t\t NULL);\n+\n \tmutex_lock(&pi->sched_lock);\n \n \tfor (i = 0; i < num_queues; i++) {\n@@ -2659,7 +2706,8 @@ ice_dis_vsi_txq(struct ice_port_info *pi, u8 num_queues, u16 *q_ids,\n \t\tqg_list.num_qs = 1;\n \t\tqg_list.q_id[0] = cpu_to_le16(q_ids[i]);\n \t\tstatus = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list,\n-\t\t\t\t\t sizeof(qg_list), cd);\n+\t\t\t\t\t sizeof(qg_list), rst_src, vmvf_num,\n+\t\t\t\t\t cd);\n \n \t\tif (status)\n \t\t\tbreak;\ndiff --git a/drivers/net/ethernet/intel/ice/ice_common.h b/drivers/net/ethernet/intel/ice/ice_common.h\nindex 7b2a5bb2e550..1900681289a4 100644\n--- a/drivers/net/ethernet/intel/ice/ice_common.h\n+++ b/drivers/net/ethernet/intel/ice/ice_common.h\n@@ -7,6 +7,7 @@\n #include \"ice.h\"\n #include \"ice_type.h\"\n #include \"ice_switch.h\"\n+#include <linux/avf/virtchnl.h>\n \n void ice_debug_cq(struct ice_hw *hw, u32 mask, void *desc, void *buf,\n \t\t u16 buf_len);\n@@ -89,7 +90,8 @@ ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,\n \t\t struct ice_sq_cd *cd);\n enum ice_status\n ice_dis_vsi_txq(struct ice_port_info *pi, u8 num_queues, u16 *q_ids,\n-\t\tu32 *q_teids, struct ice_sq_cd *cmd_details);\n+\t\tu32 *q_teids, enum ice_disq_rst_src rst_src, u16 vmvf_num,\n+\t\tstruct ice_sq_cd *cmd_details);\n enum ice_status\n ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,\n \t\tu16 *max_lanqs);\ndiff --git a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h\nindex c2d867b756ef..b676b3151d04 100644\n--- a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h\n+++ b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h\n@@ -90,10 +90,16 @@\n #define GLGEN_RTRIG_CORER_M\t\t\tBIT(0)\n #define GLGEN_RTRIG_GLOBR_M\t\t\tBIT(1)\n #define GLGEN_STAT\t\t\t\t0x000B612C\n+#define GLGEN_VFLRSTAT(_i)\t\t\t(0x00093A04 + ((_i) * 4))\n #define PFGEN_CTRL\t\t\t\t0x00091000\n #define PFGEN_CTRL_PFSWR_M\t\t\tBIT(0)\n #define PFGEN_STATE\t\t\t\t0x00088000\n #define PRTGEN_STATUS\t\t\t\t0x000B8100\n+#define VFGEN_RSTAT(_VF)\t\t\t(0x00074000 + ((_VF) * 4))\n+#define VPGEN_VFRSTAT(_VF)\t\t\t(0x00090800 + ((_VF) * 4))\n+#define VPGEN_VFRSTAT_VFRD_M\t\t\tBIT(0)\n+#define VPGEN_VFRTRIG(_VF)\t\t\t(0x00090000 + ((_VF) * 4))\n+#define VPGEN_VFRTRIG_VFSWR_M\t\t\tBIT(0)\n #define PFHMC_ERRORDATA\t\t\t\t0x00520500\n #define PFHMC_ERRORINFO\t\t\t\t0x00520400\n #define GLINT_DYN_CTL(_INT)\t\t\t(0x00160000 + ((_INT) * 4))\n@@ -106,6 +112,13 @@\n #define GLINT_ITR(_i, _INT)\t\t\t(0x00154000 + ((_i) * 8192 + (_INT) * 4))\n #define GLINT_RATE(_INT)\t\t\t(0x0015A000 + ((_INT) * 4))\n #define GLINT_RATE_INTRL_ENA_M\t\t\tBIT(6)\n+#define GLINT_VECT2FUNC(_INT)\t\t\t(0x00162000 + ((_INT) * 4))\n+#define GLINT_VECT2FUNC_VF_NUM_S\t\t0\n+#define GLINT_VECT2FUNC_VF_NUM_M\t\tICE_M(0xFF, 0)\n+#define GLINT_VECT2FUNC_PF_NUM_S\t\t12\n+#define GLINT_VECT2FUNC_PF_NUM_M\t\tICE_M(0x7, 12)\n+#define GLINT_VECT2FUNC_IS_PF_S\t\t\t16\n+#define GLINT_VECT2FUNC_IS_PF_M\t\t\tBIT(16)\n #define PFINT_FW_CTL\t\t\t\t0x0016C800\n #define PFINT_FW_CTL_MSIX_INDX_M\t\tICE_M(0x7FF, 0)\n #define PFINT_FW_CTL_ITR_INDX_S\t\t\t11\n@@ -137,6 +150,12 @@\n #define QINT_TQCTL_MSIX_INDX_S\t\t\t0\n #define QINT_TQCTL_ITR_INDX_S\t\t\t11\n #define QINT_TQCTL_CAUSE_ENA_M\t\t\tBIT(30)\n+#define VPINT_ALLOC(_VF)\t\t\t(0x001D1000 + ((_VF) * 4))\n+#define VPINT_ALLOC_FIRST_S\t\t\t0\n+#define VPINT_ALLOC_FIRST_M\t\t\tICE_M(0x7FF, 0)\n+#define VPINT_ALLOC_LAST_S\t\t\t12\n+#define VPINT_ALLOC_LAST_M\t\t\tICE_M(0x7FF, 12)\n+#define VPINT_ALLOC_VALID_M\t\t\tBIT(31)\n #define QRX_CONTEXT(_i, _QRX)\t\t\t(0x00280000 + ((_i) * 8192 + (_QRX) * 4))\n #define QRX_CTRL(_QRX)\t\t\t\t(0x00120000 + ((_QRX) * 4))\n #define QRX_CTRL_MAX_INDEX\t\t\t2047\n@@ -149,6 +168,20 @@\n #define QRX_TAIL_MAX_INDEX\t\t\t2047\n #define QRX_TAIL_TAIL_S\t\t\t\t0\n #define QRX_TAIL_TAIL_M\t\t\t\tICE_M(0x1FFF, 0)\n+#define VPLAN_RX_QBASE(_VF)\t\t\t(0x00072000 + ((_VF) * 4))\n+#define VPLAN_RX_QBASE_VFFIRSTQ_S\t\t0\n+#define VPLAN_RX_QBASE_VFFIRSTQ_M\t\tICE_M(0x7FF, 0)\n+#define VPLAN_RX_QBASE_VFNUMQ_S\t\t\t16\n+#define VPLAN_RX_QBASE_VFNUMQ_M\t\t\tICE_M(0xFF, 16)\n+#define VPLAN_RXQ_MAPENA(_VF)\t\t\t(0x00073000 + ((_VF) * 4))\n+#define VPLAN_RXQ_MAPENA_RX_ENA_M\t\tBIT(0)\n+#define VPLAN_TX_QBASE(_VF)\t\t\t(0x001D1800 + ((_VF) * 4))\n+#define VPLAN_TX_QBASE_VFFIRSTQ_S\t\t0\n+#define VPLAN_TX_QBASE_VFFIRSTQ_M\t\tICE_M(0x3FFF, 0)\n+#define VPLAN_TX_QBASE_VFNUMQ_S\t\t\t16\n+#define VPLAN_TX_QBASE_VFNUMQ_M\t\t\tICE_M(0xFF, 16)\n+#define VPLAN_TXQ_MAPENA(_VF)\t\t\t(0x00073800 + ((_VF) * 4))\n+#define VPLAN_TXQ_MAPENA_TX_ENA_M\t\tBIT(0)\n #define GL_MDET_RX\t\t\t\t0x00294C00\n #define GL_MDET_RX_QNUM_S\t\t\t0\n #define GL_MDET_RX_QNUM_M\t\t\tICE_M(0x7FFF, 0)\n@@ -196,6 +229,9 @@\n #define PF_FUNC_RID\t\t\t\t0x0009E880\n #define PF_FUNC_RID_FUNC_NUM_S\t\t\t0\n #define PF_FUNC_RID_FUNC_NUM_M\t\t\tICE_M(0x7, 0)\n+#define PF_PCI_CIAA\t\t\t\t0x0009E580\n+#define PF_PCI_CIAA_VF_NUM_S\t\t\t12\n+#define PF_PCI_CIAD\t\t\t\t0x0009E500\n #define GL_PWR_MODE_CTL\t\t\t\t0x000B820C\n #define GL_PWR_MODE_CTL_CAR_MAX_BW_S\t\t30\n #define GL_PWR_MODE_CTL_CAR_MAX_BW_M\t\tICE_M(0x3, 30)\n@@ -276,5 +312,7 @@\n #define GLV_UPTCH(_i)\t\t\t\t(0x0030A004 + ((_i) * 8))\n #define GLV_UPTCL(_i)\t\t\t\t(0x0030A000 + ((_i) * 8))\n #define VSIQF_HKEY_MAX_INDEX\t\t\t12\n+#define VFINT_DYN_CTLN(_i)\t\t\t(0x00003800 + ((_i) * 4))\n+#define VFINT_DYN_CTLN_CLEARPBA_M\t\tBIT(1)\n \n #endif /* _ICE_HW_AUTOGEN_H_ */\ndiff --git a/drivers/net/ethernet/intel/ice/ice_lib.c b/drivers/net/ethernet/intel/ice/ice_lib.c\nindex d67d7005916c..45459c6a0d24 100644\n--- a/drivers/net/ethernet/intel/ice/ice_lib.c\n+++ b/drivers/net/ethernet/intel/ice/ice_lib.c\n@@ -1784,8 +1784,11 @@ int ice_vsi_stop_rx_rings(struct ice_vsi *vsi)\n /**\n * ice_vsi_stop_tx_rings - Disable Tx rings\n * @vsi: the VSI being configured\n+ * @rst_src: reset source\n+ * @rel_vmvf_num: Relative id of VF/VM\n */\n-int ice_vsi_stop_tx_rings(struct ice_vsi *vsi)\n+int ice_vsi_stop_tx_rings(struct ice_vsi *vsi, enum ice_disq_rst_src rst_src,\n+\t\t\t u16 rel_vmvf_num)\n {\n \tstruct ice_pf *pf = vsi->back;\n \tstruct ice_hw *hw = &pf->hw;\n@@ -1837,7 +1840,7 @@ int ice_vsi_stop_tx_rings(struct ice_vsi *vsi)\n \t\t GLINT_DYN_CTL_SWINT_TRIG_M | GLINT_DYN_CTL_INTENA_MSK_M);\n \t}\n \tstatus = ice_dis_vsi_txq(vsi->port_info, vsi->num_txq, q_ids, q_teids,\n-\t\t\t\t NULL);\n+\t\t\t\t rst_src, rel_vmvf_num, NULL);\n \t/* if the disable queue command was exercised during an active reset\n \t * flow, ICE_ERR_RESET_ONGOING is returned. This is not an error as\n \t * the reset operation disables queues at the hardware level anyway.\ndiff --git a/drivers/net/ethernet/intel/ice/ice_lib.h b/drivers/net/ethernet/intel/ice/ice_lib.h\nindex 2617afe01c82..677db40338f5 100644\n--- a/drivers/net/ethernet/intel/ice/ice_lib.h\n+++ b/drivers/net/ethernet/intel/ice/ice_lib.h\n@@ -31,7 +31,8 @@ int ice_vsi_start_rx_rings(struct ice_vsi *vsi);\n \n int ice_vsi_stop_rx_rings(struct ice_vsi *vsi);\n \n-int ice_vsi_stop_tx_rings(struct ice_vsi *vsi);\n+int ice_vsi_stop_tx_rings(struct ice_vsi *vsi, enum ice_disq_rst_src rst_src,\n+\t\t\t u16 rel_vmvf_num);\n \n int ice_cfg_vlan_pruning(struct ice_vsi *vsi, bool ena);\n \ndiff --git a/drivers/net/ethernet/intel/ice/ice_main.c b/drivers/net/ethernet/intel/ice/ice_main.c\nindex 59bcf5edd447..7e15f9e7ba95 100644\n--- a/drivers/net/ethernet/intel/ice/ice_main.c\n+++ b/drivers/net/ethernet/intel/ice/ice_main.c\n@@ -2184,6 +2184,8 @@ static void ice_remove(struct pci_dev *pdev)\n \tset_bit(__ICE_DOWN, pf->state);\n \tice_service_task_stop(pf);\n \n+\tif (test_bit(ICE_FLAG_SRIOV_ENA, pf->flags))\n+\t\tice_free_vfs(pf);\n \tice_vsi_release_all(pf);\n \tice_free_irq_msix_misc(pf);\n \tice_clear_interrupt_scheme(pf);\n@@ -2214,6 +2216,7 @@ static struct pci_driver ice_driver = {\n \t.id_table = ice_pci_tbl,\n \t.probe = ice_probe,\n \t.remove = ice_remove,\n+\t.sriov_configure = ice_sriov_configure,\n };\n \n /**\n@@ -2973,7 +2976,7 @@ int ice_down(struct ice_vsi *vsi)\n \t}\n \n \tice_vsi_dis_irq(vsi);\n-\ttx_err = ice_vsi_stop_tx_rings(vsi);\n+\ttx_err = ice_vsi_stop_tx_rings(vsi, ICE_NO_RESET, 0);\n \tif (tx_err)\n \t\tnetdev_err(vsi->netdev,\n \t\t\t \"Failed stop tx rings, VSI %d error %d\\n\",\n@@ -3375,6 +3378,7 @@ static void ice_rebuild(struct ice_pf *pf)\n \t\tgoto err_vsi_rebuild;\n \t}\n \n+\tice_reset_all_vfs(pf, true);\n \t/* if we get here, reset flow is successful */\n \tclear_bit(__ICE_RESET_FAILED, pf->state);\n \treturn;\ndiff --git a/drivers/net/ethernet/intel/ice/ice_type.h b/drivers/net/ethernet/intel/ice/ice_type.h\nindex 6d053fb5f941..15b3c999006a 100644\n--- a/drivers/net/ethernet/intel/ice/ice_type.h\n+++ b/drivers/net/ethernet/intel/ice/ice_type.h\n@@ -104,6 +104,15 @@ struct ice_link_status {\n \tu8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];\n };\n \n+/* Different reset sources for which a disable queue AQ call has to be made in\n+ * order to clean the TX scheduler as a part of the reset\n+ */\n+enum ice_disq_rst_src {\n+\tICE_NO_RESET = 0,\n+\tICE_VM_RESET,\n+\tICE_VF_RESET,\n+};\n+\n /* PHY info such as phy_type, etc... */\n struct ice_phy_info {\n \tstruct ice_link_status link_info;\n@@ -130,6 +139,7 @@ struct ice_hw_common_caps {\n \n \t/* Virtualization support */\n \tu8 sr_iov_1_1;\t\t\t/* SR-IOV enabled */\n+\n \t/* RSS related capabilities */\n \tu16 rss_table_size;\t\t/* 512 for PFs and 64 for VFs */\n \tu8 rss_table_entry_width;\t/* RSS Entry width in bits */\ndiff --git a/drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c b/drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c\nnew file mode 100644\nindex 000000000000..1b7017c1f190\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c\n@@ -0,0 +1,847 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/* Copyright (c) 2018, Intel Corporation. */\n+\n+#include \"ice.h\"\n+#include \"ice_lib.h\"\n+\n+/**\n+ * ice_get_vf_vector - get VF interrupt vector register offset\n+ * @vf_msix: number of msix vector per VF on a PF\n+ * @vf_id: VF identifier\n+ * @i: index of msix vector\n+ */\n+static u32 ice_get_vf_vector(int vf_msix, int vf_id, int i)\n+{\n+\treturn ((i == 0) ? VFINT_DYN_CTLN(vf_id) :\n+\t\t VFINT_DYN_CTLN(((vf_msix - 1) * (vf_id)) + (i - 1)));\n+}\n+\n+/**\n+ * ice_free_vf_res - Free a VF's resources\n+ * @vf: pointer to the VF info\n+ */\n+static void ice_free_vf_res(struct ice_vf *vf)\n+{\n+\tstruct ice_pf *pf = vf->pf;\n+\tint i, pf_vf_msix;\n+\n+\t/* First, disable VF's configuration API to prevent OS from\n+\t * accessing the VF's VSI after it's freed or invalidated.\n+\t */\n+\tclear_bit(ICE_VF_STATE_INIT, vf->vf_states);\n+\n+\t/* free vsi & disconnect it from the parent uplink */\n+\tif (vf->lan_vsi_idx) {\n+\t\tice_vsi_release(pf->vsi[vf->lan_vsi_idx]);\n+\t\tvf->lan_vsi_idx = 0;\n+\t\tvf->lan_vsi_num = 0;\n+\t\tvf->num_mac = 0;\n+\t}\n+\n+\tpf_vf_msix = pf->num_vf_msix;\n+\t/* Disable interrupts so that VF starts in a known state */\n+\tfor (i = 0; i < pf_vf_msix; i++) {\n+\t\tu32 reg_idx;\n+\n+\t\treg_idx = ice_get_vf_vector(pf_vf_msix, vf->vf_id, i);\n+\t\twr32(&pf->hw, reg_idx, VFINT_DYN_CTLN_CLEARPBA_M);\n+\t\tice_flush(&pf->hw);\n+\t}\n+\t/* reset some of the state variables keeping track of the resources */\n+\tclear_bit(ICE_VF_STATE_MC_PROMISC, vf->vf_states);\n+\tclear_bit(ICE_VF_STATE_UC_PROMISC, vf->vf_states);\n+}\n+\n+/***********************enable_vf routines*****************************/\n+\n+/**\n+ * ice_dis_vf_mappings\n+ * @vf: pointer to the VF structure\n+ */\n+static void ice_dis_vf_mappings(struct ice_vf *vf)\n+{\n+\tstruct ice_pf *pf = vf->pf;\n+\tstruct ice_vsi *vsi;\n+\tint first, last, v;\n+\tstruct ice_hw *hw;\n+\n+\thw = &pf->hw;\n+\tvsi = pf->vsi[vf->lan_vsi_idx];\n+\n+\twr32(hw, VPINT_ALLOC(vf->vf_id), 0);\n+\n+\tfirst = vf->first_vector_idx;\n+\tlast = first + pf->num_vf_msix - 1;\n+\tfor (v = first; v <= last; v++) {\n+\t\tu32 reg;\n+\n+\t\treg = (((1 << GLINT_VECT2FUNC_IS_PF_S) &\n+\t\t\tGLINT_VECT2FUNC_IS_PF_M) |\n+\t\t ((hw->pf_id << GLINT_VECT2FUNC_PF_NUM_S) &\n+\t\t\tGLINT_VECT2FUNC_PF_NUM_M));\n+\t\twr32(hw, GLINT_VECT2FUNC(v), reg);\n+\t}\n+\n+\tif (vsi->tx_mapping_mode == ICE_VSI_MAP_CONTIG)\n+\t\twr32(hw, VPLAN_TX_QBASE(vf->vf_id), 0);\n+\telse\n+\t\tdev_err(&pf->pdev->dev,\n+\t\t\t\"Scattered mode for VF Tx queues is not yet implemented\\n\");\n+\n+\tif (vsi->rx_mapping_mode == ICE_VSI_MAP_CONTIG)\n+\t\twr32(hw, VPLAN_RX_QBASE(vf->vf_id), 0);\n+\telse\n+\t\tdev_err(&pf->pdev->dev,\n+\t\t\t\"Scattered mode for VF Rx queues is not yet implemented\\n\");\n+}\n+\n+/**\n+ * ice_free_vfs - Free all VFs\n+ * @pf: pointer to the PF structure\n+ */\n+void ice_free_vfs(struct ice_pf *pf)\n+{\n+\tstruct ice_hw *hw = &pf->hw;\n+\tint tmp, i;\n+\n+\tif (!pf->vf)\n+\t\treturn;\n+\n+\twhile (test_and_set_bit(__ICE_VF_DIS, pf->state))\n+\t\tusleep_range(1000, 2000);\n+\n+\t/* Avoid wait time by stopping all VFs at the same time */\n+\tfor (i = 0; i < pf->num_alloc_vfs; i++) {\n+\t\tif (!test_bit(ICE_VF_STATE_ENA, pf->vf[i].vf_states))\n+\t\t\tcontinue;\n+\n+\t\t/* stop rings without wait time */\n+\t\tice_vsi_stop_tx_rings(pf->vsi[pf->vf[i].lan_vsi_idx],\n+\t\t\t\t ICE_NO_RESET, i);\n+\t\tice_vsi_stop_rx_rings(pf->vsi[pf->vf[i].lan_vsi_idx]);\n+\n+\t\tclear_bit(ICE_VF_STATE_ENA, pf->vf[i].vf_states);\n+\t}\n+\n+\t/* Disable IOV before freeing resources. This lets any VF drivers\n+\t * running in the host get themselves cleaned up before we yank\n+\t * the carpet out from underneath their feet.\n+\t */\n+\tif (!pci_vfs_assigned(pf->pdev))\n+\t\tpci_disable_sriov(pf->pdev);\n+\telse\n+\t\tdev_warn(&pf->pdev->dev, \"VFs are assigned - not disabling SR-IOV\\n\");\n+\n+\ttmp = pf->num_alloc_vfs;\n+\tpf->num_vf_qps = 0;\n+\tpf->num_alloc_vfs = 0;\n+\tfor (i = 0; i < tmp; i++) {\n+\t\tif (test_bit(ICE_VF_STATE_INIT, pf->vf[i].vf_states)) {\n+\t\t\t/* disable VF qp mappings */\n+\t\t\tice_dis_vf_mappings(&pf->vf[i]);\n+\n+\t\t\t/* Set this state so that assigned VF vectors can be\n+\t\t\t * reclaimed by PF for reuse in ice_vsi_release(). No\n+\t\t\t * need to clear this bit since pf->vf array is being\n+\t\t\t * freed anyways after this for loop\n+\t\t\t */\n+\t\t\tset_bit(ICE_VF_STATE_CFG_INTR, pf->vf[i].vf_states);\n+\t\t\tice_free_vf_res(&pf->vf[i]);\n+\t\t}\n+\t}\n+\n+\tdevm_kfree(&pf->pdev->dev, pf->vf);\n+\tpf->vf = NULL;\n+\n+\t/* This check is for when the driver is unloaded while VFs are\n+\t * assigned. Setting the number of VFs to 0 through sysfs is caught\n+\t * before this function ever gets called.\n+\t */\n+\tif (!pci_vfs_assigned(pf->pdev)) {\n+\t\tint vf_id;\n+\n+\t\t/* Acknowledge VFLR for all VFs. Without this, VFs will fail to\n+\t\t * work correctly when SR-IOV gets re-enabled.\n+\t\t */\n+\t\tfor (vf_id = 0; vf_id < tmp; vf_id++) {\n+\t\t\tu32 reg_idx, bit_idx;\n+\n+\t\t\treg_idx = (hw->func_caps.vf_base_id + vf_id) / 32;\n+\t\t\tbit_idx = (hw->func_caps.vf_base_id + vf_id) % 32;\n+\t\t\twr32(hw, GLGEN_VFLRSTAT(reg_idx), BIT(bit_idx));\n+\t\t}\n+\t}\n+\tclear_bit(__ICE_VF_DIS, pf->state);\n+\tclear_bit(ICE_FLAG_SRIOV_ENA, pf->flags);\n+}\n+\n+/**\n+ * ice_trigger_vf_reset - Reset a VF on HW\n+ * @vf: pointer to the VF structure\n+ * @is_vflr: true if VFLR was issued, false if not\n+ *\n+ * Trigger hardware to start a reset for a particular VF. Expects the caller\n+ * to wait the proper amount of time to allow hardware to reset the VF before\n+ * it cleans up and restores VF functionality.\n+ */\n+static void ice_trigger_vf_reset(struct ice_vf *vf, bool is_vflr)\n+{\n+\tstruct ice_pf *pf = vf->pf;\n+\tu32 reg, reg_idx, bit_idx;\n+\tstruct ice_hw *hw;\n+\tint vf_abs_id, i;\n+\n+\thw = &pf->hw;\n+\tvf_abs_id = vf->vf_id + hw->func_caps.vf_base_id;\n+\n+\t/* Inform VF that it is no longer active, as a warning */\n+\tclear_bit(ICE_VF_STATE_ACTIVE, vf->vf_states);\n+\n+\t/* Disable VF's configuration API during reset. The flag is re-enabled\n+\t * in ice_alloc_vf_res(), when it's safe again to access VF's VSI.\n+\t * It's normally disabled in ice_free_vf_res(), but it's safer\n+\t * to do it earlier to give some time to finish to any VF config\n+\t * functions that may still be running at this point.\n+\t */\n+\tclear_bit(ICE_VF_STATE_INIT, vf->vf_states);\n+\n+\t/* In the case of a VFLR, the HW has already reset the VF and we\n+\t * just need to clean up, so don't hit the VFRTRIG register.\n+\t */\n+\tif (!is_vflr) {\n+\t\t/* reset VF using VPGEN_VFRTRIG reg */\n+\t\treg = rd32(hw, VPGEN_VFRTRIG(vf->vf_id));\n+\t\treg |= VPGEN_VFRTRIG_VFSWR_M;\n+\t\twr32(hw, VPGEN_VFRTRIG(vf->vf_id), reg);\n+\t}\n+\t/* clear the VFLR bit in GLGEN_VFLRSTAT */\n+\treg_idx = (vf_abs_id) / 32;\n+\tbit_idx = (vf_abs_id) % 32;\n+\twr32(hw, GLGEN_VFLRSTAT(reg_idx), BIT(bit_idx));\n+\tice_flush(hw);\n+\n+\twr32(hw, PF_PCI_CIAA,\n+\t VF_DEVICE_STATUS | (vf_abs_id << PF_PCI_CIAA_VF_NUM_S));\n+\tfor (i = 0; i < 100; i++) {\n+\t\treg = rd32(hw, PF_PCI_CIAD);\n+\t\tif ((reg & VF_TRANS_PENDING_M) != 0)\n+\t\t\tdev_err(&pf->pdev->dev,\n+\t\t\t\t\"VF %d PCI transactions stuck\\n\", vf->vf_id);\n+\t\tudelay(1);\n+\t}\n+}\n+\n+/**\n+ * ice_vsi_set_pvid - Set port VLAN id for the VSI\n+ * @vsi: the VSI being changed\n+ * @vid: the VLAN id to set as a PVID\n+ */\n+static int ice_vsi_set_pvid(struct ice_vsi *vsi, u16 vid)\n+{\n+\tstruct device *dev = &vsi->back->pdev->dev;\n+\tstruct ice_hw *hw = &vsi->back->hw;\n+\tstruct ice_vsi_ctx ctxt = { 0 };\n+\tenum ice_status status;\n+\n+\tctxt.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_TAGGED |\n+\t\t\t ICE_AQ_VSI_PVLAN_INSERT_PVID |\n+\t\t\t ICE_AQ_VSI_VLAN_EMOD_STR;\n+\tctxt.info.pvid = cpu_to_le16(vid);\n+\tctxt.info.valid_sections = cpu_to_le16(ICE_AQ_VSI_PROP_VLAN_VALID);\n+\n+\tstatus = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);\n+\tif (status) {\n+\t\tdev_info(dev, \"update VSI for VLAN insert failed, err %d aq_err %d\\n\",\n+\t\t\t status, hw->adminq.sq_last_status);\n+\t\treturn -EIO;\n+\t}\n+\n+\tvsi->info.pvid = ctxt.info.pvid;\n+\tvsi->info.vlan_flags = ctxt.info.vlan_flags;\n+\treturn 0;\n+}\n+\n+/**\n+ * ice_vf_vsi_setup - Set up a VF VSI\n+ * @pf: board private structure\n+ * @pi: pointer to the port_info instance\n+ * @vf_id: defines VF id to which this VSI connects.\n+ *\n+ * Returns pointer to the successfully allocated VSI struct on success,\n+ * otherwise returns NULL on failure.\n+ */\n+static struct ice_vsi *\n+ice_vf_vsi_setup(struct ice_pf *pf, struct ice_port_info *pi, u16 vf_id)\n+{\n+\treturn ice_vsi_setup(pf, pi, ICE_VSI_VF, vf_id);\n+}\n+\n+/**\n+ * ice_alloc_vsi_res - Setup VF VSI and its resources\n+ * @vf: pointer to the VF structure\n+ *\n+ * Returns 0 on success, negative value on failure\n+ */\n+static int ice_alloc_vsi_res(struct ice_vf *vf)\n+{\n+\tstruct ice_pf *pf = vf->pf;\n+\tLIST_HEAD(tmp_add_list);\n+\tu8 broadcast[ETH_ALEN];\n+\tstruct ice_vsi *vsi;\n+\tint status = 0;\n+\n+\tvsi = ice_vf_vsi_setup(pf, pf->hw.port_info, vf->vf_id);\n+\n+\tif (!vsi) {\n+\t\tdev_err(&pf->pdev->dev, \"Failed to create VF VSI\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tvf->lan_vsi_idx = vsi->idx;\n+\tvf->lan_vsi_num = vsi->vsi_num;\n+\n+\t/* first vector index is the VFs OICR index */\n+\tvf->first_vector_idx = vsi->hw_base_vector;\n+\t/* Since hw_base_vector holds the vector where data queue interrupts\n+\t * starts, increment by 1 since VFs allocated vectors include OICR intr\n+\t * as well.\n+\t */\n+\tvsi->hw_base_vector += 1;\n+\n+\t/* Check if port VLAN exist before, and restore it accordingly */\n+\tif (vf->port_vlan_id)\n+\t\tice_vsi_set_pvid(vsi, vf->port_vlan_id);\n+\n+\teth_broadcast_addr(broadcast);\n+\n+\tstatus = ice_add_mac_to_list(vsi, &tmp_add_list, broadcast);\n+\tif (status)\n+\t\tgoto ice_alloc_vsi_res_exit;\n+\n+\tif (is_valid_ether_addr(vf->dflt_lan_addr.addr)) {\n+\t\tstatus = ice_add_mac_to_list(vsi, &tmp_add_list,\n+\t\t\t\t\t vf->dflt_lan_addr.addr);\n+\t\tif (status)\n+\t\t\tgoto ice_alloc_vsi_res_exit;\n+\t}\n+\n+\tstatus = ice_add_mac(&pf->hw, &tmp_add_list);\n+\tif (status)\n+\t\tdev_err(&pf->pdev->dev, \"could not add mac filters\\n\");\n+\n+\t/* Clear this bit after VF initialization since we shouldn't reclaim\n+\t * and reassign interrupts for synchronous or asynchronous VFR events.\n+\t * We dont want to reconfigure interrupts since AVF driver doesn't\n+\t * expect vector assignment to be changed unless there is a request for\n+\t * more vectors.\n+\t */\n+\tclear_bit(ICE_VF_STATE_CFG_INTR, vf->vf_states);\n+ice_alloc_vsi_res_exit:\n+\tice_free_fltr_list(&pf->pdev->dev, &tmp_add_list);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_alloc_vf_res - Allocate VF resources\n+ * @vf: pointer to the VF structure\n+ */\n+static int ice_alloc_vf_res(struct ice_vf *vf)\n+{\n+\tint status;\n+\n+\t/* setup VF VSI and necessary resources */\n+\tstatus = ice_alloc_vsi_res(vf);\n+\tif (status)\n+\t\tgoto ice_alloc_vf_res_exit;\n+\n+\tif (vf->trusted)\n+\t\tset_bit(ICE_VIRTCHNL_VF_CAP_PRIVILEGE, &vf->vf_caps);\n+\telse\n+\t\tclear_bit(ICE_VIRTCHNL_VF_CAP_PRIVILEGE, &vf->vf_caps);\n+\n+\t/* VF is now completely initialized */\n+\tset_bit(ICE_VF_STATE_INIT, vf->vf_states);\n+\n+\treturn status;\n+\n+ice_alloc_vf_res_exit:\n+\tice_free_vf_res(vf);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_ena_vf_mappings\n+ * @vf: pointer to the VF structure\n+ *\n+ * Enable VF vectors and queues allocation by writing the details into\n+ * respective registers.\n+ */\n+static void ice_ena_vf_mappings(struct ice_vf *vf)\n+{\n+\tstruct ice_pf *pf = vf->pf;\n+\tstruct ice_vsi *vsi;\n+\tint first, last, v;\n+\tstruct ice_hw *hw;\n+\tint abs_vf_id;\n+\tu32 reg;\n+\n+\thw = &pf->hw;\n+\tvsi = pf->vsi[vf->lan_vsi_idx];\n+\tfirst = vf->first_vector_idx;\n+\tlast = (first + pf->num_vf_msix) - 1;\n+\tabs_vf_id = vf->vf_id + hw->func_caps.vf_base_id;\n+\n+\t/* VF Vector allocation */\n+\treg = (((first << VPINT_ALLOC_FIRST_S) & VPINT_ALLOC_FIRST_M) |\n+\t ((last << VPINT_ALLOC_LAST_S) & VPINT_ALLOC_LAST_M) |\n+\t VPINT_ALLOC_VALID_M);\n+\twr32(hw, VPINT_ALLOC(vf->vf_id), reg);\n+\n+\t/* map the interrupts to its functions */\n+\tfor (v = first; v <= last; v++) {\n+\t\treg = (((abs_vf_id << GLINT_VECT2FUNC_VF_NUM_S) &\n+\t\t\tGLINT_VECT2FUNC_VF_NUM_M) |\n+\t\t ((hw->pf_id << GLINT_VECT2FUNC_PF_NUM_S) &\n+\t\t\tGLINT_VECT2FUNC_PF_NUM_M));\n+\t\twr32(hw, GLINT_VECT2FUNC(v), reg);\n+\t}\n+\n+\t/* VF Tx queues allocation */\n+\tif (vsi->tx_mapping_mode == ICE_VSI_MAP_CONTIG) {\n+\t\twr32(hw, VPLAN_TXQ_MAPENA(vf->vf_id),\n+\t\t VPLAN_TXQ_MAPENA_TX_ENA_M);\n+\t\t/* set the VF PF Tx queue range\n+\t\t * VFNUMQ value should be set to (number of queues - 1). A value\n+\t\t * of 0 means 1 queue and a value of 255 means 256 queues\n+\t\t */\n+\t\treg = (((vsi->txq_map[0] << VPLAN_TX_QBASE_VFFIRSTQ_S) &\n+\t\t\tVPLAN_TX_QBASE_VFFIRSTQ_M) |\n+\t\t (((vsi->alloc_txq - 1) << VPLAN_TX_QBASE_VFNUMQ_S) &\n+\t\t\tVPLAN_TX_QBASE_VFNUMQ_M));\n+\t\twr32(hw, VPLAN_TX_QBASE(vf->vf_id), reg);\n+\t} else {\n+\t\tdev_err(&pf->pdev->dev,\n+\t\t\t\"Scattered mode for VF Tx queues is not yet implemented\\n\");\n+\t}\n+\n+\t/* VF Rx queues allocation */\n+\tif (vsi->rx_mapping_mode == ICE_VSI_MAP_CONTIG) {\n+\t\twr32(hw, VPLAN_RXQ_MAPENA(vf->vf_id),\n+\t\t VPLAN_RXQ_MAPENA_RX_ENA_M);\n+\t\t/* set the VF PF Rx queue range\n+\t\t * VFNUMQ value should be set to (number of queues - 1). A value\n+\t\t * of 0 means 1 queue and a value of 255 means 256 queues\n+\t\t */\n+\t\treg = (((vsi->rxq_map[0] << VPLAN_RX_QBASE_VFFIRSTQ_S) &\n+\t\t\tVPLAN_RX_QBASE_VFFIRSTQ_M) |\n+\t\t (((vsi->alloc_txq - 1) << VPLAN_RX_QBASE_VFNUMQ_S) &\n+\t\t\tVPLAN_RX_QBASE_VFNUMQ_M));\n+\t\twr32(hw, VPLAN_RX_QBASE(vf->vf_id), reg);\n+\t} else {\n+\t\tdev_err(&pf->pdev->dev,\n+\t\t\t\"Scattered mode for VF Rx queues is not yet implemented\\n\");\n+\t}\n+}\n+\n+/**\n+ * ice_determine_res\n+ * @pf: pointer to the PF structure\n+ * @avail_res: available resources in the PF structure\n+ * @max_res: maximum resources that can be given per VF\n+ * @min_res: minimum resources that can be given per VF\n+ *\n+ * Returns non-zero value if resources (queues/vectors) are available or\n+ * returns zero if PF cannot accommodate for all num_alloc_vfs.\n+ */\n+static int\n+ice_determine_res(struct ice_pf *pf, u16 avail_res, u16 max_res, u16 min_res)\n+{\n+\tbool checked_min_res = false;\n+\tint res;\n+\n+\t/* start by checking if PF can assign max number of resources for\n+\t * all num_alloc_vfs.\n+\t * if yes, return number per VF\n+\t * If no, divide by 2 and roundup, check again\n+\t * repeat the loop till we reach a point where even minimum resources\n+\t * are not available, in that case return 0\n+\t */\n+\tres = max_res;\n+\twhile ((res >= min_res) && !checked_min_res) {\n+\t\tint num_all_res;\n+\n+\t\tnum_all_res = pf->num_alloc_vfs * res;\n+\t\tif (num_all_res <= avail_res)\n+\t\t\treturn res;\n+\n+\t\tif (res == min_res)\n+\t\t\tchecked_min_res = true;\n+\n+\t\tres = DIV_ROUND_UP(res, 2);\n+\t}\n+\treturn 0;\n+}\n+\n+/**\n+ * ice_check_avail_res - check if vectors and queues are available\n+ * @pf: pointer to the PF structure\n+ *\n+ * This function is where we calculate actual number of resources for VF VSIs,\n+ * we don't reserve ahead of time during probe. Returns success if vectors and\n+ * queues resources are available, otherwise returns error code\n+ */\n+static int ice_check_avail_res(struct ice_pf *pf)\n+{\n+\tu16 num_msix, num_txq, num_rxq;\n+\n+\tif (!pf->num_alloc_vfs)\n+\t\treturn -EINVAL;\n+\n+\t/* Grab from HW interrupts common pool\n+\t * Note: By the time the user decides it needs more vectors in a VF\n+\t * its already too late since one must decide this prior to creating the\n+\t * VF interface. So the best we can do is take a guess as to what the\n+\t * user might want.\n+\t *\n+\t * We have two policies for vector allocation:\n+\t * 1. if num_alloc_vfs is from 1 to 16, then we consider this as small\n+\t * number of NFV VFs used for NFV appliances, since this is a special\n+\t * case, we try to assign maximum vectors per VF (65) as much as\n+\t * possible, based on determine_resources algorithm.\n+\t * 2. if num_alloc_vfs is from 17 to 256, then its large number of\n+\t * regular VFs which are not used for any special purpose. Hence try to\n+\t * grab default interrupt vectors (5 as supported by AVF driver).\n+\t */\n+\tif (pf->num_alloc_vfs <= 16) {\n+\t\tnum_msix = ice_determine_res(pf, pf->num_avail_hw_msix,\n+\t\t\t\t\t ICE_MAX_INTR_PER_VF,\n+\t\t\t\t\t ICE_MIN_INTR_PER_VF);\n+\t} else if (pf->num_alloc_vfs <= ICE_MAX_VF_COUNT) {\n+\t\tnum_msix = ice_determine_res(pf, pf->num_avail_hw_msix,\n+\t\t\t\t\t ICE_DFLT_INTR_PER_VF,\n+\t\t\t\t\t ICE_MIN_INTR_PER_VF);\n+\t} else {\n+\t\tdev_err(&pf->pdev->dev,\n+\t\t\t\"Number of VFs %d exceeds max VF count %d\\n\",\n+\t\t\tpf->num_alloc_vfs, ICE_MAX_VF_COUNT);\n+\t\treturn -EIO;\n+\t}\n+\n+\tif (!num_msix)\n+\t\treturn -EIO;\n+\n+\t/* Grab from the common pool\n+\t * start by requesting Default queues (4 as supported by AVF driver),\n+\t * Note that, the main difference between queues and vectors is, latter\n+\t * can only be reserved at init time but queues can be requested by VF\n+\t * at runtime through Virtchnl, that is the reason we start by reserving\n+\t * few queues.\n+\t */\n+\tnum_txq = ice_determine_res(pf, pf->q_left_tx, ICE_DFLT_QS_PER_VF,\n+\t\t\t\t ICE_MIN_QS_PER_VF);\n+\n+\tnum_rxq = ice_determine_res(pf, pf->q_left_rx, ICE_DFLT_QS_PER_VF,\n+\t\t\t\t ICE_MIN_QS_PER_VF);\n+\n+\tif (!num_txq || !num_rxq)\n+\t\treturn -EIO;\n+\n+\t/* since AVF driver works with only queue pairs which means, it expects\n+\t * to have equal number of Rx and Tx queues, so take the minimum of\n+\t * available Tx or Rx queues\n+\t */\n+\tpf->num_vf_qps = min_t(int, num_txq, num_rxq);\n+\tpf->num_vf_msix = num_msix;\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * ice_cleanup_and_realloc_vf - Clean up VF and reallocate resources after reset\n+ * @vf: pointer to the VF structure\n+ *\n+ * Cleanup a VF after the hardware reset is finished. Expects the caller to\n+ * have verified whether the reset is finished properly, and ensure the\n+ * minimum amount of wait time has passed. Reallocate VF resources back to make\n+ * VF state active\n+ */\n+static void ice_cleanup_and_realloc_vf(struct ice_vf *vf)\n+{\n+\tstruct ice_pf *pf = vf->pf;\n+\tstruct ice_hw *hw;\n+\tu32 reg;\n+\n+\thw = &pf->hw;\n+\n+\t/* PF software completes the flow by notifying VF that reset flow is\n+\t * completed. This is done by enabling hardware by clearing the reset\n+\t * bit in the VPGEN_VFRTRIG reg and setting VFR_STATE in the VFGEN_RSTAT\n+\t * register to VFR completed (done at the end of this function)\n+\t * By doing this we allow HW to access VF memory at any point. If we\n+\t * did it any sooner, HW could access memory while it was being freed\n+\t * in ice_free_vf_res(), causing an IOMMU fault.\n+\t *\n+\t * On the other hand, this needs to be done ASAP, because the VF driver\n+\t * is waiting for this to happen and may report a timeout. It's\n+\t * harmless, but it gets logged into Guest OS kernel log, so best avoid\n+\t * it.\n+\t */\n+\treg = rd32(hw, VPGEN_VFRTRIG(vf->vf_id));\n+\treg &= ~VPGEN_VFRTRIG_VFSWR_M;\n+\twr32(hw, VPGEN_VFRTRIG(vf->vf_id), reg);\n+\n+\t/* reallocate VF resources to finish resetting the VSI state */\n+\tif (!ice_alloc_vf_res(vf)) {\n+\t\tice_ena_vf_mappings(vf);\n+\t\tset_bit(ICE_VF_STATE_ACTIVE, vf->vf_states);\n+\t\tclear_bit(ICE_VF_STATE_DIS, vf->vf_states);\n+\t\tvf->num_vlan = 0;\n+\t}\n+\n+\t/* Tell the VF driver the reset is done. This needs to be done only\n+\t * after VF has been fully initialized, because the VF driver may\n+\t * request resources immediately after setting this flag.\n+\t */\n+\twr32(hw, VFGEN_RSTAT(vf->vf_id), VIRTCHNL_VFR_VFACTIVE);\n+}\n+\n+/**\n+ * ice_reset_all_vfs - reset all allocated VFs in one go\n+ * @pf: pointer to the PF structure\n+ * @is_vflr: true if VFLR was issued, false if not\n+ *\n+ * First, tell the hardware to reset each VF, then do all the waiting in one\n+ * chunk, and finally finish restoring each VF after the wait. This is useful\n+ * during PF routines which need to reset all VFs, as otherwise it must perform\n+ * these resets in a serialized fashion.\n+ *\n+ * Returns true if any VFs were reset, and false otherwise.\n+ */\n+bool ice_reset_all_vfs(struct ice_pf *pf, bool is_vflr)\n+{\n+\tstruct ice_hw *hw = &pf->hw;\n+\tint v, i;\n+\n+\t/* If we don't have any VFs, then there is nothing to reset */\n+\tif (!pf->num_alloc_vfs)\n+\t\treturn false;\n+\n+\t/* If VFs have been disabled, there is no need to reset */\n+\tif (test_and_set_bit(__ICE_VF_DIS, pf->state))\n+\t\treturn false;\n+\n+\t/* Begin reset on all VFs at once */\n+\tfor (v = 0; v < pf->num_alloc_vfs; v++)\n+\t\tice_trigger_vf_reset(&pf->vf[v], is_vflr);\n+\n+\t/* Call Disable LAN Tx queue AQ call with VFR bit set and 0\n+\t * queues to inform Firmware about VF reset.\n+\t */\n+\tfor (v = 0; v < pf->num_alloc_vfs; v++)\n+\t\tice_dis_vsi_txq(pf->vsi[0]->port_info, 0, NULL, NULL,\n+\t\t\t\tICE_VF_RESET, v, NULL);\n+\n+\t/* HW requires some time to make sure it can flush the FIFO for a VF\n+\t * when it resets it. Poll the VPGEN_VFRSTAT register for each VF in\n+\t * sequence to make sure that it has completed. We'll keep track of\n+\t * the VFs using a simple iterator that increments once that VF has\n+\t * finished resetting.\n+\t */\n+\tfor (i = 0, v = 0; i < 10 && v < pf->num_alloc_vfs; i++) {\n+\t\tusleep_range(10000, 20000);\n+\n+\t\t/* Check each VF in sequence */\n+\t\twhile (v < pf->num_alloc_vfs) {\n+\t\t\tstruct ice_vf *vf = &pf->vf[v];\n+\t\t\tu32 reg;\n+\n+\t\t\treg = rd32(hw, VPGEN_VFRSTAT(vf->vf_id));\n+\t\t\tif (!(reg & VPGEN_VFRSTAT_VFRD_M))\n+\t\t\t\tbreak;\n+\n+\t\t\t/* If the current VF has finished resetting, move on\n+\t\t\t * to the next VF in sequence.\n+\t\t\t */\n+\t\t\tv++;\n+\t\t}\n+\t}\n+\n+\t/* Display a warning if at least one VF didn't manage to reset in\n+\t * time, but continue on with the operation.\n+\t */\n+\tif (v < pf->num_alloc_vfs)\n+\t\tdev_warn(&pf->pdev->dev, \"VF reset check timeout\\n\");\n+\tusleep_range(10000, 20000);\n+\n+\t/* free VF resources to begin resetting the VSI state */\n+\tfor (v = 0; v < pf->num_alloc_vfs; v++)\n+\t\tice_free_vf_res(&pf->vf[v]);\n+\n+\tif (ice_check_avail_res(pf)) {\n+\t\tdev_err(&pf->pdev->dev,\n+\t\t\t\"Cannot allocate VF resources, try with fewer number of VFs\\n\");\n+\t\treturn false;\n+\t}\n+\n+\t/* Finish the reset on each VF */\n+\tfor (v = 0; v < pf->num_alloc_vfs; v++)\n+\t\tice_cleanup_and_realloc_vf(&pf->vf[v]);\n+\n+\tice_flush(hw);\n+\tclear_bit(__ICE_VF_DIS, pf->state);\n+\n+\treturn true;\n+}\n+\n+/**\n+ * ice_alloc_vfs - Allocate and set up VFs resources\n+ * @pf: pointer to the PF structure\n+ * @num_alloc_vfs: number of VFs to allocate\n+ */\n+static int ice_alloc_vfs(struct ice_pf *pf, u16 num_alloc_vfs)\n+{\n+\tstruct ice_hw *hw = &pf->hw;\n+\tstruct ice_vf *vfs;\n+\tint i, ret;\n+\n+\t/* Disable global interrupt 0 so we don't try to handle the VFLR. */\n+\twr32(hw, GLINT_DYN_CTL(pf->hw_oicr_idx),\n+\t ICE_ITR_NONE << GLINT_DYN_CTL_ITR_INDX_S);\n+\n+\tice_flush(hw);\n+\n+\tret = pci_enable_sriov(pf->pdev, num_alloc_vfs);\n+\tif (ret) {\n+\t\tpf->num_alloc_vfs = 0;\n+\t\tgoto err_unroll_intr;\n+\t}\n+\t/* allocate memory */\n+\tvfs = devm_kcalloc(&pf->pdev->dev, num_alloc_vfs, sizeof(*vfs),\n+\t\t\t GFP_KERNEL);\n+\tif (!vfs) {\n+\t\tret = -ENOMEM;\n+\t\tgoto err_unroll_sriov;\n+\t}\n+\tpf->vf = vfs;\n+\n+\t/* apply default profile */\n+\tfor (i = 0; i < num_alloc_vfs; i++) {\n+\t\tvfs[i].pf = pf;\n+\t\tvfs[i].vf_sw_id = pf->first_sw;\n+\t\tvfs[i].vf_id = i;\n+\n+\t\t/* assign default capabilities */\n+\t\tset_bit(ICE_VIRTCHNL_VF_CAP_L2, &vfs[i].vf_caps);\n+\t\tvfs[i].spoofchk = true;\n+\n+\t\t/* Set this state so that PF driver does VF vector assignment */\n+\t\tset_bit(ICE_VF_STATE_CFG_INTR, vfs[i].vf_states);\n+\t}\n+\tpf->num_alloc_vfs = num_alloc_vfs;\n+\n+\t/* VF resources get allocated during reset */\n+\tif (!ice_reset_all_vfs(pf, false))\n+\t\tgoto err_unroll_sriov;\n+\n+\tgoto err_unroll_intr;\n+\n+err_unroll_sriov:\n+\tpci_disable_sriov(pf->pdev);\n+err_unroll_intr:\n+\t/* rearm interrupts here */\n+\tice_irq_dynamic_ena(hw, NULL, NULL);\n+\treturn ret;\n+}\n+\n+/**\n+ * ice_pf_state_is_nominal - checks the pf for nominal state\n+ * @pf: pointer to pf to check\n+ *\n+ * Check the PF's state for a collection of bits that would indicate\n+ * the PF is in a state that would inhibit normal operation for\n+ * driver functionality.\n+ *\n+ * Returns true if PF is in a nominal state.\n+ * Returns false otherwise\n+ */\n+static bool ice_pf_state_is_nominal(struct ice_pf *pf)\n+{\n+\tDECLARE_BITMAP(check_bits, __ICE_STATE_NBITS) = { 0 };\n+\n+\tif (!pf)\n+\t\treturn false;\n+\n+\tbitmap_set(check_bits, 0, __ICE_STATE_NOMINAL_CHECK_BITS);\n+\tif (bitmap_intersects(pf->state, check_bits, __ICE_STATE_NBITS))\n+\t\treturn false;\n+\n+\treturn true;\n+}\n+\n+/**\n+ * ice_pci_sriov_ena - Enable or change number of VFs\n+ * @pf: pointer to the PF structure\n+ * @num_vfs: number of VFs to allocate\n+ */\n+static int ice_pci_sriov_ena(struct ice_pf *pf, int num_vfs)\n+{\n+\tint pre_existing_vfs = pci_num_vf(pf->pdev);\n+\tstruct device *dev = &pf->pdev->dev;\n+\tint err;\n+\n+\tif (!ice_pf_state_is_nominal(pf)) {\n+\t\tdev_err(dev, \"Cannot enable SR-IOV, device not ready\\n\");\n+\t\treturn -EBUSY;\n+\t}\n+\n+\tif (!test_bit(ICE_FLAG_SRIOV_CAPABLE, pf->flags)) {\n+\t\tdev_err(dev, \"This device is not capable of SR-IOV\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tif (pre_existing_vfs && pre_existing_vfs != num_vfs)\n+\t\tice_free_vfs(pf);\n+\telse if (pre_existing_vfs && pre_existing_vfs == num_vfs)\n+\t\treturn num_vfs;\n+\n+\tif (num_vfs > pf->num_vfs_supported) {\n+\t\tdev_err(dev, \"Can't enable %d VFs, max VFs supported is %d\\n\",\n+\t\t\tnum_vfs, pf->num_vfs_supported);\n+\t\treturn -ENOTSUPP;\n+\t}\n+\n+\tdev_info(dev, \"Allocating %d VFs\\n\", num_vfs);\n+\terr = ice_alloc_vfs(pf, num_vfs);\n+\tif (err) {\n+\t\tdev_err(dev, \"Failed to enable SR-IOV: %d\\n\", err);\n+\t\treturn err;\n+\t}\n+\n+\tset_bit(ICE_FLAG_SRIOV_ENA, pf->flags);\n+\treturn num_vfs;\n+}\n+\n+/**\n+ * ice_sriov_configure - Enable or change number of VFs via sysfs\n+ * @pdev: pointer to a pci_dev structure\n+ * @num_vfs: number of vfs to allocate\n+ *\n+ * This function is called when the user updates the number of VFs in sysfs.\n+ */\n+int ice_sriov_configure(struct pci_dev *pdev, int num_vfs)\n+{\n+\tstruct ice_pf *pf = pci_get_drvdata(pdev);\n+\n+\tif (num_vfs)\n+\t\treturn ice_pci_sriov_ena(pf, num_vfs);\n+\n+\tif (!pci_vfs_assigned(pdev)) {\n+\t\tice_free_vfs(pf);\n+\t} else {\n+\t\tdev_err(&pf->pdev->dev,\n+\t\t\t\"can't free VFs because some are assigned to VMs.\\n\");\n+\t\treturn -EBUSY;\n+\t}\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/net/ethernet/intel/ice/ice_virtchnl_pf.h b/drivers/net/ethernet/intel/ice/ice_virtchnl_pf.h\nnew file mode 100644\nindex 000000000000..3d5344d12efb\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/ice/ice_virtchnl_pf.h\n@@ -0,0 +1,74 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/* Copyright (c) 2018, Intel Corporation. */\n+\n+#ifndef _ICE_VIRTCHNL_PF_H_\n+#define _ICE_VIRTCHNL_PF_H_\n+#include \"ice.h\"\n+\n+/* Static VF transaction/status register def */\n+#define VF_DEVICE_STATUS\t\t0xAA\n+#define VF_TRANS_PENDING_M\t\t0x20\n+\n+/* Specific VF states */\n+enum ice_vf_states {\n+\tICE_VF_STATE_INIT = 0,\n+\tICE_VF_STATE_ACTIVE,\n+\tICE_VF_STATE_ENA,\n+\tICE_VF_STATE_DIS,\n+\tICE_VF_STATE_MC_PROMISC,\n+\tICE_VF_STATE_UC_PROMISC,\n+\t/* state to indicate if PF needs to do vector assignment for VF.\n+\t * This needs to be set during first time VF initialization or later\n+\t * when VF asks for more Vectors through virtchnl OP.\n+\t */\n+\tICE_VF_STATE_CFG_INTR,\n+\tICE_VF_STATES_NBITS\n+};\n+\n+/* VF capabilities */\n+enum ice_virtchnl_cap {\n+\tICE_VIRTCHNL_VF_CAP_L2 = 0,\n+\tICE_VIRTCHNL_VF_CAP_PRIVILEGE,\n+};\n+\n+/* VF information structure */\n+struct ice_vf {\n+\tstruct ice_pf *pf;\n+\n+\ts16 vf_id;\t\t\t/* VF id in the PF space */\n+\tint first_vector_idx;\t\t/* first vector index of this VF */\n+\tstruct ice_sw *vf_sw_id;\t/* switch id the VF VSIs connect to */\n+\tstruct virtchnl_ether_addr dflt_lan_addr;\n+\tu16 port_vlan_id;\n+\tu8 trusted;\n+\tu16 lan_vsi_idx;\t\t/* index into PF struct */\n+\tu16 lan_vsi_num;\t\t/* ID as used by firmware */\n+\tunsigned long vf_caps;\t\t/* vf's adv. capabilities */\n+\tDECLARE_BITMAP(vf_states, ICE_VF_STATES_NBITS);\t/* vf runtime states */\n+\tu8 spoofchk;\n+\tu16 num_mac;\n+\tu16 num_vlan;\n+};\n+\n+#ifdef CONFIG_PCI_IOV\n+int ice_sriov_configure(struct pci_dev *pdev, int num_vfs);\n+void ice_free_vfs(struct ice_pf *pf);\n+bool ice_reset_all_vfs(struct ice_pf *pf, bool is_vflr);\n+#else /* CONFIG_PCI_IOV */\n+#define ice_free_vfs(pf) do {} while (0)\n+\n+static inline bool\n+ice_reset_all_vfs(struct ice_pf __always_unused *pf,\n+\t\t bool __always_unused is_vflr)\n+{\n+\treturn true;\n+}\n+\n+static inline int\n+ice_sriov_configure(struct pci_dev __always_unused *pdev,\n+\t\t int __always_unused num_vfs)\n+{\n+\treturn -EOPNOTSUPP;\n+}\n+#endif /* CONFIG_PCI_IOV */\n+#endif /* _ICE_VIRTCHNL_PF_H_ */\n", "prefixes": [ "v2", "03/16" ] }