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GET /api/patches/972077/?format=api
{ "id": 972077, "url": "http://patchwork.ozlabs.org/api/patches/972077/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20180920004308.13772-5-anirudh.venkataramanan@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20180920004308.13772-5-anirudh.venkataramanan@intel.com>", "list_archive_url": null, "date": "2018-09-20T00:42:56", "name": "[v2,04/16] ice: Update VSI and queue management code to handle VF VSI", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "12a9b6662ee5dc329f59cd45b4b0912e71d5834a", "submitter": { "id": 73601, "url": "http://patchwork.ozlabs.org/api/people/73601/?format=api", "name": "Anirudh Venkataramanan", "email": "anirudh.venkataramanan@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20180920004308.13772-5-anirudh.venkataramanan@intel.com/mbox/", "series": [ { "id": 66527, "url": "http://patchwork.ozlabs.org/api/series/66527/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=66527", "date": "2018-09-20T00:42:53", "name": "Add SR-IOV support, feature updates", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/66527/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/972077/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/972077/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.136; helo=silver.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 42FydZ31QDz9sBW\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 20 Sep 2018 10:43:30 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id CBF2B302BD;\n\tThu, 20 Sep 2018 00:43:28 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 0rH4yyTSxZF5; Thu, 20 Sep 2018 00:43:21 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby silver.osuosl.org (Postfix) with ESMTP id F132330949;\n\tThu, 20 Sep 2018 00:43:19 +0000 (UTC)", "from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\tby ash.osuosl.org (Postfix) with ESMTP id 9D4AA1C08AF\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 20 Sep 2018 00:43:12 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 91D5D876F7\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 20 Sep 2018 00:43:12 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id SQmgWPuvk3Yn for <intel-wired-lan@lists.osuosl.org>;\n\tThu, 20 Sep 2018 00:43:10 +0000 (UTC)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n\tby fraxinus.osuosl.org (Postfix) with ESMTPS id 028B98755F\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 20 Sep 2018 00:43:09 +0000 (UTC)", "from orsmga004.jf.intel.com ([10.7.209.38])\n\tby fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t19 Sep 2018 17:43:09 -0700", "from shasta.jf.intel.com ([10.166.241.11])\n\tby orsmga004.jf.intel.com with ESMTP; 19 Sep 2018 17:43:08 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.53,396,1531810800\"; d=\"scan'208\";a=\"234371594\"", "From": "Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Wed, 19 Sep 2018 17:42:56 -0700", "Message-Id": "<20180920004308.13772-5-anirudh.venkataramanan@intel.com>", "X-Mailer": "git-send-email 2.14.3", "In-Reply-To": "<20180920004308.13772-1-anirudh.venkataramanan@intel.com>", "References": "<20180920004308.13772-1-anirudh.venkataramanan@intel.com>", "Subject": "[Intel-wired-lan] [PATCH v2 04/16] ice: Update VSI and queue\n\tmanagement code to handle VF VSI", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.24", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "Until now, all the VSI and queue management code supported only the PF\nVSI type (ICE_VSI_PF). Update these flows to handle the VF VSI type\n(ICE_VSI_VF) type as well.\n\nSigned-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>\n---\n drivers/net/ethernet/intel/ice/ice.h | 2 +\n drivers/net/ethernet/intel/ice/ice_hw_autogen.h | 1 +\n drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h | 1 +\n drivers/net/ethernet/intel/ice/ice_lib.c | 211 ++++++++++++++++++++----\n drivers/net/ethernet/intel/ice/ice_switch.h | 1 +\n drivers/net/ethernet/intel/ice/ice_type.h | 3 +\n 6 files changed, 184 insertions(+), 35 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/ice/ice.h b/drivers/net/ethernet/intel/ice/ice.h\nindex 89e6112bc819..f97a23930cab 100644\n--- a/drivers/net/ethernet/intel/ice/ice.h\n+++ b/drivers/net/ethernet/intel/ice/ice.h\n@@ -202,6 +202,8 @@ struct ice_vsi {\n \t/* Interrupt thresholds */\n \tu16 work_lmt;\n \n+\ts16 vf_id;\t\t\t /* VF ID for SR-IOV VSIs */\n+\n \t/* RSS config */\n \tu16 rss_table_size;\t/* HW RSS table size */\n \tu16 rss_size;\t\t/* Allocated RSS queues */\ndiff --git a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h\nindex b676b3151d04..12d4c862bf05 100644\n--- a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h\n+++ b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h\n@@ -312,6 +312,7 @@\n #define GLV_UPTCH(_i)\t\t\t\t(0x0030A004 + ((_i) * 8))\n #define GLV_UPTCL(_i)\t\t\t\t(0x0030A000 + ((_i) * 8))\n #define VSIQF_HKEY_MAX_INDEX\t\t\t12\n+#define VSIQF_HLUT_MAX_INDEX\t\t\t15\n #define VFINT_DYN_CTLN(_i)\t\t\t(0x00003800 + ((_i) * 4))\n #define VFINT_DYN_CTLN_CLEARPBA_M\t\tBIT(1)\n \ndiff --git a/drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h b/drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h\nindex 94504023d86e..f5269f780e1c 100644\n--- a/drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h\n+++ b/drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h\n@@ -418,6 +418,7 @@ struct ice_tlan_ctx {\n \tu8 pf_num;\n \tu16 vmvf_num;\n \tu8 vmvf_type;\n+#define ICE_TLAN_CTX_VMVF_TYPE_VF\t0\n #define ICE_TLAN_CTX_VMVF_TYPE_VMQ\t1\n #define ICE_TLAN_CTX_VMVF_TYPE_PF\t2\n \tu16 src_vsi;\ndiff --git a/drivers/net/ethernet/intel/ice/ice_lib.c b/drivers/net/ethernet/intel/ice/ice_lib.c\nindex 45459c6a0d24..0dbf3245a9d9 100644\n--- a/drivers/net/ethernet/intel/ice/ice_lib.c\n+++ b/drivers/net/ethernet/intel/ice/ice_lib.c\n@@ -68,18 +68,20 @@ static int ice_setup_rx_ctx(struct ice_ring *ring)\n \t /* Enable Flexible Descriptors in the queue context which\n \t * allows this driver to select a specific receive descriptor format\n \t */\n-\tregval = rd32(hw, QRXFLXP_CNTXT(pf_q));\n-\tregval |= (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &\n-\t\tQRXFLXP_CNTXT_RXDID_IDX_M;\n-\n-\t/* increasing context priority to pick up profile id;\n-\t * default is 0x01; setting to 0x03 to ensure profile\n-\t * is programming if prev context is of same priority\n-\t */\n-\tregval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &\n-\t\tQRXFLXP_CNTXT_RXDID_PRIO_M;\n+\tif (vsi->type != ICE_VSI_VF) {\n+\t\tregval = rd32(hw, QRXFLXP_CNTXT(pf_q));\n+\t\tregval |= (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &\n+\t\t\tQRXFLXP_CNTXT_RXDID_IDX_M;\n+\n+\t\t/* increasing context priority to pick up profile id;\n+\t\t * default is 0x01; setting to 0x03 to ensure profile\n+\t\t * is programming if prev context is of same priority\n+\t\t */\n+\t\tregval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &\n+\t\t\tQRXFLXP_CNTXT_RXDID_PRIO_M;\n \n-\twr32(hw, QRXFLXP_CNTXT(pf_q), regval);\n+\t\twr32(hw, QRXFLXP_CNTXT(pf_q), regval);\n+\t}\n \n \t/* Absolute queue number out of 2K needs to be passed */\n \terr = ice_write_rxq_ctx(hw, &rlan_ctx, pf_q);\n@@ -90,6 +92,9 @@ static int ice_setup_rx_ctx(struct ice_ring *ring)\n \t\treturn -EIO;\n \t}\n \n+\tif (vsi->type == ICE_VSI_VF)\n+\t\treturn 0;\n+\n \t/* init queue specific tail register */\n \tring->tail = hw->hw_addr + QRX_TAIL(pf_q);\n \twritel(0, ring->tail);\n@@ -132,6 +137,11 @@ ice_setup_tx_ctx(struct ice_ring *ring, struct ice_tlan_ctx *tlan_ctx, u16 pf_q)\n \tcase ICE_VSI_PF:\n \t\ttlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;\n \t\tbreak;\n+\tcase ICE_VSI_VF:\n+\t\t/* Firmware expects vmvf_num to be absolute VF id */\n+\t\ttlan_ctx->vmvf_num = hw->func_caps.vf_base_id + vsi->vf_id;\n+\t\ttlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_VF;\n+\t\tbreak;\n \tdefault:\n \t\treturn;\n \t}\n@@ -285,6 +295,16 @@ static void ice_vsi_set_num_qs(struct ice_vsi *vsi)\n \t\tvsi->num_desc = ALIGN(ICE_DFLT_NUM_DESC, ICE_REQ_DESC_MULTIPLE);\n \t\tvsi->num_q_vectors = max_t(int, pf->num_lan_rx, pf->num_lan_tx);\n \t\tbreak;\n+\tcase ICE_VSI_VF:\n+\t\tvsi->alloc_txq = pf->num_vf_qps;\n+\t\tvsi->alloc_rxq = pf->num_vf_qps;\n+\t\t/* pf->num_vf_msix includes (VF miscellaneous vector +\n+\t\t * data queue interrupts). Since vsi->num_q_vectors is number\n+\t\t * of queues vectors, subtract 1 from the original vector\n+\t\t * count\n+\t\t */\n+\t\tvsi->num_q_vectors = pf->num_vf_msix - 1;\n+\t\tbreak;\n \tdefault:\n \t\tdev_warn(&vsi->back->pdev->dev, \"Unknown VSI type %d\\n\",\n \t\t\t vsi->type);\n@@ -331,6 +351,8 @@ void ice_vsi_delete(struct ice_vsi *vsi)\n \tstruct ice_vsi_ctx ctxt;\n \tenum ice_status status;\n \n+\tif (vsi->type == ICE_VSI_VF)\n+\t\tctxt.vf_num = vsi->vf_id;\n \tctxt.vsi_num = vsi->vsi_num;\n \n \tmemcpy(&ctxt.info, &vsi->info, sizeof(struct ice_aqc_vsi_props));\n@@ -466,6 +488,10 @@ static struct ice_vsi *ice_vsi_alloc(struct ice_pf *pf, enum ice_vsi_type type)\n \t\t/* Setup default MSIX irq handler for VSI */\n \t\tvsi->irq_handler = ice_msix_clean_rings;\n \t\tbreak;\n+\tcase ICE_VSI_VF:\n+\t\tif (ice_vsi_alloc_arrays(vsi, true))\n+\t\t\tgoto err_rings;\n+\t\tbreak;\n \tdefault:\n \t\tdev_warn(&pf->pdev->dev, \"Unknown VSI type %d\\n\", vsi->type);\n \t\tgoto unlock_pf;\n@@ -685,6 +711,15 @@ static void ice_vsi_set_rss_params(struct ice_vsi *vsi)\n \t\t\t\t BIT(cap->rss_table_entry_width));\n \t\tvsi->rss_lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;\n \t\tbreak;\n+\tcase ICE_VSI_VF:\n+\t\t/* VF VSI will gets a small RSS table\n+\t\t * For VSI_LUT, LUT size should be set to 64 bytes\n+\t\t */\n+\t\tvsi->rss_table_size = ICE_VSIQF_HLUT_ARRAY_SIZE;\n+\t\tvsi->rss_size = min_t(int, num_online_cpus(),\n+\t\t\t\t BIT(cap->rss_table_entry_width));\n+\t\tvsi->rss_lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI;\n+\t\tbreak;\n \tdefault:\n \t\tdev_warn(&pf->pdev->dev, \"Unknown VSI type %d\\n\",\n \t\t\t vsi->type);\n@@ -773,17 +808,17 @@ static void ice_vsi_setup_q_map(struct ice_vsi *vsi, struct ice_vsi_ctx *ctxt)\n \t * Setup number and offset of Rx queues for all TCs for the VSI\n \t */\n \n+\tqcount = numq_tc;\n \t/* qcount will change if RSS is enabled */\n \tif (test_bit(ICE_FLAG_RSS_ENA, vsi->back->flags)) {\n-\t\tif (vsi->type == ICE_VSI_PF)\n-\t\t\tmax_rss = ICE_MAX_LG_RSS_QS;\n-\t\telse\n-\t\t\tmax_rss = ICE_MAX_SMALL_RSS_QS;\n-\n-\t\tqcount = min_t(int, numq_tc, max_rss);\n-\t\tqcount = min_t(int, qcount, vsi->rss_size);\n-\t} else {\n-\t\tqcount = numq_tc;\n+\t\tif (vsi->type == ICE_VSI_PF || vsi->type == ICE_VSI_VF) {\n+\t\t\tif (vsi->type == ICE_VSI_PF)\n+\t\t\t\tmax_rss = ICE_MAX_LG_RSS_QS;\n+\t\t\telse\n+\t\t\t\tmax_rss = ICE_MAX_SMALL_RSS_QS;\n+\t\t\tqcount = min_t(int, numq_tc, max_rss);\n+\t\t\tqcount = min_t(int, qcount, vsi->rss_size);\n+\t\t}\n \t}\n \n \t/* find the (rounded up) power-of-2 of qcount */\n@@ -813,6 +848,14 @@ static void ice_vsi_setup_q_map(struct ice_vsi *vsi, struct ice_vsi_ctx *ctxt)\n \tvsi->num_txq = qcount_tx;\n \tvsi->num_rxq = offset;\n \n+\tif (vsi->type == ICE_VSI_VF && vsi->num_txq != vsi->num_rxq) {\n+\t\tdev_dbg(&vsi->back->pdev->dev, \"VF VSI should have same number of Tx and Rx queues. Hence making them equal\\n\");\n+\t\t/* since there is a chance that num_rxq could have been changed\n+\t\t * in the above for loop, make num_txq equal to num_rxq.\n+\t\t */\n+\t\tvsi->num_txq = vsi->num_rxq;\n+\t}\n+\n \t/* Rx queue mapping */\n \tctxt->info.mapping_flags |= cpu_to_le16(ICE_AQ_VSI_Q_MAP_CONTIG);\n \t/* q_mapping buffer holds the info for the first queue allocated for\n@@ -838,6 +881,11 @@ static void ice_set_rss_vsi_ctx(struct ice_vsi_ctx *ctxt, struct ice_vsi *vsi)\n \t\tlut_type = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF;\n \t\thash_type = ICE_AQ_VSI_Q_OPT_RSS_TPLZ;\n \t\tbreak;\n+\tcase ICE_VSI_VF:\n+\t\t/* VF VSI will gets a small RSS table which is a VSI LUT type */\n+\t\tlut_type = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI;\n+\t\thash_type = ICE_AQ_VSI_Q_OPT_RSS_TPLZ;\n+\t\tbreak;\n \tdefault:\n \t\tdev_warn(&vsi->back->pdev->dev, \"Unknown VSI type %d\\n\",\n \t\t\t vsi->type);\n@@ -868,6 +916,11 @@ static int ice_vsi_init(struct ice_vsi *vsi)\n \tcase ICE_VSI_PF:\n \t\tctxt.flags = ICE_AQ_VSI_TYPE_PF;\n \t\tbreak;\n+\tcase ICE_VSI_VF:\n+\t\tctxt.flags = ICE_AQ_VSI_TYPE_VF;\n+\t\t/* VF number here is the absolute VF number (0-255) */\n+\t\tctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;\n+\t\tbreak;\n \tdefault:\n \t\treturn -ENODEV;\n \t}\n@@ -961,6 +1014,8 @@ static int ice_vsi_alloc_q_vector(struct ice_vsi *vsi, int v_idx)\n \n \tq_vector->vsi = vsi;\n \tq_vector->v_idx = v_idx;\n+\tif (vsi->type == ICE_VSI_VF)\n+\t\tgoto out;\n \t/* only set affinity_mask if the CPU is online */\n \tif (cpu_online(v_idx))\n \t\tcpumask_set_cpu(v_idx, &q_vector->affinity_mask);\n@@ -972,7 +1027,7 @@ static int ice_vsi_alloc_q_vector(struct ice_vsi *vsi, int v_idx)\n \tif (vsi->netdev)\n \t\tnetif_napi_add(vsi->netdev, &q_vector->napi, ice_napi_poll,\n \t\t\t NAPI_POLL_WEIGHT);\n-\n+out:\n \t/* tie q_vector and vsi together */\n \tvsi->q_vectors[v_idx] = q_vector;\n \n@@ -1067,6 +1122,13 @@ static int ice_vsi_setup_vector_base(struct ice_vsi *vsi)\n \t\tvsi->hw_base_vector = ice_get_res(pf, pf->hw_irq_tracker,\n \t\t\t\t\t\t num_q_vectors, vsi->idx);\n \t\tbreak;\n+\tcase ICE_VSI_VF:\n+\t\t/* take VF misc vector and data vectors into account */\n+\t\tnum_q_vectors = pf->num_vf_msix;\n+\t\t/* For VF VSI, reserve slots only from HW interrupts */\n+\t\tvsi->hw_base_vector = ice_get_res(pf, pf->hw_irq_tracker,\n+\t\t\t\t\t\t num_q_vectors, vsi->idx);\n+\t\tbreak;\n \tdefault:\n \t\tdev_warn(&vsi->back->pdev->dev, \"Unknown VSI type %d\\n\",\n \t\t\t vsi->type);\n@@ -1077,9 +1139,11 @@ static int ice_vsi_setup_vector_base(struct ice_vsi *vsi)\n \t\tdev_err(&pf->pdev->dev,\n \t\t\t\"Failed to get tracking for %d HW vectors for VSI %d, err=%d\\n\",\n \t\t\tnum_q_vectors, vsi->vsi_num, vsi->hw_base_vector);\n-\t\tice_free_res(vsi->back->sw_irq_tracker, vsi->sw_base_vector,\n-\t\t\t vsi->idx);\n-\t\tpf->num_avail_sw_msix += num_q_vectors;\n+\t\tif (vsi->type != ICE_VSI_VF) {\n+\t\t\tice_free_res(vsi->back->sw_irq_tracker,\n+\t\t\t\t vsi->sw_base_vector, vsi->idx);\n+\t\t\tpf->num_avail_sw_msix += num_q_vectors;\n+\t\t}\n \t\treturn -ENOENT;\n \t}\n \n@@ -1512,6 +1576,9 @@ int ice_vsi_cfg_rxqs(struct ice_vsi *vsi)\n \tint err = 0;\n \tu16 i;\n \n+\tif (vsi->type == ICE_VSI_VF)\n+\t\tgoto setup_rings;\n+\n \tif (vsi->netdev && vsi->netdev->mtu > ETH_DATA_LEN)\n \t\tvsi->max_frame = vsi->netdev->mtu +\n \t\t\tETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;\n@@ -1519,6 +1586,7 @@ int ice_vsi_cfg_rxqs(struct ice_vsi *vsi)\n \t\tvsi->max_frame = ICE_RXBUF_2048;\n \n \tvsi->rx_buf_len = ICE_RXBUF_2048;\n+setup_rings:\n \t/* set up individual rings */\n \tfor (i = 0; i < vsi->num_rxq && !err; i++)\n \t\terr = ice_setup_rx_ctx(vsi->rx_rings[i]);\n@@ -1667,9 +1735,14 @@ void ice_vsi_cfg_msix(struct ice_vsi *vsi)\n \t\t\tu32 val;\n \n \t\t\titr = ICE_ITR_NONE;\n-\t\t\tval = QINT_TQCTL_CAUSE_ENA_M |\n-\t\t\t (itr << QINT_TQCTL_ITR_INDX_S) |\n-\t\t\t (vector << QINT_TQCTL_MSIX_INDX_S);\n+\t\t\tif (vsi->type == ICE_VSI_VF)\n+\t\t\t\tval = QINT_TQCTL_CAUSE_ENA_M |\n+\t\t\t\t (itr << QINT_TQCTL_ITR_INDX_S) |\n+\t\t\t\t ((i + 1) << QINT_TQCTL_MSIX_INDX_S);\n+\t\t\telse\n+\t\t\t\tval = QINT_TQCTL_CAUSE_ENA_M |\n+\t\t\t\t (itr << QINT_TQCTL_ITR_INDX_S) |\n+\t\t\t\t (vector << QINT_TQCTL_MSIX_INDX_S);\n \t\t\twr32(hw, QINT_TQCTL(vsi->txq_map[txq]), val);\n \t\t\ttxq++;\n \t\t}\n@@ -1678,9 +1751,14 @@ void ice_vsi_cfg_msix(struct ice_vsi *vsi)\n \t\t\tu32 val;\n \n \t\t\titr = ICE_ITR_NONE;\n-\t\t\tval = QINT_RQCTL_CAUSE_ENA_M |\n-\t\t\t (itr << QINT_RQCTL_ITR_INDX_S) |\n-\t\t\t (vector << QINT_RQCTL_MSIX_INDX_S);\n+\t\t\tif (vsi->type == ICE_VSI_VF)\n+\t\t\t\tval = QINT_RQCTL_CAUSE_ENA_M |\n+\t\t\t\t (itr << QINT_RQCTL_ITR_INDX_S) |\n+\t\t\t\t ((i + 1) << QINT_RQCTL_MSIX_INDX_S);\n+\t\t\telse\n+\t\t\t\tval = QINT_RQCTL_CAUSE_ENA_M |\n+\t\t\t\t (itr << QINT_RQCTL_ITR_INDX_S) |\n+\t\t\t\t (vector << QINT_RQCTL_MSIX_INDX_S);\n \t\t\twr32(hw, QINT_RQCTL(vsi->rxq_map[rxq]), val);\n \t\t\trxq++;\n \t\t}\n@@ -1937,7 +2015,7 @@ int ice_cfg_vlan_pruning(struct ice_vsi *vsi, bool ena)\n */\n struct ice_vsi *\n ice_vsi_setup(struct ice_pf *pf, struct ice_port_info *pi,\n-\t enum ice_vsi_type type, u16 __always_unused vf_id)\n+\t enum ice_vsi_type type, u16 vf_id)\n {\n \tu16 max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };\n \tstruct device *dev = &pf->pdev->dev;\n@@ -1952,6 +2030,8 @@ ice_vsi_setup(struct ice_pf *pf, struct ice_port_info *pi,\n \n \tvsi->port_info = pi;\n \tvsi->vsw = pf->first_sw;\n+\tif (vsi->type == ICE_VSI_VF)\n+\t\tvsi->vf_id = vf_id;\n \n \tif (ice_vsi_get_qs(vsi)) {\n \t\tdev_err(dev, \"Failed to allocate queues. vsi->idx = %d\\n\",\n@@ -1990,6 +2070,34 @@ ice_vsi_setup(struct ice_pf *pf, struct ice_port_info *pi,\n \t\tif (test_bit(ICE_FLAG_RSS_ENA, pf->flags))\n \t\t\tice_vsi_cfg_rss_lut_key(vsi);\n \t\tbreak;\n+\tcase ICE_VSI_VF:\n+\t\t/* VF driver will take care of creating netdev for this type and\n+\t\t * map queues to vectors through Virtchnl, PF driver only\n+\t\t * creates a VSI and corresponding structures for bookkeeping\n+\t\t * purpose\n+\t\t */\n+\t\tret = ice_vsi_alloc_q_vectors(vsi);\n+\t\tif (ret)\n+\t\t\tgoto unroll_vsi_init;\n+\n+\t\tret = ice_vsi_alloc_rings(vsi);\n+\t\tif (ret)\n+\t\t\tgoto unroll_alloc_q_vector;\n+\n+\t\t/* Setup Vector base only during VF init phase or when VF asks\n+\t\t * for more vectors than assigned number. In all other cases,\n+\t\t * assign hw_base_vector to the value given earlier.\n+\t\t */\n+\t\tif (test_bit(ICE_VF_STATE_CFG_INTR, pf->vf[vf_id].vf_states)) {\n+\t\t\tret = ice_vsi_setup_vector_base(vsi);\n+\t\t\tif (ret)\n+\t\t\t\tgoto unroll_vector_base;\n+\t\t} else {\n+\t\t\tvsi->hw_base_vector = pf->vf[vf_id].first_vector_idx;\n+\t\t}\n+\t\tpf->q_left_tx -= vsi->alloc_txq;\n+\t\tpf->q_left_rx -= vsi->alloc_rxq;\n+\t\tbreak;\n \tdefault:\n \t\t/* if vsi type is not recognized, clean up the resources and\n \t\t * exit\n@@ -2080,6 +2188,8 @@ void ice_vsi_free_irq(struct ice_vsi *vsi)\n \t\t\treturn;\n \n \t\tice_vsi_release_msix(vsi);\n+\t\tif (vsi->type == ICE_VSI_VF)\n+\t\t\treturn;\n \n \t\tvsi->irqs_ready = false;\n \t\tfor (i = 0; i < vsi->num_q_vectors; i++) {\n@@ -2320,10 +2430,12 @@ void ice_vsi_dis_irq(struct ice_vsi *vsi)\n int ice_vsi_release(struct ice_vsi *vsi)\n {\n \tstruct ice_pf *pf;\n+\tstruct ice_vf *vf;\n \n \tif (!vsi->back)\n \t\treturn -ENODEV;\n \tpf = vsi->back;\n+\tvf = &pf->vf[vsi->vf_id];\n \t/* do not unregister and free netdevs while driver is in the reset\n \t * recovery pending state. Since reset/rebuild happens through PF\n \t * service task workqueue, its not a good idea to unregister netdev\n@@ -2345,10 +2457,23 @@ int ice_vsi_release(struct ice_vsi *vsi)\n \tice_vsi_close(vsi);\n \n \t/* reclaim interrupt vectors back to PF */\n-\tice_free_res(vsi->back->sw_irq_tracker, vsi->sw_base_vector, vsi->idx);\n-\tpf->num_avail_sw_msix += vsi->num_q_vectors;\n-\tice_free_res(vsi->back->hw_irq_tracker, vsi->hw_base_vector, vsi->idx);\n-\tpf->num_avail_hw_msix += vsi->num_q_vectors;\n+\tif (vsi->type != ICE_VSI_VF) {\n+\t\t/* reclaim SW interrupts back to the common pool */\n+\t\tice_free_res(vsi->back->sw_irq_tracker, vsi->sw_base_vector,\n+\t\t\t vsi->idx);\n+\t\tpf->num_avail_sw_msix += vsi->num_q_vectors;\n+\t\t/* reclaim HW interrupts back to the common pool */\n+\t\tice_free_res(vsi->back->hw_irq_tracker, vsi->hw_base_vector,\n+\t\t\t vsi->idx);\n+\t\tpf->num_avail_hw_msix += vsi->num_q_vectors;\n+\t} else if (test_bit(ICE_VF_STATE_CFG_INTR, vf->vf_states)) {\n+\t\t/* Reclaim VF resources back only while freeing all VFs or\n+\t\t * vector reassignment is requested\n+\t\t */\n+\t\tice_free_res(vsi->back->hw_irq_tracker, vf->first_vector_idx,\n+\t\t\t vsi->idx);\n+\t\tpf->num_avail_hw_msix += pf->num_vf_msix;\n+\t}\n \n \tice_remove_vsi_fltr(&pf->hw, vsi->idx);\n \tice_vsi_delete(vsi);\n@@ -2417,6 +2542,22 @@ int ice_vsi_rebuild(struct ice_vsi *vsi)\n \n \t\tice_vsi_map_rings_to_vectors(vsi);\n \t\tbreak;\n+\tcase ICE_VSI_VF:\n+\t\tret = ice_vsi_alloc_q_vectors(vsi);\n+\t\tif (ret)\n+\t\t\tgoto err_rings;\n+\n+\t\tret = ice_vsi_setup_vector_base(vsi);\n+\t\tif (ret)\n+\t\t\tgoto err_vectors;\n+\n+\t\tret = ice_vsi_alloc_rings(vsi);\n+\t\tif (ret)\n+\t\t\tgoto err_vectors;\n+\n+\t\tvsi->back->q_left_tx -= vsi->alloc_txq;\n+\t\tvsi->back->q_left_rx -= vsi->alloc_rxq;\n+\t\tbreak;\n \tdefault:\n \t\tbreak;\n \t}\ndiff --git a/drivers/net/ethernet/intel/ice/ice_switch.h b/drivers/net/ethernet/intel/ice/ice_switch.h\nindex 7706e9b6003c..b88d96a1ef69 100644\n--- a/drivers/net/ethernet/intel/ice/ice_switch.h\n+++ b/drivers/net/ethernet/intel/ice/ice_switch.h\n@@ -19,6 +19,7 @@ struct ice_vsi_ctx {\n \tstruct ice_aqc_vsi_props info;\n \tstruct ice_sched_vsi_info sched;\n \tu8 alloc_from_pool;\n+\tu8 vf_num;\n };\n \n enum ice_sw_fwd_act_type {\ndiff --git a/drivers/net/ethernet/intel/ice/ice_type.h b/drivers/net/ethernet/intel/ice/ice_type.h\nindex 15b3c999006a..12f9432abf11 100644\n--- a/drivers/net/ethernet/intel/ice/ice_type.h\n+++ b/drivers/net/ethernet/intel/ice/ice_type.h\n@@ -443,4 +443,7 @@ struct ice_hw_port_stats {\n #define ICE_SR_SECTOR_SIZE_IN_WORDS\t0x800\n #define ICE_SR_WORDS_IN_1KB\t\t512\n \n+/* Hash redirection LUT for VSI - maximum array size */\n+#define ICE_VSIQF_HLUT_ARRAY_SIZE\t((VSIQF_HLUT_MAX_INDEX + 1) * 4)\n+\n #endif /* _ICE_TYPE_H_ */\n", "prefixes": [ "v2", "04/16" ] }