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GET /api/patches/972068/?format=api
{ "id": 972068, "url": "http://patchwork.ozlabs.org/api/patches/972068/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20180920004308.13772-14-anirudh.venkataramanan@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20180920004308.13772-14-anirudh.venkataramanan@intel.com>", "list_archive_url": null, "date": "2018-09-20T00:43:05", "name": "[v2,13/16] ice: Add more flexibility on how we assign an ITR index", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "bcbd07f561ea2435e3e5f8ccc6e8ec59f7631f9e", "submitter": { "id": 73601, "url": "http://patchwork.ozlabs.org/api/people/73601/?format=api", "name": "Anirudh Venkataramanan", "email": "anirudh.venkataramanan@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20180920004308.13772-14-anirudh.venkataramanan@intel.com/mbox/", "series": [ { "id": 66527, "url": "http://patchwork.ozlabs.org/api/series/66527/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=66527", "date": "2018-09-20T00:42:53", "name": "Add SR-IOV support, feature updates", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/66527/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/972068/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/972068/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.136; helo=silver.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 42FydN6J5Tz9sBJ\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 20 Sep 2018 10:43:20 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id 31B9D2279C;\n\tThu, 20 Sep 2018 00:43:19 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id SYuHFcbgdNa4; Thu, 20 Sep 2018 00:43:14 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby silver.osuosl.org (Postfix) with ESMTP id 96B0130968;\n\tThu, 20 Sep 2018 00:43:13 +0000 (UTC)", "from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\tby ash.osuosl.org (Postfix) with ESMTP id 92C1C1C08AF\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 20 Sep 2018 00:43:11 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 90ECF876F7\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 20 Sep 2018 00:43:11 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 5YzEcWYJZrkl for <intel-wired-lan@lists.osuosl.org>;\n\tThu, 20 Sep 2018 00:43:10 +0000 (UTC)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n\tby fraxinus.osuosl.org (Postfix) with ESMTPS id 8A40C876E4\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 20 Sep 2018 00:43:10 +0000 (UTC)", "from orsmga004.jf.intel.com ([10.7.209.38])\n\tby fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t19 Sep 2018 17:43:10 -0700", "from shasta.jf.intel.com ([10.166.241.11])\n\tby orsmga004.jf.intel.com with ESMTP; 19 Sep 2018 17:43:09 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.53,396,1531810800\"; d=\"scan'208\";a=\"234371603\"", "From": "Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Wed, 19 Sep 2018 17:43:05 -0700", "Message-Id": "<20180920004308.13772-14-anirudh.venkataramanan@intel.com>", "X-Mailer": "git-send-email 2.14.3", "In-Reply-To": "<20180920004308.13772-1-anirudh.venkataramanan@intel.com>", "References": "<20180920004308.13772-1-anirudh.venkataramanan@intel.com>", "Subject": "[Intel-wired-lan] [PATCH v2 13/16] ice: Add more flexibility on how\n\twe assign an ITR index", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.24", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "From: Brett Creeley <brett.creeley@intel.com>\n\nThis issue came about when looking at the VF function\nice_vc_cfg_irq_map_msg. Currently we are assigning the itr_setting value\nto the itr_idx received from the AVF driver, which is not correct and is\nnot used for the VF flow anyway. Currently the only way we set the ITR\nindex for both the PF and VF driver is by hardcoding ICE_TX_ITR or\nICE_RX_ITR for the ITR index on each q_vector.\n\nTo fix this, add the member itr_idx in struct ice_ring_container. Thisi\ncan then be used to dynamically program the correct ITR index. This change\nalso affected the PF driver so make the necessary changes there as well.\n\nAlso, removed the itr_setting member in struct ice_ring because it is not\nbeing used meaningfully and is going to be removed in a future patch that\nincludes dynamic itr.\n\nOn another note, this will be useful moving forward if we decide to split\nrx/tx rings on different q_vectors instead of sharing them as queue pairs.\n\nSigned-off-by: Brett Creeley <brett.creeley@intel.com>\nSigned-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>\n---\n[Anirudh Venkataramanan <anirudh.venkataramanan@intel.com> cleaned up commit message]\n---\n drivers/net/ethernet/intel/ice/ice_lib.c | 73 ++++++++++++++----------\n drivers/net/ethernet/intel/ice/ice_txrx.h | 13 ++---\n drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c | 20 ++++---\n 3 files changed, 59 insertions(+), 47 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/ice/ice_lib.c b/drivers/net/ethernet/intel/ice/ice_lib.c\nindex 0dbf3245a9d9..5315a10c6849 100644\n--- a/drivers/net/ethernet/intel/ice/ice_lib.c\n+++ b/drivers/net/ethernet/intel/ice/ice_lib.c\n@@ -1203,7 +1203,6 @@ static int ice_vsi_alloc_rings(struct ice_vsi *vsi)\n \t\tring->vsi = vsi;\n \t\tring->dev = &pf->pdev->dev;\n \t\tring->count = vsi->num_desc;\n-\t\tring->itr_setting = ICE_DFLT_TX_ITR;\n \t\tvsi->tx_rings[i] = ring;\n \t}\n \n@@ -1223,7 +1222,6 @@ static int ice_vsi_alloc_rings(struct ice_vsi *vsi)\n \t\tring->netdev = vsi->netdev;\n \t\tring->dev = &pf->pdev->dev;\n \t\tring->count = vsi->num_desc;\n-\t\tring->itr_setting = ICE_DFLT_RX_ITR;\n \t\tvsi->rx_rings[i] = ring;\n \t}\n \n@@ -1260,6 +1258,7 @@ static void ice_vsi_map_rings_to_vectors(struct ice_vsi *vsi)\n \t\ttx_rings_per_v = DIV_ROUND_UP(tx_rings_rem, q_vectors - v_id);\n \t\tq_vector->num_ring_tx = tx_rings_per_v;\n \t\tq_vector->tx.ring = NULL;\n+\t\tq_vector->tx.itr_idx = ICE_TX_ITR;\n \t\tq_base = vsi->num_txq - tx_rings_rem;\n \n \t\tfor (q_id = q_base; q_id < (q_base + tx_rings_per_v); q_id++) {\n@@ -1275,6 +1274,7 @@ static void ice_vsi_map_rings_to_vectors(struct ice_vsi *vsi)\n \t\trx_rings_per_v = DIV_ROUND_UP(rx_rings_rem, q_vectors - v_id);\n \t\tq_vector->num_ring_rx = rx_rings_per_v;\n \t\tq_vector->rx.ring = NULL;\n+\t\tq_vector->rx.itr_idx = ICE_RX_ITR;\n \t\tq_base = vsi->num_rxq - rx_rings_rem;\n \n \t\tfor (q_id = q_base; q_id < (q_base + rx_rings_per_v); q_id++) {\n@@ -1682,6 +1682,37 @@ static u32 ice_intrl_usec_to_reg(u8 intrl, u8 gran)\n \treturn 0;\n }\n \n+/**\n+ * ice_cfg_itr - configure the initial interrupt throttle values\n+ * @hw: pointer to the hw structure\n+ * @q_vector: interrupt vector that's being configured\n+ * @vector: hw vector index to apply the interrupt throttling to\n+ *\n+ * Configure interrupt throttling values for the ring containers that are\n+ * associated with the interrupt vector passed in.\n+ */\n+static void\n+ice_cfg_itr(struct ice_hw *hw, struct ice_q_vector *q_vector, u16 vector)\n+{\n+\tu8 itr_gran = hw->itr_gran;\n+\n+\tif (q_vector->num_ring_rx) {\n+\t\tstruct ice_ring_container *rc = &q_vector->rx;\n+\n+\t\trc->itr = ITR_TO_REG(ICE_DFLT_RX_ITR, itr_gran);\n+\t\trc->latency_range = ICE_LOW_LATENCY;\n+\t\twr32(hw, GLINT_ITR(rc->itr_idx, vector), rc->itr);\n+\t}\n+\n+\tif (q_vector->num_ring_tx) {\n+\t\tstruct ice_ring_container *rc = &q_vector->tx;\n+\n+\t\trc->itr = ITR_TO_REG(ICE_DFLT_TX_ITR, itr_gran);\n+\t\trc->latency_range = ICE_LOW_LATENCY;\n+\t\twr32(hw, GLINT_ITR(rc->itr_idx, vector), rc->itr);\n+\t}\n+}\n+\n /**\n * ice_vsi_cfg_msix - MSIX mode Interrupt Config in the HW\n * @vsi: the VSI being configured\n@@ -1692,31 +1723,13 @@ void ice_vsi_cfg_msix(struct ice_vsi *vsi)\n \tu16 vector = vsi->hw_base_vector;\n \tstruct ice_hw *hw = &pf->hw;\n \tu32 txq = 0, rxq = 0;\n-\tint i, q, itr;\n-\tu8 itr_gran;\n+\tint i, q;\n \n \tfor (i = 0; i < vsi->num_q_vectors; i++, vector++) {\n \t\tstruct ice_q_vector *q_vector = vsi->q_vectors[i];\n \n-\t\titr_gran = hw->itr_gran;\n+\t\tice_cfg_itr(hw, q_vector, vector);\n \n-\t\tq_vector->intrl = ICE_DFLT_INTRL;\n-\n-\t\tif (q_vector->num_ring_rx) {\n-\t\t\tq_vector->rx.itr =\n-\t\t\t\tITR_TO_REG(vsi->rx_rings[rxq]->itr_setting,\n-\t\t\t\t\t itr_gran);\n-\t\t\tq_vector->rx.latency_range = ICE_LOW_LATENCY;\n-\t\t}\n-\n-\t\tif (q_vector->num_ring_tx) {\n-\t\t\tq_vector->tx.itr =\n-\t\t\t\tITR_TO_REG(vsi->tx_rings[txq]->itr_setting,\n-\t\t\t\t\t itr_gran);\n-\t\t\tq_vector->tx.latency_range = ICE_LOW_LATENCY;\n-\t\t}\n-\t\twr32(hw, GLINT_ITR(ICE_RX_ITR, vector), q_vector->rx.itr);\n-\t\twr32(hw, GLINT_ITR(ICE_TX_ITR, vector), q_vector->tx.itr);\n \t\twr32(hw, GLINT_RATE(vector),\n \t\t ice_intrl_usec_to_reg(q_vector->intrl, hw->intrl_gran));\n \n@@ -1732,32 +1745,32 @@ void ice_vsi_cfg_msix(struct ice_vsi *vsi)\n \t\t * tracked for this PF.\n \t\t */\n \t\tfor (q = 0; q < q_vector->num_ring_tx; q++) {\n+\t\t\tint itr_idx = q_vector->tx.itr_idx;\n \t\t\tu32 val;\n \n-\t\t\titr = ICE_ITR_NONE;\n \t\t\tif (vsi->type == ICE_VSI_VF)\n \t\t\t\tval = QINT_TQCTL_CAUSE_ENA_M |\n-\t\t\t\t (itr << QINT_TQCTL_ITR_INDX_S) |\n+\t\t\t\t (itr_idx << QINT_TQCTL_ITR_INDX_S) |\n \t\t\t\t ((i + 1) << QINT_TQCTL_MSIX_INDX_S);\n \t\t\telse\n \t\t\t\tval = QINT_TQCTL_CAUSE_ENA_M |\n-\t\t\t\t (itr << QINT_TQCTL_ITR_INDX_S) |\n+\t\t\t\t (itr_idx << QINT_TQCTL_ITR_INDX_S) |\n \t\t\t\t (vector << QINT_TQCTL_MSIX_INDX_S);\n \t\t\twr32(hw, QINT_TQCTL(vsi->txq_map[txq]), val);\n \t\t\ttxq++;\n \t\t}\n \n \t\tfor (q = 0; q < q_vector->num_ring_rx; q++) {\n+\t\t\tint itr_idx = q_vector->rx.itr_idx;\n \t\t\tu32 val;\n \n-\t\t\titr = ICE_ITR_NONE;\n \t\t\tif (vsi->type == ICE_VSI_VF)\n \t\t\t\tval = QINT_RQCTL_CAUSE_ENA_M |\n-\t\t\t\t (itr << QINT_RQCTL_ITR_INDX_S) |\n+\t\t\t\t (itr_idx << QINT_RQCTL_ITR_INDX_S) |\n \t\t\t\t ((i + 1) << QINT_RQCTL_MSIX_INDX_S);\n \t\t\telse\n \t\t\t\tval = QINT_RQCTL_CAUSE_ENA_M |\n-\t\t\t\t (itr << QINT_RQCTL_ITR_INDX_S) |\n+\t\t\t\t (itr_idx << QINT_RQCTL_ITR_INDX_S) |\n \t\t\t\t (vector << QINT_RQCTL_MSIX_INDX_S);\n \t\t\twr32(hw, QINT_RQCTL(vsi->rxq_map[rxq]), val);\n \t\t\trxq++;\n@@ -2156,8 +2169,8 @@ static void ice_vsi_release_msix(struct ice_vsi *vsi)\n \tfor (i = 0; i < vsi->num_q_vectors; i++, vector++) {\n \t\tstruct ice_q_vector *q_vector = vsi->q_vectors[i];\n \n-\t\twr32(hw, GLINT_ITR(ICE_RX_ITR, vector), 0);\n-\t\twr32(hw, GLINT_ITR(ICE_TX_ITR, vector), 0);\n+\t\twr32(hw, GLINT_ITR(ICE_IDX_ITR0, vector), 0);\n+\t\twr32(hw, GLINT_ITR(ICE_IDX_ITR1, vector), 0);\n \t\tfor (q = 0; q < q_vector->num_ring_tx; q++) {\n \t\t\twr32(hw, QINT_TQCTL(vsi->txq_map[txq]), 0);\n \t\t\ttxq++;\ndiff --git a/drivers/net/ethernet/intel/ice/ice_txrx.h b/drivers/net/ethernet/intel/ice/ice_txrx.h\nindex a9b92974e041..1d0f58bd389b 100644\n--- a/drivers/net/ethernet/intel/ice/ice_txrx.h\n+++ b/drivers/net/ethernet/intel/ice/ice_txrx.h\n@@ -105,8 +105,9 @@ enum ice_rx_dtype {\n #define ICE_TX_ITR\tICE_IDX_ITR1\n #define ICE_ITR_DYNAMIC\t0x8000 /* use top bit as a flag */\n #define ICE_ITR_8K\t125\n-#define ICE_DFLT_TX_ITR\tICE_ITR_8K\n-#define ICE_DFLT_RX_ITR\tICE_ITR_8K\n+#define ICE_ITR_20K\t50\n+#define ICE_DFLT_TX_ITR\tICE_ITR_20K\n+#define ICE_DFLT_RX_ITR\tICE_ITR_20K\n /* apply ITR granularity translation to program the register. itr_gran is either\n * 2 or 4 usecs so we need to divide by 2 first then shift by that value\n */\n@@ -135,13 +136,6 @@ struct ice_ring {\n \tu16 q_index;\t\t\t/* Queue number of ring */\n \tu32 txq_teid;\t\t\t/* Added Tx queue TEID */\n \n-\t/* high bit set means dynamic, use accessor routines to read/write.\n-\t * hardware supports 4us/2us resolution for the ITR registers.\n-\t * these values always store the USER setting, and must be converted\n-\t * before programming to a register.\n-\t */\n-\tu16 itr_setting;\n-\n \tu16 count;\t\t\t/* Number of descriptors */\n \tu16 reg_idx;\t\t\t/* HW register index of the ring */\n \n@@ -178,6 +172,7 @@ struct ice_ring_container {\n \tunsigned int total_bytes;\t/* total bytes processed this int */\n \tunsigned int total_pkts;\t/* total packets processed this int */\n \tenum ice_latency_range latency_range;\n+\tint itr_idx;\t/* index in the interrupt vector */\n \tu16 itr;\n };\n \ndiff --git a/drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c b/drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c\nindex 5d14b9f2682a..cd72a6482f53 100644\n--- a/drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c\n+++ b/drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c\n@@ -1678,26 +1678,30 @@ static int ice_vc_cfg_irq_map_msg(struct ice_vf *vf, u8 *msg)\n \t\t/* lookout for the invalid queue index */\n \t\tqmap = map->rxq_map;\n \t\tfor_each_set_bit(vsi_q_id, &qmap, ICE_MAX_BASE_QS_PER_VF) {\n+\t\t\tstruct ice_q_vector *q_vector;\n+\n \t\t\tif (!ice_vc_isvalid_q_id(vf, vsi_id, vsi_q_id)) {\n \t\t\t\taq_ret = ICE_ERR_PARAM;\n \t\t\t\tgoto error_param;\n \t\t\t}\n-\t\t\tvsi->q_vectors[i]->num_ring_rx++;\n-\t\t\tvsi->rx_rings[vsi_q_id]->itr_setting =\n-\t\t\t\tmap->rxitr_idx;\n-\t\t\tvsi->rx_rings[vsi_q_id]->q_vector = vsi->q_vectors[i];\n+\t\t\tq_vector = vsi->q_vectors[i];\n+\t\t\tq_vector->num_ring_rx++;\n+\t\t\tq_vector->rx.itr_idx = map->rxitr_idx;\n+\t\t\tvsi->rx_rings[vsi_q_id]->q_vector = q_vector;\n \t\t}\n \n \t\tqmap = map->txq_map;\n \t\tfor_each_set_bit(vsi_q_id, &qmap, ICE_MAX_BASE_QS_PER_VF) {\n+\t\t\tstruct ice_q_vector *q_vector;\n+\n \t\t\tif (!ice_vc_isvalid_q_id(vf, vsi_id, vsi_q_id)) {\n \t\t\t\taq_ret = ICE_ERR_PARAM;\n \t\t\t\tgoto error_param;\n \t\t\t}\n-\t\t\tvsi->q_vectors[i]->num_ring_tx++;\n-\t\t\tvsi->tx_rings[vsi_q_id]->itr_setting =\n-\t\t\t\tmap->txitr_idx;\n-\t\t\tvsi->tx_rings[vsi_q_id]->q_vector = vsi->q_vectors[i];\n+\t\t\tq_vector = vsi->q_vectors[i];\n+\t\t\tq_vector->num_ring_tx++;\n+\t\t\tq_vector->tx.itr_idx = map->txitr_idx;\n+\t\t\tvsi->tx_rings[vsi_q_id]->q_vector = q_vector;\n \t\t}\n \t}\n \n", "prefixes": [ "v2", "13/16" ] }