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GET /api/patches/972067/?format=api
{ "id": 972067, "url": "http://patchwork.ozlabs.org/api/patches/972067/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20180920004308.13772-3-anirudh.venkataramanan@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20180920004308.13772-3-anirudh.venkataramanan@intel.com>", "list_archive_url": null, "date": "2018-09-20T00:42:54", "name": "[v2,02/16] ice: Add support to detect SR-IOV capability and mailbox queues", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "520b839f22ca4791387116a02340975de19d424f", "submitter": { "id": 73601, "url": "http://patchwork.ozlabs.org/api/people/73601/?format=api", "name": "Anirudh Venkataramanan", "email": "anirudh.venkataramanan@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20180920004308.13772-3-anirudh.venkataramanan@intel.com/mbox/", "series": [ { "id": 66527, "url": "http://patchwork.ozlabs.org/api/series/66527/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=66527", "date": "2018-09-20T00:42:53", "name": "Add SR-IOV support, feature updates", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/66527/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/972067/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/972067/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.138; helo=whitealder.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 42FydJ709kz9sBs\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 20 Sep 2018 10:43:16 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 0A72588236;\n\tThu, 20 Sep 2018 00:43:15 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id iMRMEQovdOze; Thu, 20 Sep 2018 00:43:12 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id D435B88230;\n\tThu, 20 Sep 2018 00:43:12 +0000 (UTC)", "from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\tby ash.osuosl.org (Postfix) with ESMTP id 0B31B1C08AF\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 20 Sep 2018 00:43:11 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 09116876EF\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 20 Sep 2018 00:43:11 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 9227iAfWI-Pk for <intel-wired-lan@lists.osuosl.org>;\n\tThu, 20 Sep 2018 00:43:09 +0000 (UTC)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n\tby fraxinus.osuosl.org (Postfix) with ESMTPS id 999E087599\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 20 Sep 2018 00:43:09 +0000 (UTC)", "from orsmga004.jf.intel.com ([10.7.209.38])\n\tby fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t19 Sep 2018 17:43:09 -0700", "from shasta.jf.intel.com ([10.166.241.11])\n\tby orsmga004.jf.intel.com with ESMTP; 19 Sep 2018 17:43:08 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.53,396,1531810800\"; d=\"scan'208\";a=\"234371592\"", "From": "Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Wed, 19 Sep 2018 17:42:54 -0700", "Message-Id": "<20180920004308.13772-3-anirudh.venkataramanan@intel.com>", "X-Mailer": "git-send-email 2.14.3", "In-Reply-To": "<20180920004308.13772-1-anirudh.venkataramanan@intel.com>", "References": "<20180920004308.13772-1-anirudh.venkataramanan@intel.com>", "Subject": "[Intel-wired-lan] [PATCH v2 02/16] ice: Add support to detect\n\tSR-IOV capability and mailbox queues", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.24", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "Mailbox queue is a type of control queue that's used for communication\nbetween PF and VF. This patch adds code to initialize, configure and\nuse mailbox queues.\n\nThis patch also adds support to detect and parse SR-IOV capabilities\nreturned by the hardware.\n\nSigned-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>\n---\n drivers/net/ethernet/intel/ice/ice.h | 5 +++\n drivers/net/ethernet/intel/ice/ice_adminq_cmd.h | 2 ++\n drivers/net/ethernet/intel/ice/ice_common.c | 22 ++++++++++++\n drivers/net/ethernet/intel/ice/ice_controlq.c | 46 +++++++++++++++++++++++-\n drivers/net/ethernet/intel/ice/ice_controlq.h | 2 ++\n drivers/net/ethernet/intel/ice/ice_hw_autogen.h | 21 +++++++++++\n drivers/net/ethernet/intel/ice/ice_main.c | 47 +++++++++++++++++++++++++\n drivers/net/ethernet/intel/ice/ice_type.h | 7 ++++\n 8 files changed, 151 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/ethernet/intel/ice/ice.h b/drivers/net/ethernet/intel/ice/ice.h\nindex 28002936a0cb..4deb6c88e199 100644\n--- a/drivers/net/ethernet/intel/ice/ice.h\n+++ b/drivers/net/ethernet/intel/ice/ice.h\n@@ -46,6 +46,7 @@ extern const char ice_drv_ver[];\n #define ICE_INT_NAME_STR_LEN\t(IFNAMSIZ + 16)\n #define ICE_ETHTOOL_FWVER_LEN\t32\n #define ICE_AQ_LEN\t\t64\n+#define ICE_MBXQ_LEN\t\t64\n #define ICE_MIN_MSIX\t\t2\n #define ICE_NO_VSI\t\t0xffff\n #define ICE_MAX_VSI_ALLOC\t130\n@@ -63,6 +64,7 @@ extern const char ice_drv_ver[];\n #define ICE_RES_MISC_VEC_ID\t(ICE_RES_VALID_BIT - 1)\n #define ICE_INVAL_Q_INDEX\t0xffff\n #define ICE_INVAL_VFID\t\t256\n+#define ICE_MAX_VF_COUNT\t256\n \n #define ICE_VSIQF_HKEY_ARRAY_SIZE\t((VSIQF_HKEY_MAX_INDEX + 1) *\t4)\n \n@@ -134,6 +136,7 @@ enum ice_state {\n \t__ICE_SUSPENDED,\t\t/* set on module remove path */\n \t__ICE_RESET_FAILED,\t\t/* set by reset/rebuild */\n \t__ICE_ADMINQ_EVENT_PENDING,\n+\t__ICE_MAILBOXQ_EVENT_PENDING,\n \t__ICE_MDD_EVENT_PENDING,\n \t__ICE_FLTR_OVERFLOW_PROMISC,\n \t__ICE_CFG_BUSY,\n@@ -240,6 +243,7 @@ enum ice_pf_flags {\n \tICE_FLAG_MSIX_ENA,\n \tICE_FLAG_FLTR_SYNC,\n \tICE_FLAG_RSS_ENA,\n+\tICE_FLAG_SRIOV_CAPABLE,\n \tICE_PF_FLAGS_NBITS\t\t/* must be last */\n };\n \n@@ -255,6 +259,7 @@ struct ice_pf {\n \n \tstruct ice_vsi **vsi;\t\t/* VSIs created by the driver */\n \tstruct ice_sw *first_sw;\t/* first switch created by firmware */\n+\tu16 num_vfs_supported;\t\t/* num VFs supported for this PF */\n \tDECLARE_BITMAP(state, __ICE_STATE_NBITS);\n \tDECLARE_BITMAP(avail_txqs, ICE_MAX_TXQS);\n \tDECLARE_BITMAP(avail_rxqs, ICE_MAX_RXQS);\ndiff --git a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h\nindex c100b4bda195..7d793cc96a18 100644\n--- a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h\n+++ b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h\n@@ -87,6 +87,8 @@ struct ice_aqc_list_caps {\n /* Device/Function buffer entry, repeated per reported capability */\n struct ice_aqc_list_caps_elem {\n \t__le16 cap;\n+#define ICE_AQC_CAPS_SRIOV\t\t\t\t0x0012\n+#define ICE_AQC_CAPS_VF\t\t\t\t\t0x0013\n #define ICE_AQC_CAPS_VSI\t\t\t\t0x0017\n #define ICE_AQC_CAPS_RSS\t\t\t\t0x0040\n #define ICE_AQC_CAPS_RXQS\t\t\t\t0x0041\ndiff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c\nindex e9e5c601b321..4612d5fa9416 100644\n--- a/drivers/net/ethernet/intel/ice/ice_common.c\n+++ b/drivers/net/ethernet/intel/ice/ice_common.c\n@@ -1406,6 +1406,28 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,\n \t\tu16 cap = le16_to_cpu(cap_resp->cap);\n \n \t\tswitch (cap) {\n+\t\tcase ICE_AQC_CAPS_SRIOV:\n+\t\t\tcaps->sr_iov_1_1 = (number == 1);\n+\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t \"HW caps: SR-IOV = %d\\n\", caps->sr_iov_1_1);\n+\t\t\tbreak;\n+\t\tcase ICE_AQC_CAPS_VF:\n+\t\t\tif (dev_p) {\n+\t\t\t\tdev_p->num_vfs_exposed = number;\n+\t\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t\t \"HW caps: VFs exposed = %d\\n\",\n+\t\t\t\t\t dev_p->num_vfs_exposed);\n+\t\t\t} else if (func_p) {\n+\t\t\t\tfunc_p->num_allocd_vfs = number;\n+\t\t\t\tfunc_p->vf_base_id = logical_id;\n+\t\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t\t \"HW caps: VFs allocated = %d\\n\",\n+\t\t\t\t\t func_p->num_allocd_vfs);\n+\t\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t\t \"HW caps: VF base_id = %d\\n\",\n+\t\t\t\t\t func_p->vf_base_id);\n+\t\t\t}\n+\t\t\tbreak;\n \t\tcase ICE_AQC_CAPS_VSI:\n \t\t\tif (dev_p) {\n \t\t\t\tdev_p->num_vsi_allocd_to_host = number;\ndiff --git a/drivers/net/ethernet/intel/ice/ice_controlq.c b/drivers/net/ethernet/intel/ice/ice_controlq.c\nindex b25ce4f587f5..84c967294eaf 100644\n--- a/drivers/net/ethernet/intel/ice/ice_controlq.c\n+++ b/drivers/net/ethernet/intel/ice/ice_controlq.c\n@@ -32,6 +32,36 @@ static void ice_adminq_init_regs(struct ice_hw *hw)\n \tcq->rq.head_mask = PF_FW_ARQH_ARQH_M;\n }\n \n+/**\n+ * ice_mailbox_init_regs - Initialize Mailbox registers\n+ * @hw: pointer to the hardware structure\n+ *\n+ * This assumes the alloc_sq and alloc_rq functions have already been called\n+ */\n+static void ice_mailbox_init_regs(struct ice_hw *hw)\n+{\n+\tstruct ice_ctl_q_info *cq = &hw->mailboxq;\n+\n+\t/* set head and tail registers in our local struct */\n+\tcq->sq.head = PF_MBX_ATQH;\n+\tcq->sq.tail = PF_MBX_ATQT;\n+\tcq->sq.len = PF_MBX_ATQLEN;\n+\tcq->sq.bah = PF_MBX_ATQBAH;\n+\tcq->sq.bal = PF_MBX_ATQBAL;\n+\tcq->sq.len_mask = PF_MBX_ATQLEN_ATQLEN_M;\n+\tcq->sq.len_ena_mask = PF_MBX_ATQLEN_ATQENABLE_M;\n+\tcq->sq.head_mask = PF_MBX_ATQH_ATQH_M;\n+\n+\tcq->rq.head = PF_MBX_ARQH;\n+\tcq->rq.tail = PF_MBX_ARQT;\n+\tcq->rq.len = PF_MBX_ARQLEN;\n+\tcq->rq.bah = PF_MBX_ARQBAH;\n+\tcq->rq.bal = PF_MBX_ARQBAL;\n+\tcq->rq.len_mask = PF_MBX_ARQLEN_ARQLEN_M;\n+\tcq->rq.len_ena_mask = PF_MBX_ARQLEN_ARQENABLE_M;\n+\tcq->rq.head_mask = PF_MBX_ARQH_ARQH_M;\n+}\n+\n /**\n * ice_check_sq_alive\n * @hw: pointer to the hw struct\n@@ -639,6 +669,10 @@ static enum ice_status ice_init_ctrlq(struct ice_hw *hw, enum ice_ctl_q q_type)\n \t\tice_adminq_init_regs(hw);\n \t\tcq = &hw->adminq;\n \t\tbreak;\n+\tcase ICE_CTL_Q_MAILBOX:\n+\t\tice_mailbox_init_regs(hw);\n+\t\tcq = &hw->mailboxq;\n+\t\tbreak;\n \tdefault:\n \t\treturn ICE_ERR_PARAM;\n \t}\n@@ -696,7 +730,12 @@ enum ice_status ice_init_all_ctrlq(struct ice_hw *hw)\n \tif (ret_code)\n \t\treturn ret_code;\n \n-\treturn ice_init_check_adminq(hw);\n+\tret_code = ice_init_check_adminq(hw);\n+\tif (ret_code)\n+\t\treturn ret_code;\n+\n+\t/* Init Mailbox queue */\n+\treturn ice_init_ctrlq(hw, ICE_CTL_Q_MAILBOX);\n }\n \n /**\n@@ -714,6 +753,9 @@ static void ice_shutdown_ctrlq(struct ice_hw *hw, enum ice_ctl_q q_type)\n \t\tif (ice_check_sq_alive(hw, cq))\n \t\t\tice_aq_q_shutdown(hw, true);\n \t\tbreak;\n+\tcase ICE_CTL_Q_MAILBOX:\n+\t\tcq = &hw->mailboxq;\n+\t\tbreak;\n \tdefault:\n \t\treturn;\n \t}\n@@ -736,6 +778,8 @@ void ice_shutdown_all_ctrlq(struct ice_hw *hw)\n {\n \t/* Shutdown FW admin queue */\n \tice_shutdown_ctrlq(hw, ICE_CTL_Q_ADMIN);\n+\t/* Shutdown PF-VF Mailbox */\n+\tice_shutdown_ctrlq(hw, ICE_CTL_Q_MAILBOX);\n }\n \n /**\ndiff --git a/drivers/net/ethernet/intel/ice/ice_controlq.h b/drivers/net/ethernet/intel/ice/ice_controlq.h\nindex ea02b89243e2..437f832fd7c4 100644\n--- a/drivers/net/ethernet/intel/ice/ice_controlq.h\n+++ b/drivers/net/ethernet/intel/ice/ice_controlq.h\n@@ -8,6 +8,7 @@\n \n /* Maximum buffer lengths for all control queue types */\n #define ICE_AQ_MAX_BUF_LEN 4096\n+#define ICE_MBXQ_MAX_BUF_LEN 4096\n \n #define ICE_CTL_Q_DESC(R, i) \\\n \t(&(((struct ice_aq_desc *)((R).desc_buf.va))[i]))\n@@ -28,6 +29,7 @@\n enum ice_ctl_q {\n \tICE_CTL_Q_UNKNOWN = 0,\n \tICE_CTL_Q_ADMIN,\n+\tICE_CTL_Q_MAILBOX,\n };\n \n /* Control Queue default settings */\ndiff --git a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h\nindex 9a78d83eaa3e..c2d867b756ef 100644\n--- a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h\n+++ b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h\n@@ -29,6 +29,22 @@\n #define PF_FW_ATQLEN_ATQCRIT_M\t\t\tBIT(30)\n #define PF_FW_ATQLEN_ATQENABLE_M\t\tBIT(31)\n #define PF_FW_ATQT\t\t\t\t0x00080400\n+#define PF_MBX_ARQBAH\t\t\t\t0x0022E400\n+#define PF_MBX_ARQBAL\t\t\t\t0x0022E380\n+#define PF_MBX_ARQH\t\t\t\t0x0022E500\n+#define PF_MBX_ARQH_ARQH_M\t\t\tICE_M(0x3FF, 0)\n+#define PF_MBX_ARQLEN\t\t\t\t0x0022E480\n+#define PF_MBX_ARQLEN_ARQLEN_M\t\t\tICE_M(0x3FF, 0)\n+#define PF_MBX_ARQLEN_ARQENABLE_M\t\tBIT(31)\n+#define PF_MBX_ARQT\t\t\t\t0x0022E580\n+#define PF_MBX_ATQBAH\t\t\t\t0x0022E180\n+#define PF_MBX_ATQBAL\t\t\t\t0x0022E100\n+#define PF_MBX_ATQH\t\t\t\t0x0022E280\n+#define PF_MBX_ATQH_ATQH_M\t\t\tICE_M(0x3FF, 0)\n+#define PF_MBX_ATQLEN\t\t\t\t0x0022E200\n+#define PF_MBX_ATQLEN_ATQLEN_M\t\t\tICE_M(0x3FF, 0)\n+#define PF_MBX_ATQLEN_ATQENABLE_M\t\tBIT(31)\n+#define PF_MBX_ATQT\t\t\t\t0x0022E300\n #define GLFLXP_RXDID_FLAGS(_i, _j)\t\t(0x0045D000 + ((_i) * 4 + (_j) * 256))\n #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S\t0\n #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M\tICE_M(0x3F, 0)\n@@ -95,6 +111,11 @@\n #define PFINT_FW_CTL_ITR_INDX_S\t\t\t11\n #define PFINT_FW_CTL_ITR_INDX_M\t\t\tICE_M(0x3, 11)\n #define PFINT_FW_CTL_CAUSE_ENA_M\t\tBIT(30)\n+#define PFINT_MBX_CTL\t\t\t\t0x0016B280\n+#define PFINT_MBX_CTL_MSIX_INDX_M\t\tICE_M(0x7FF, 0)\n+#define PFINT_MBX_CTL_ITR_INDX_S\t\t11\n+#define PFINT_MBX_CTL_ITR_INDX_M\t\tICE_M(0x3, 11)\n+#define PFINT_MBX_CTL_CAUSE_ENA_M\t\tBIT(30)\n #define PFINT_OICR\t\t\t\t0x0016CA00\n #define PFINT_OICR_ECC_ERR_M\t\t\tBIT(16)\n #define PFINT_OICR_MAL_DETECT_M\t\t\tBIT(19)\ndiff --git a/drivers/net/ethernet/intel/ice/ice_main.c b/drivers/net/ethernet/intel/ice/ice_main.c\nindex 4aa6b849a6cc..59bcf5edd447 100644\n--- a/drivers/net/ethernet/intel/ice/ice_main.c\n+++ b/drivers/net/ethernet/intel/ice/ice_main.c\n@@ -711,6 +711,10 @@ static int __ice_clean_ctrlq(struct ice_pf *pf, enum ice_ctl_q q_type)\n \t\tcq = &hw->adminq;\n \t\tqtype = \"Admin\";\n \t\tbreak;\n+\tcase ICE_CTL_Q_MAILBOX:\n+\t\tcq = &hw->mailboxq;\n+\t\tqtype = \"Mailbox\";\n+\t\tbreak;\n \tdefault:\n \t\tdev_warn(&pf->pdev->dev, \"Unknown control queue type 0x%x\\n\",\n \t\t\t q_type);\n@@ -850,6 +854,28 @@ static void ice_clean_adminq_subtask(struct ice_pf *pf)\n \tice_flush(hw);\n }\n \n+/**\n+ * ice_clean_mailboxq_subtask - clean the MailboxQ rings\n+ * @pf: board private structure\n+ */\n+static void ice_clean_mailboxq_subtask(struct ice_pf *pf)\n+{\n+\tstruct ice_hw *hw = &pf->hw;\n+\n+\tif (!test_bit(__ICE_MAILBOXQ_EVENT_PENDING, pf->state))\n+\t\treturn;\n+\n+\tif (__ice_clean_ctrlq(pf, ICE_CTL_Q_MAILBOX))\n+\t\treturn;\n+\n+\tclear_bit(__ICE_MAILBOXQ_EVENT_PENDING, pf->state);\n+\n+\tif (ice_ctrlq_pending(hw, &hw->mailboxq))\n+\t\t__ice_clean_ctrlq(pf, ICE_CTL_Q_MAILBOX);\n+\n+\tice_flush(hw);\n+}\n+\n /**\n * ice_service_task_schedule - schedule the service task to wake up\n * @pf: board private structure\n@@ -1040,6 +1066,7 @@ static void ice_service_task(struct work_struct *work)\n \tice_handle_mdd_event(pf);\n \tice_watchdog_subtask(pf);\n \tice_clean_adminq_subtask(pf);\n+\tice_clean_mailboxq_subtask(pf);\n \n \t/* Clear __ICE_SERVICE_SCHED flag to allow scheduling next event */\n \tice_service_task_complete(pf);\n@@ -1050,6 +1077,7 @@ static void ice_service_task(struct work_struct *work)\n \t */\n \tif (time_after(jiffies, (start_time + pf->serv_tmr_period)) ||\n \t test_bit(__ICE_MDD_EVENT_PENDING, pf->state) ||\n+\t test_bit(__ICE_MAILBOXQ_EVENT_PENDING, pf->state) ||\n \t test_bit(__ICE_ADMINQ_EVENT_PENDING, pf->state))\n \t\tmod_timer(&pf->serv_tmr, jiffies);\n }\n@@ -1064,6 +1092,10 @@ static void ice_set_ctrlq_len(struct ice_hw *hw)\n \thw->adminq.num_sq_entries = ICE_AQ_LEN;\n \thw->adminq.rq_buf_size = ICE_AQ_MAX_BUF_LEN;\n \thw->adminq.sq_buf_size = ICE_AQ_MAX_BUF_LEN;\n+\thw->mailboxq.num_rq_entries = ICE_MBXQ_LEN;\n+\thw->mailboxq.num_sq_entries = ICE_MBXQ_LEN;\n+\thw->mailboxq.rq_buf_size = ICE_MBXQ_MAX_BUF_LEN;\n+\thw->mailboxq.sq_buf_size = ICE_MBXQ_MAX_BUF_LEN;\n }\n \n /**\n@@ -1220,6 +1252,7 @@ static irqreturn_t ice_misc_intr(int __always_unused irq, void *data)\n \tu32 oicr, ena_mask;\n \n \tset_bit(__ICE_ADMINQ_EVENT_PENDING, pf->state);\n+\tset_bit(__ICE_MAILBOXQ_EVENT_PENDING, pf->state);\n \n \toicr = rd32(hw, PFINT_OICR);\n \tena_mask = rd32(hw, PFINT_OICR_ENA);\n@@ -1406,6 +1439,11 @@ static int ice_req_irq_msix_misc(struct ice_pf *pf)\n \t PFINT_FW_CTL_CAUSE_ENA_M);\n \twr32(hw, PFINT_FW_CTL, val);\n \n+\t/* This enables Mailbox queue Interrupt causes */\n+\tval = ((pf->hw_oicr_idx & PFINT_MBX_CTL_MSIX_INDX_M) |\n+\t PFINT_MBX_CTL_CAUSE_ENA_M);\n+\twr32(hw, PFINT_MBX_CTL, val);\n+\n \titr_gran = hw->itr_gran;\n \n \twr32(hw, GLINT_ITR(ICE_RX_ITR, pf->hw_oicr_idx),\n@@ -1775,6 +1813,15 @@ static void ice_init_pf(struct ice_pf *pf)\n {\n \tbitmap_zero(pf->flags, ICE_PF_FLAGS_NBITS);\n \tset_bit(ICE_FLAG_MSIX_ENA, pf->flags);\n+#ifdef CONFIG_PCI_IOV\n+\tif (pf->hw.func_caps.common_cap.sr_iov_1_1) {\n+\t\tstruct ice_hw *hw = &pf->hw;\n+\n+\t\tset_bit(ICE_FLAG_SRIOV_CAPABLE, pf->flags);\n+\t\tpf->num_vfs_supported = min_t(int, hw->func_caps.num_allocd_vfs,\n+\t\t\t\t\t ICE_MAX_VF_COUNT);\n+\t}\n+#endif /* CONFIG_PCI_IOV */\n \n \tmutex_init(&pf->sw_mutex);\n \tmutex_init(&pf->avail_q_mutex);\ndiff --git a/drivers/net/ethernet/intel/ice/ice_type.h b/drivers/net/ethernet/intel/ice/ice_type.h\nindex f5c8de0ed0eb..6d053fb5f941 100644\n--- a/drivers/net/ethernet/intel/ice/ice_type.h\n+++ b/drivers/net/ethernet/intel/ice/ice_type.h\n@@ -84,6 +84,7 @@ enum ice_media_type {\n \n enum ice_vsi_type {\n \tICE_VSI_PF = 0,\n+\tICE_VSI_VF,\n };\n \n struct ice_link_status {\n@@ -127,6 +128,8 @@ struct ice_hw_common_caps {\n \t/* Max MTU for function or device */\n \tu16 max_mtu;\n \n+\t/* Virtualization support */\n+\tu8 sr_iov_1_1;\t\t\t/* SR-IOV enabled */\n \t/* RSS related capabilities */\n \tu16 rss_table_size;\t\t/* 512 for PFs and 64 for VFs */\n \tu8 rss_table_entry_width;\t/* RSS Entry width in bits */\n@@ -135,12 +138,15 @@ struct ice_hw_common_caps {\n /* Function specific capabilities */\n struct ice_hw_func_caps {\n \tstruct ice_hw_common_caps common_cap;\n+\tu32 num_allocd_vfs;\t\t/* Number of allocated VFs */\n+\tu32 vf_base_id;\t\t\t/* Logical ID of the first VF */\n \tu32 guaranteed_num_vsi;\n };\n \n /* Device wide capabilities */\n struct ice_hw_dev_caps {\n \tstruct ice_hw_common_caps common_cap;\n+\tu32 num_vfs_exposed;\t\t/* Total number of VFs exposed */\n \tu32 num_vsi_allocd_to_host;\t/* Excluding EMP VSI */\n };\n \n@@ -321,6 +327,7 @@ struct ice_hw {\n \n \t/* Control Queue info */\n \tstruct ice_ctl_q_info adminq;\n+\tstruct ice_ctl_q_info mailboxq;\n \n \tu8 api_branch;\t\t/* API branch version */\n \tu8 api_maj_ver;\t\t/* API major version */\n", "prefixes": [ "v2", "02/16" ] }