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GET /api/patches/972043/?format=api
{ "id": 972043, "url": "http://patchwork.ozlabs.org/api/patches/972043/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20180920002319.10971-17-anirudh.venkataramanan@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20180920002319.10971-17-anirudh.venkataramanan@intel.com>", "list_archive_url": null, "date": "2018-09-20T00:23:19", "name": "[16/16] ice: Add support for dynamic interrupt moderation", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "7368c14eb42e7fe039715f0528c04978547251b1", "submitter": { "id": 73601, "url": "http://patchwork.ozlabs.org/api/people/73601/?format=api", "name": "Anirudh Venkataramanan", "email": "anirudh.venkataramanan@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20180920002319.10971-17-anirudh.venkataramanan@intel.com/mbox/", "series": [ { "id": 66525, "url": "http://patchwork.ozlabs.org/api/series/66525/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=66525", "date": "2018-09-20T00:23:03", "name": "Implementation updates for ice", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/66525/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/972043/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/972043/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.138; helo=whitealder.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 42FyBt5Mlqz9sBJ\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 20 Sep 2018 10:23:50 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 58F7B88209;\n\tThu, 20 Sep 2018 00:23:49 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id S-foy18zhYrC; Thu, 20 Sep 2018 00:23:43 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 1C186882D0;\n\tThu, 20 Sep 2018 00:23:36 +0000 (UTC)", "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\tby ash.osuosl.org (Postfix) with ESMTP id 8D3661C08AF\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 20 Sep 2018 00:23:32 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id 89CCC201F5\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 20 Sep 2018 00:23:32 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id ugUdfLPb7iY6 for <intel-wired-lan@lists.osuosl.org>;\n\tThu, 20 Sep 2018 00:23:29 +0000 (UTC)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n\tby silver.osuosl.org (Postfix) with ESMTPS id 3BF093096D\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 20 Sep 2018 00:23:25 +0000 (UTC)", "from fmsmga006.fm.intel.com ([10.253.24.20])\n\tby fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t19 Sep 2018 17:23:24 -0700", "from shasta.jf.intel.com ([10.166.241.11])\n\tby fmsmga006.fm.intel.com with ESMTP; 19 Sep 2018 17:23:20 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.53,396,1531810800\"; d=\"scan'208\";a=\"265057708\"", "From": "Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Wed, 19 Sep 2018 17:23:19 -0700", "Message-Id": "<20180920002319.10971-17-anirudh.venkataramanan@intel.com>", "X-Mailer": "git-send-email 2.14.3", "In-Reply-To": "<20180920002319.10971-1-anirudh.venkataramanan@intel.com>", "References": "<20180920002319.10971-1-anirudh.venkataramanan@intel.com>", "Subject": "[Intel-wired-lan] [PATCH 16/16] ice: Add support for dynamic\n\tinterrupt moderation", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.24", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "From: Brett Creeley <brett.creeley@intel.com>\n\nCurrently there is no support for dynamic interrupt moderation. This\npatch adds some initial code to support this. The following changes\nwere made:\n\n1. Currently we are using multiple members to store the interrupt\n granularity (itr_gran_25/50/100/200). This is not necessary because\n we can query the device to determine what the interrupt granularity\n should be set to, done by a new function ice_get_itr_intrl_gran.\n\n2. Added intrl to ice_q_vector structure to support interrupt rate\n limiting.\n\n3. Added the function ice_intrl_usecs_to_reg for converting to a value\n in usecs that the device understands.\n\n4. Added call to write to the GLINT_RATE register. Disable intrl by\n default for now.\n\n5. Changed rx/tx_itr_setting to itr_setting because having both seems\n redundant because a ring is either tx or rx.\n\n6. Initialize itr_setting for both tx/rx rings in ice_vsi_alloc_rings()\n\nSigned-off-by: Brett Creeley <brett.creeley@intel.com>\nSigned-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>\n---\n drivers/net/ethernet/intel/ice/ice.h | 4 +++\n drivers/net/ethernet/intel/ice/ice_common.c | 41 ++++++++++++++++++++++---\n drivers/net/ethernet/intel/ice/ice_hw_autogen.h | 5 +++\n drivers/net/ethernet/intel/ice/ice_lib.c | 29 +++++++++++++++--\n drivers/net/ethernet/intel/ice/ice_main.c | 2 +-\n drivers/net/ethernet/intel/ice/ice_txrx.h | 17 ++++++----\n drivers/net/ethernet/intel/ice/ice_type.h | 28 +++++++++++------\n 7 files changed, 102 insertions(+), 24 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/ice/ice.h b/drivers/net/ethernet/intel/ice/ice.h\nindex 88d13157ab5b..28002936a0cb 100644\n--- a/drivers/net/ethernet/intel/ice/ice.h\n+++ b/drivers/net/ethernet/intel/ice/ice.h\n@@ -230,6 +230,10 @@ struct ice_q_vector {\n \tu8 num_ring_tx;\t\t\t/* total number of tx rings in vector */\n \tu8 num_ring_rx;\t\t\t/* total number of rx rings in vector */\n \tchar name[ICE_INT_NAME_STR_LEN];\n+\t/* in usecs, need to use ice_intrl_to_usecs_reg() before writing this\n+\t * value to the device\n+\t */\n+\tu8 intrl;\n } ____cacheline_internodealigned_in_smp;\n \n enum ice_pf_flags {\ndiff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c\nindex 78315bb6431c..e9e5c601b321 100644\n--- a/drivers/net/ethernet/intel/ice/ice_common.c\n+++ b/drivers/net/ethernet/intel/ice/ice_common.c\n@@ -597,6 +597,39 @@ void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf)\n \tice_debug(hw, ICE_DBG_AQ_MSG, \"[ FW Log Msg End ]\\n\");\n }\n \n+/**\n+ * ice_get_itr_intrl_gran - determine int/intrl granularity\n+ * @hw: pointer to the hw struct\n+ *\n+ * Determines the itr/intrl granularities based on the maximum aggregate\n+ * bandwidth according to the device's configuration during power-on.\n+ */\n+static enum ice_status ice_get_itr_intrl_gran(struct ice_hw *hw)\n+{\n+\tu8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &\n+\t\t\t GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>\n+\t\t\tGL_PWR_MODE_CTL_CAR_MAX_BW_S;\n+\n+\tswitch (max_agg_bw) {\n+\tcase ICE_MAX_AGG_BW_200G:\n+\tcase ICE_MAX_AGG_BW_100G:\n+\tcase ICE_MAX_AGG_BW_50G:\n+\t\thw->itr_gran = ICE_ITR_GRAN_ABOVE_25;\n+\t\thw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;\n+\t\tbreak;\n+\tcase ICE_MAX_AGG_BW_25G:\n+\t\thw->itr_gran = ICE_ITR_GRAN_MAX_25;\n+\t\thw->intrl_gran = ICE_INTRL_GRAN_MAX_25;\n+\t\tbreak;\n+\tdefault:\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t \"Failed to determine itr/intrl granularity\\n\");\n+\t\treturn ICE_ERR_CFG;\n+\t}\n+\n+\treturn 0;\n+}\n+\n /**\n * ice_init_hw - main hardware initialization routine\n * @hw: pointer to the hardware structure\n@@ -621,11 +654,9 @@ enum ice_status ice_init_hw(struct ice_hw *hw)\n \tif (status)\n \t\treturn status;\n \n-\t/* set these values to minimum allowed */\n-\thw->itr_gran_200 = ICE_ITR_GRAN_MIN_200;\n-\thw->itr_gran_100 = ICE_ITR_GRAN_MIN_100;\n-\thw->itr_gran_50 = ICE_ITR_GRAN_MIN_50;\n-\thw->itr_gran_25 = ICE_ITR_GRAN_MIN_25;\n+\tstatus = ice_get_itr_intrl_gran(hw);\n+\tif (status)\n+\t\treturn status;\n \n \tstatus = ice_init_all_ctrlq(hw);\n \tif (status)\ndiff --git a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h\nindex 88f11498804b..9a78d83eaa3e 100644\n--- a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h\n+++ b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h\n@@ -88,6 +88,8 @@\n #define GLINT_DYN_CTL_SW_ITR_INDX_M\t\tICE_M(0x3, 25)\n #define GLINT_DYN_CTL_INTENA_MSK_M\t\tBIT(31)\n #define GLINT_ITR(_i, _INT)\t\t\t(0x00154000 + ((_i) * 8192 + (_INT) * 4))\n+#define GLINT_RATE(_INT)\t\t\t(0x0015A000 + ((_INT) * 4))\n+#define GLINT_RATE_INTRL_ENA_M\t\t\tBIT(6)\n #define PFINT_FW_CTL\t\t\t\t0x0016C800\n #define PFINT_FW_CTL_MSIX_INDX_M\t\tICE_M(0x7FF, 0)\n #define PFINT_FW_CTL_ITR_INDX_S\t\t\t11\n@@ -173,6 +175,9 @@\n #define PF_FUNC_RID\t\t\t\t0x0009E880\n #define PF_FUNC_RID_FUNC_NUM_S\t\t\t0\n #define PF_FUNC_RID_FUNC_NUM_M\t\t\tICE_M(0x7, 0)\n+#define GL_PWR_MODE_CTL\t\t\t\t0x000B820C\n+#define GL_PWR_MODE_CTL_CAR_MAX_BW_S\t\t30\n+#define GL_PWR_MODE_CTL_CAR_MAX_BW_M\t\tICE_M(0x3, 30)\n #define GLPRT_BPRCH(_i)\t\t\t\t(0x00381384 + ((_i) * 8))\n #define GLPRT_BPRCL(_i)\t\t\t\t(0x00381380 + ((_i) * 8))\n #define GLPRT_BPTCH(_i)\t\t\t\t(0x00381244 + ((_i) * 8))\ndiff --git a/drivers/net/ethernet/intel/ice/ice_lib.c b/drivers/net/ethernet/intel/ice/ice_lib.c\nindex 0d341652fb92..d67d7005916c 100644\n--- a/drivers/net/ethernet/intel/ice/ice_lib.c\n+++ b/drivers/net/ethernet/intel/ice/ice_lib.c\n@@ -1139,6 +1139,7 @@ static int ice_vsi_alloc_rings(struct ice_vsi *vsi)\n \t\tring->vsi = vsi;\n \t\tring->dev = &pf->pdev->dev;\n \t\tring->count = vsi->num_desc;\n+\t\tring->itr_setting = ICE_DFLT_TX_ITR;\n \t\tvsi->tx_rings[i] = ring;\n \t}\n \n@@ -1158,6 +1159,7 @@ static int ice_vsi_alloc_rings(struct ice_vsi *vsi)\n \t\tring->netdev = vsi->netdev;\n \t\tring->dev = &pf->pdev->dev;\n \t\tring->count = vsi->num_desc;\n+\t\tring->itr_setting = ICE_DFLT_RX_ITR;\n \t\tvsi->rx_rings[i] = ring;\n \t}\n \n@@ -1595,6 +1597,23 @@ int ice_vsi_cfg_txqs(struct ice_vsi *vsi)\n \treturn err;\n }\n \n+/**\n+ * ice_intrl_usec_to_reg - convert interrupt rate limit to register value\n+ * @intrl: interrupt rate limit in usecs\n+ * @gran: interrupt rate limit granularity in usecs\n+ *\n+ * This function converts a decimal interrupt rate limit in usecs to the format\n+ * expected by firmware.\n+ */\n+static u32 ice_intrl_usec_to_reg(u8 intrl, u8 gran)\n+{\n+\tu32 val = intrl / gran;\n+\n+\tif (val)\n+\t\treturn val | GLINT_RATE_INTRL_ENA_M;\n+\treturn 0;\n+}\n+\n /**\n * ice_vsi_cfg_msix - MSIX mode Interrupt Config in the HW\n * @vsi: the VSI being configured\n@@ -1611,23 +1630,27 @@ void ice_vsi_cfg_msix(struct ice_vsi *vsi)\n \tfor (i = 0; i < vsi->num_q_vectors; i++, vector++) {\n \t\tstruct ice_q_vector *q_vector = vsi->q_vectors[i];\n \n-\t\titr_gran = hw->itr_gran_200;\n+\t\titr_gran = hw->itr_gran;\n+\n+\t\tq_vector->intrl = ICE_DFLT_INTRL;\n \n \t\tif (q_vector->num_ring_rx) {\n \t\t\tq_vector->rx.itr =\n-\t\t\t\tITR_TO_REG(vsi->rx_rings[rxq]->rx_itr_setting,\n+\t\t\t\tITR_TO_REG(vsi->rx_rings[rxq]->itr_setting,\n \t\t\t\t\t itr_gran);\n \t\t\tq_vector->rx.latency_range = ICE_LOW_LATENCY;\n \t\t}\n \n \t\tif (q_vector->num_ring_tx) {\n \t\t\tq_vector->tx.itr =\n-\t\t\t\tITR_TO_REG(vsi->tx_rings[txq]->tx_itr_setting,\n+\t\t\t\tITR_TO_REG(vsi->tx_rings[txq]->itr_setting,\n \t\t\t\t\t itr_gran);\n \t\t\tq_vector->tx.latency_range = ICE_LOW_LATENCY;\n \t\t}\n \t\twr32(hw, GLINT_ITR(ICE_RX_ITR, vector), q_vector->rx.itr);\n \t\twr32(hw, GLINT_ITR(ICE_TX_ITR, vector), q_vector->tx.itr);\n+\t\twr32(hw, GLINT_RATE(vector),\n+\t\t ice_intrl_usec_to_reg(q_vector->intrl, hw->intrl_gran));\n \n \t\t/* Both Transmit Queue Interrupt Cause Control register\n \t\t * and Receive Queue Interrupt Cause control register\ndiff --git a/drivers/net/ethernet/intel/ice/ice_main.c b/drivers/net/ethernet/intel/ice/ice_main.c\nindex e244317915a3..4aa6b849a6cc 100644\n--- a/drivers/net/ethernet/intel/ice/ice_main.c\n+++ b/drivers/net/ethernet/intel/ice/ice_main.c\n@@ -1406,7 +1406,7 @@ static int ice_req_irq_msix_misc(struct ice_pf *pf)\n \t PFINT_FW_CTL_CAUSE_ENA_M);\n \twr32(hw, PFINT_FW_CTL, val);\n \n-\titr_gran = hw->itr_gran_200;\n+\titr_gran = hw->itr_gran;\n \n \twr32(hw, GLINT_ITR(ICE_RX_ITR, pf->hw_oicr_idx),\n \t ITR_TO_REG(ICE_ITR_8K, itr_gran));\ndiff --git a/drivers/net/ethernet/intel/ice/ice_txrx.h b/drivers/net/ethernet/intel/ice/ice_txrx.h\nindex 839fd9ff6043..a9b92974e041 100644\n--- a/drivers/net/ethernet/intel/ice/ice_txrx.h\n+++ b/drivers/net/ethernet/intel/ice/ice_txrx.h\n@@ -104,10 +104,16 @@ enum ice_rx_dtype {\n #define ICE_RX_ITR\tICE_IDX_ITR0\n #define ICE_TX_ITR\tICE_IDX_ITR1\n #define ICE_ITR_DYNAMIC\t0x8000 /* use top bit as a flag */\n-#define ICE_ITR_8K\t0x003E\n+#define ICE_ITR_8K\t125\n+#define ICE_DFLT_TX_ITR\tICE_ITR_8K\n+#define ICE_DFLT_RX_ITR\tICE_ITR_8K\n+/* apply ITR granularity translation to program the register. itr_gran is either\n+ * 2 or 4 usecs so we need to divide by 2 first then shift by that value\n+ */\n+#define ITR_TO_REG(val, itr_gran) (((val) & ~ICE_ITR_DYNAMIC) >> \\\n+\t\t\t\t ((itr_gran) / 2))\n \n-/* apply ITR HW granularity translation to program the HW registers */\n-#define ITR_TO_REG(val, itr_gran) (((val) & ~ICE_ITR_DYNAMIC) >> (itr_gran))\n+#define ICE_DFLT_INTRL\t0\n \n /* Legacy or Advanced Mode Queue */\n #define ICE_TX_ADVANCED\t0\n@@ -130,12 +136,11 @@ struct ice_ring {\n \tu32 txq_teid;\t\t\t/* Added Tx queue TEID */\n \n \t/* high bit set means dynamic, use accessor routines to read/write.\n-\t * hardware supports 2us/1us resolution for the ITR registers.\n+\t * hardware supports 4us/2us resolution for the ITR registers.\n \t * these values always store the USER setting, and must be converted\n \t * before programming to a register.\n \t */\n-\tu16 rx_itr_setting;\n-\tu16 tx_itr_setting;\n+\tu16 itr_setting;\n \n \tu16 count;\t\t\t/* Number of descriptors */\n \tu16 reg_idx;\t\t\t/* HW register index of the ring */\ndiff --git a/drivers/net/ethernet/intel/ice/ice_type.h b/drivers/net/ethernet/intel/ice/ice_type.h\nindex 87930f68d3fb..f5c8de0ed0eb 100644\n--- a/drivers/net/ethernet/intel/ice/ice_type.h\n+++ b/drivers/net/ethernet/intel/ice/ice_type.h\n@@ -333,16 +333,26 @@ struct ice_hw {\n \tu32 fw_build;\t\t/* firmware build number */\n \n \tstruct ice_fw_log_cfg fw_log;\n-\t/* minimum allowed value for different speeds */\n-#define ICE_ITR_GRAN_MIN_200\t1\n-#define ICE_ITR_GRAN_MIN_100\t1\n-#define ICE_ITR_GRAN_MIN_50\t2\n-#define ICE_ITR_GRAN_MIN_25\t4\n+\n+/* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL\n+ * register. Used for determining the itr/intrl granularity during\n+ * initialization.\n+ */\n+#define ICE_MAX_AGG_BW_200G\t0x0\n+#define ICE_MAX_AGG_BW_100G\t0X1\n+#define ICE_MAX_AGG_BW_50G\t0x2\n+#define ICE_MAX_AGG_BW_25G\t0x3\n+\t/* ITR granularity for different speeds */\n+#define ICE_ITR_GRAN_ABOVE_25\t2\n+#define ICE_ITR_GRAN_MAX_25\t4\n \t/* ITR granularity in 1 us */\n-\tu8 itr_gran_200;\n-\tu8 itr_gran_100;\n-\tu8 itr_gran_50;\n-\tu8 itr_gran_25;\n+\tu8 itr_gran;\n+\t/* INTRL granularity for different speeds */\n+#define ICE_INTRL_GRAN_ABOVE_25\t4\n+#define ICE_INTRL_GRAN_MAX_25\t8\n+\t/* INTRL granularity in 1 us */\n+\tu8 intrl_gran;\n+\n \tu8 ucast_shared;\t/* true if VSIs can share unicast addr */\n \n };\n", "prefixes": [ "16/16" ] }