Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/970206/?format=api
{ "id": 970206, "url": "http://patchwork.ozlabs.org/api/patches/970206/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20180915003757.169108-3-jesse.brandeburg@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20180915003757.169108-3-jesse.brandeburg@intel.com>", "list_archive_url": null, "date": "2018-09-15T00:37:45", "name": "[net-next,v2,02/14] iavf: diet and reformat", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "d58a62ba1b94976050426d9b80622d0d65c18905", "submitter": { "id": 189, "url": "http://patchwork.ozlabs.org/api/people/189/?format=api", "name": "Jesse Brandeburg", "email": "jesse.brandeburg@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20180915003757.169108-3-jesse.brandeburg@intel.com/mbox/", "series": [ { "id": 65816, "url": "http://patchwork.ozlabs.org/api/series/65816/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=65816", "date": "2018-09-15T00:37:43", "name": "[net-next,v2,01/14] intel-ethernet: rename i40evf to iavf", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/65816/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/970206/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/970206/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.133; helo=hemlock.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 42C7DT4z1pz9sCT\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 15 Sep 2018 20:00:25 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 6680388603;\n\tSat, 15 Sep 2018 10:00:23 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 9XnjvGSoQp2r; Sat, 15 Sep 2018 10:00:15 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id D1A7B884FA;\n\tSat, 15 Sep 2018 10:00:15 +0000 (UTC)", "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\tby ash.osuosl.org (Postfix) with ESMTP id 80FED1C2E93\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tSat, 15 Sep 2018 00:38:21 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 6E8DA88571\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tSat, 15 Sep 2018 00:38:21 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id mBApO8dWvRUD for <intel-wired-lan@lists.osuosl.org>;\n\tSat, 15 Sep 2018 00:37:58 +0000 (UTC)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n\tby whitealder.osuosl.org (Postfix) with ESMTPS id 377438855F\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tSat, 15 Sep 2018 00:37:58 +0000 (UTC)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n\tby fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t14 Sep 2018 17:37:58 -0700", "from jfsjbrandeb002.jf.intel.com ([10.166.241.63])\n\tby fmsmga001.fm.intel.com with ESMTP; 14 Sep 2018 17:37:57 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.53,375,1531810800\"; d=\"scan'208\";a=\"90189546\"", "From": "Jesse Brandeburg <jesse.brandeburg@intel.com>", "To": "netdev@vger.kernel.org,\n\tintel-wired-lan@lists.osuosl.org", "Date": "Fri, 14 Sep 2018 17:37:45 -0700", "Message-Id": "<20180915003757.169108-3-jesse.brandeburg@intel.com>", "X-Mailer": "git-send-email 2.14.4", "In-Reply-To": "<20180915003757.169108-1-jesse.brandeburg@intel.com>", "References": "<20180915003757.169108-1-jesse.brandeburg@intel.com>", "X-Mailman-Approved-At": "Sat, 15 Sep 2018 10:00:15 +0000", "Subject": "[Intel-wired-lan] [PATCH net-next v2 02/14] iavf: diet and reformat", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.24", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "Remove a bunch of unused code and reformat a few lines. Also\nremove some now un-necessary files.\n\nSigned-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>\n---\n drivers/net/ethernet/intel/iavf/i40e_adminq.c | 27 -\n drivers/net/ethernet/intel/iavf/i40e_adminq_cmd.h | 2277 +--------------------\n drivers/net/ethernet/intel/iavf/i40e_common.c | 337 ---\n drivers/net/ethernet/intel/iavf/i40e_hmc.h | 215 --\n drivers/net/ethernet/intel/iavf/i40e_lan_hmc.h | 158 --\n drivers/net/ethernet/intel/iavf/i40e_prototype.h | 65 +-\n drivers/net/ethernet/intel/iavf/i40e_register.h | 245 ---\n drivers/net/ethernet/intel/iavf/i40e_type.h | 783 +------\n 8 files changed, 50 insertions(+), 4057 deletions(-)\n delete mode 100644 drivers/net/ethernet/intel/iavf/i40e_hmc.h\n delete mode 100644 drivers/net/ethernet/intel/iavf/i40e_lan_hmc.h", "diff": "diff --git a/drivers/net/ethernet/intel/iavf/i40e_adminq.c b/drivers/net/ethernet/intel/iavf/i40e_adminq.c\nindex 21a0dbf6ccf6..32e0e2d9cdc5 100644\n--- a/drivers/net/ethernet/intel/iavf/i40e_adminq.c\n+++ b/drivers/net/ethernet/intel/iavf/i40e_adminq.c\n@@ -7,16 +7,6 @@\n #include \"i40e_adminq.h\"\n #include \"i40e_prototype.h\"\n \n-/**\n- * i40e_is_nvm_update_op - return true if this is an NVM update operation\n- * @desc: API request descriptor\n- **/\n-static inline bool i40e_is_nvm_update_op(struct i40e_aq_desc *desc)\n-{\n-\treturn (desc->opcode == i40e_aqc_opc_nvm_erase) ||\n-\t (desc->opcode == i40e_aqc_opc_nvm_update);\n-}\n-\n /**\n * i40e_adminq_init_regs - Initialize AdminQ registers\n * @hw: pointer to the hardware structure\n@@ -569,9 +559,6 @@ i40e_status i40evf_shutdown_adminq(struct i40e_hw *hw)\n \ti40e_shutdown_asq(hw);\n \ti40e_shutdown_arq(hw);\n \n-\tif (hw->nvm_buff.va)\n-\t\ti40e_free_virt_mem(hw, &hw->nvm_buff);\n-\n \treturn ret_code;\n }\n \n@@ -951,17 +938,3 @@ i40e_status i40evf_clean_arq_element(struct i40e_hw *hw,\n \n \treturn ret_code;\n }\n-\n-void i40evf_resume_aq(struct i40e_hw *hw)\n-{\n-\t/* Registers are reset after PF reset */\n-\thw->aq.asq.next_to_use = 0;\n-\thw->aq.asq.next_to_clean = 0;\n-\n-\ti40e_config_asq_regs(hw);\n-\n-\thw->aq.arq.next_to_use = 0;\n-\thw->aq.arq.next_to_clean = 0;\n-\n-\ti40e_config_arq_regs(hw);\n-}\ndiff --git a/drivers/net/ethernet/intel/iavf/i40e_adminq_cmd.h b/drivers/net/ethernet/intel/iavf/i40e_adminq_cmd.h\nindex 5fd8529465d4..493bdc5331f7 100644\n--- a/drivers/net/ethernet/intel/iavf/i40e_adminq_cmd.h\n+++ b/drivers/net/ethernet/intel/iavf/i40e_adminq_cmd.h\n@@ -307,33 +307,6 @@ enum i40e_admin_queue_opc {\n */\n #define I40E_CHECK_CMD_LENGTH(X)\tI40E_CHECK_STRUCT_LEN(16, X)\n \n-/* internal (0x00XX) commands */\n-\n-/* Get version (direct 0x0001) */\n-struct i40e_aqc_get_version {\n-\t__le32 rom_ver;\n-\t__le32 fw_build;\n-\t__le16 fw_major;\n-\t__le16 fw_minor;\n-\t__le16 api_major;\n-\t__le16 api_minor;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);\n-\n-/* Send driver version (indirect 0x0002) */\n-struct i40e_aqc_driver_version {\n-\tu8\tdriver_major_ver;\n-\tu8\tdriver_minor_ver;\n-\tu8\tdriver_build_ver;\n-\tu8\tdriver_subbuild_ver;\n-\tu8\treserved[4];\n-\t__le32\taddress_high;\n-\t__le32\taddress_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);\n-\n /* Queue Shutdown (direct 0x0003) */\n struct i40e_aqc_queue_shutdown {\n \t__le32\tdriver_unloading;\n@@ -343,490 +316,6 @@ struct i40e_aqc_queue_shutdown {\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);\n \n-/* Set PF context (0x0004, direct) */\n-struct i40e_aqc_set_pf_context {\n-\tu8\tpf_id;\n-\tu8\treserved[15];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);\n-\n-/* Request resource ownership (direct 0x0008)\n- * Release resource ownership (direct 0x0009)\n- */\n-#define I40E_AQ_RESOURCE_NVM\t\t\t1\n-#define I40E_AQ_RESOURCE_SDP\t\t\t2\n-#define I40E_AQ_RESOURCE_ACCESS_READ\t\t1\n-#define I40E_AQ_RESOURCE_ACCESS_WRITE\t\t2\n-#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT\t3000\n-#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT\t180000\n-\n-struct i40e_aqc_request_resource {\n-\t__le16\tresource_id;\n-\t__le16\taccess_type;\n-\t__le32\ttimeout;\n-\t__le32\tresource_number;\n-\tu8\treserved[4];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);\n-\n-/* Get function capabilities (indirect 0x000A)\n- * Get device capabilities (indirect 0x000B)\n- */\n-struct i40e_aqc_list_capabilites {\n-\tu8 command_flags;\n-#define I40E_AQ_LIST_CAP_PF_INDEX_EN\t1\n-\tu8 pf_index;\n-\tu8 reserved[2];\n-\t__le32 count;\n-\t__le32 addr_high;\n-\t__le32 addr_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);\n-\n-struct i40e_aqc_list_capabilities_element_resp {\n-\t__le16\tid;\n-\tu8\tmajor_rev;\n-\tu8\tminor_rev;\n-\t__le32\tnumber;\n-\t__le32\tlogical_id;\n-\t__le32\tphys_id;\n-\tu8\treserved[16];\n-};\n-\n-/* list of caps */\n-\n-#define I40E_AQ_CAP_ID_SWITCH_MODE\t0x0001\n-#define I40E_AQ_CAP_ID_MNG_MODE\t\t0x0002\n-#define I40E_AQ_CAP_ID_NPAR_ACTIVE\t0x0003\n-#define I40E_AQ_CAP_ID_OS2BMC_CAP\t0x0004\n-#define I40E_AQ_CAP_ID_FUNCTIONS_VALID\t0x0005\n-#define I40E_AQ_CAP_ID_ALTERNATE_RAM\t0x0006\n-#define I40E_AQ_CAP_ID_WOL_AND_PROXY\t0x0008\n-#define I40E_AQ_CAP_ID_SRIOV\t\t0x0012\n-#define I40E_AQ_CAP_ID_VF\t\t0x0013\n-#define I40E_AQ_CAP_ID_VMDQ\t\t0x0014\n-#define I40E_AQ_CAP_ID_8021QBG\t\t0x0015\n-#define I40E_AQ_CAP_ID_8021QBR\t\t0x0016\n-#define I40E_AQ_CAP_ID_VSI\t\t0x0017\n-#define I40E_AQ_CAP_ID_DCB\t\t0x0018\n-#define I40E_AQ_CAP_ID_FCOE\t\t0x0021\n-#define I40E_AQ_CAP_ID_ISCSI\t\t0x0022\n-#define I40E_AQ_CAP_ID_RSS\t\t0x0040\n-#define I40E_AQ_CAP_ID_RXQ\t\t0x0041\n-#define I40E_AQ_CAP_ID_TXQ\t\t0x0042\n-#define I40E_AQ_CAP_ID_MSIX\t\t0x0043\n-#define I40E_AQ_CAP_ID_VF_MSIX\t\t0x0044\n-#define I40E_AQ_CAP_ID_FLOW_DIRECTOR\t0x0045\n-#define I40E_AQ_CAP_ID_1588\t\t0x0046\n-#define I40E_AQ_CAP_ID_IWARP\t\t0x0051\n-#define I40E_AQ_CAP_ID_LED\t\t0x0061\n-#define I40E_AQ_CAP_ID_SDP\t\t0x0062\n-#define I40E_AQ_CAP_ID_MDIO\t\t0x0063\n-#define I40E_AQ_CAP_ID_WSR_PROT\t\t0x0064\n-#define I40E_AQ_CAP_ID_NVM_MGMT\t\t0x0080\n-#define I40E_AQ_CAP_ID_FLEX10\t\t0x00F1\n-#define I40E_AQ_CAP_ID_CEM\t\t0x00F2\n-\n-/* Set CPPM Configuration (direct 0x0103) */\n-struct i40e_aqc_cppm_configuration {\n-\t__le16\tcommand_flags;\n-#define I40E_AQ_CPPM_EN_LTRC\t0x0800\n-#define I40E_AQ_CPPM_EN_DMCTH\t0x1000\n-#define I40E_AQ_CPPM_EN_DMCTLX\t0x2000\n-#define I40E_AQ_CPPM_EN_HPTC\t0x4000\n-#define I40E_AQ_CPPM_EN_DMARC\t0x8000\n-\t__le16\tttlx;\n-\t__le32\tdmacr;\n-\t__le16\tdmcth;\n-\tu8\thptc;\n-\tu8\treserved;\n-\t__le32\tpfltrc;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);\n-\n-/* Set ARP Proxy command / response (indirect 0x0104) */\n-struct i40e_aqc_arp_proxy_data {\n-\t__le16\tcommand_flags;\n-#define I40E_AQ_ARP_INIT_IPV4\t0x0800\n-#define I40E_AQ_ARP_UNSUP_CTL\t0x1000\n-#define I40E_AQ_ARP_ENA\t\t0x2000\n-#define I40E_AQ_ARP_ADD_IPV4\t0x4000\n-#define I40E_AQ_ARP_DEL_IPV4\t0x8000\n-\t__le16\ttable_id;\n-\t__le32\tenabled_offloads;\n-#define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE\t0x00000020\n-#define I40E_AQ_ARP_OFFLOAD_ENABLE\t\t0x00000800\n-\t__le32\tip_addr;\n-\tu8\tmac_addr[6];\n-\tu8\treserved[2];\n-};\n-\n-I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);\n-\n-/* Set NS Proxy Table Entry Command (indirect 0x0105) */\n-struct i40e_aqc_ns_proxy_data {\n-\t__le16\ttable_idx_mac_addr_0;\n-\t__le16\ttable_idx_mac_addr_1;\n-\t__le16\ttable_idx_ipv6_0;\n-\t__le16\ttable_idx_ipv6_1;\n-\t__le16\tcontrol;\n-#define I40E_AQ_NS_PROXY_ADD_0\t\t0x0001\n-#define I40E_AQ_NS_PROXY_DEL_0\t\t0x0002\n-#define I40E_AQ_NS_PROXY_ADD_1\t\t0x0004\n-#define I40E_AQ_NS_PROXY_DEL_1\t\t0x0008\n-#define I40E_AQ_NS_PROXY_ADD_IPV6_0\t0x0010\n-#define I40E_AQ_NS_PROXY_DEL_IPV6_0\t0x0020\n-#define I40E_AQ_NS_PROXY_ADD_IPV6_1\t0x0040\n-#define I40E_AQ_NS_PROXY_DEL_IPV6_1\t0x0080\n-#define I40E_AQ_NS_PROXY_COMMAND_SEQ\t0x0100\n-#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL\t0x0200\n-#define I40E_AQ_NS_PROXY_INIT_MAC_TBL\t0x0400\n-#define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE\t0x0800\n-#define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE\t0x1000\n-\tu8\tmac_addr_0[6];\n-\tu8\tmac_addr_1[6];\n-\tu8\tlocal_mac_addr[6];\n-\tu8\tipv6_addr_0[16]; /* Warning! spec specifies BE byte order */\n-\tu8\tipv6_addr_1[16];\n-};\n-\n-I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);\n-\n-/* Manage LAA Command (0x0106) - obsolete */\n-struct i40e_aqc_mng_laa {\n-\t__le16\tcommand_flags;\n-#define I40E_AQ_LAA_FLAG_WR\t0x8000\n-\tu8\treserved[2];\n-\t__le32\tsal;\n-\t__le16\tsah;\n-\tu8\treserved2[6];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);\n-\n-/* Manage MAC Address Read Command (indirect 0x0107) */\n-struct i40e_aqc_mac_address_read {\n-\t__le16\tcommand_flags;\n-#define I40E_AQC_LAN_ADDR_VALID\t\t0x10\n-#define I40E_AQC_SAN_ADDR_VALID\t\t0x20\n-#define I40E_AQC_PORT_ADDR_VALID\t0x40\n-#define I40E_AQC_WOL_ADDR_VALID\t\t0x80\n-#define I40E_AQC_MC_MAG_EN_VALID\t0x100\n-#define I40E_AQC_ADDR_VALID_MASK\t0x3F0\n-\tu8\treserved[6];\n-\t__le32\taddr_high;\n-\t__le32\taddr_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);\n-\n-struct i40e_aqc_mac_address_read_data {\n-\tu8 pf_lan_mac[6];\n-\tu8 pf_san_mac[6];\n-\tu8 port_mac[6];\n-\tu8 pf_wol_mac[6];\n-};\n-\n-I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);\n-\n-/* Manage MAC Address Write Command (0x0108) */\n-struct i40e_aqc_mac_address_write {\n-\t__le16\tcommand_flags;\n-#define I40E_AQC_WRITE_TYPE_LAA_ONLY\t0x0000\n-#define I40E_AQC_WRITE_TYPE_LAA_WOL\t0x4000\n-#define I40E_AQC_WRITE_TYPE_PORT\t0x8000\n-#define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG\t0xC000\n-#define I40E_AQC_WRITE_TYPE_MASK\t0xC000\n-\n-\t__le16\tmac_sah;\n-\t__le32\tmac_sal;\n-\tu8\treserved[8];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);\n-\n-/* PXE commands (0x011x) */\n-\n-/* Clear PXE Command and response (direct 0x0110) */\n-struct i40e_aqc_clear_pxe {\n-\tu8\trx_cnt;\n-\tu8\treserved[15];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);\n-\n-/* Set WoL Filter (0x0120) */\n-\n-struct i40e_aqc_set_wol_filter {\n-\t__le16 filter_index;\n-#define I40E_AQC_MAX_NUM_WOL_FILTERS\t8\n-#define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT\t15\n-#define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK\t(0x1 << \\\n-\t\tI40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT)\n-\n-#define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT\t\t0\n-#define I40E_AQC_SET_WOL_FILTER_INDEX_MASK\t(0x7 << \\\n-\t\tI40E_AQC_SET_WOL_FILTER_INDEX_SHIFT)\n-\t__le16 cmd_flags;\n-#define I40E_AQC_SET_WOL_FILTER\t\t\t\t0x8000\n-#define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL\t\t0x4000\n-#define I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR\t0x2000\n-#define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR\t\t0\n-#define I40E_AQC_SET_WOL_FILTER_ACTION_SET\t\t1\n-\t__le16 valid_flags;\n-#define I40E_AQC_SET_WOL_FILTER_ACTION_VALID\t\t0x8000\n-#define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID\t0x4000\n-\tu8 reserved[2];\n-\t__le32\taddress_high;\n-\t__le32\taddress_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter);\n-\n-struct i40e_aqc_set_wol_filter_data {\n-\tu8 filter[128];\n-\tu8 mask[16];\n-};\n-\n-I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data);\n-\n-/* Get Wake Reason (0x0121) */\n-\n-struct i40e_aqc_get_wake_reason_completion {\n-\tu8 reserved_1[2];\n-\t__le16 wake_reason;\n-#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT\t0\n-#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \\\n-\t\tI40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT)\n-#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT\t8\n-#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK\t(0xFF << \\\n-\t\tI40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT)\n-\tu8 reserved_2[12];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion);\n-\n-/* Switch configuration commands (0x02xx) */\n-\n-/* Used by many indirect commands that only pass an seid and a buffer in the\n- * command\n- */\n-struct i40e_aqc_switch_seid {\n-\t__le16\tseid;\n-\tu8\treserved[6];\n-\t__le32\taddr_high;\n-\t__le32\taddr_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);\n-\n-/* Get Switch Configuration command (indirect 0x0200)\n- * uses i40e_aqc_switch_seid for the descriptor\n- */\n-struct i40e_aqc_get_switch_config_header_resp {\n-\t__le16\tnum_reported;\n-\t__le16\tnum_total;\n-\tu8\treserved[12];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);\n-\n-struct i40e_aqc_switch_config_element_resp {\n-\tu8\telement_type;\n-#define I40E_AQ_SW_ELEM_TYPE_MAC\t1\n-#define I40E_AQ_SW_ELEM_TYPE_PF\t\t2\n-#define I40E_AQ_SW_ELEM_TYPE_VF\t\t3\n-#define I40E_AQ_SW_ELEM_TYPE_EMP\t4\n-#define I40E_AQ_SW_ELEM_TYPE_BMC\t5\n-#define I40E_AQ_SW_ELEM_TYPE_PV\t\t16\n-#define I40E_AQ_SW_ELEM_TYPE_VEB\t17\n-#define I40E_AQ_SW_ELEM_TYPE_PA\t\t18\n-#define I40E_AQ_SW_ELEM_TYPE_VSI\t19\n-\tu8\trevision;\n-#define I40E_AQ_SW_ELEM_REV_1\t\t1\n-\t__le16\tseid;\n-\t__le16\tuplink_seid;\n-\t__le16\tdownlink_seid;\n-\tu8\treserved[3];\n-\tu8\tconnection_type;\n-#define I40E_AQ_CONN_TYPE_REGULAR\t0x1\n-#define I40E_AQ_CONN_TYPE_DEFAULT\t0x2\n-#define I40E_AQ_CONN_TYPE_CASCADED\t0x3\n-\t__le16\tscheduler_id;\n-\t__le16\telement_info;\n-};\n-\n-I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);\n-\n-/* Get Switch Configuration (indirect 0x0200)\n- * an array of elements are returned in the response buffer\n- * the first in the array is the header, remainder are elements\n- */\n-struct i40e_aqc_get_switch_config_resp {\n-\tstruct i40e_aqc_get_switch_config_header_resp\theader;\n-\tstruct i40e_aqc_switch_config_element_resp\telement[1];\n-};\n-\n-I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);\n-\n-/* Add Statistics (direct 0x0201)\n- * Remove Statistics (direct 0x0202)\n- */\n-struct i40e_aqc_add_remove_statistics {\n-\t__le16\tseid;\n-\t__le16\tvlan;\n-\t__le16\tstat_index;\n-\tu8\treserved[10];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);\n-\n-/* Set Port Parameters command (direct 0x0203) */\n-struct i40e_aqc_set_port_parameters {\n-\t__le16\tcommand_flags;\n-#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS\t1\n-#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS\t2 /* must set! */\n-#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA\t4\n-\t__le16\tbad_frame_vsi;\n-#define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT\t0x0\n-#define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK\t0x3FF\n-\t__le16\tdefault_seid; /* reserved for command */\n-\tu8\treserved[10];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);\n-\n-/* Get Switch Resource Allocation (indirect 0x0204) */\n-struct i40e_aqc_get_switch_resource_alloc {\n-\tu8\tnum_entries; /* reserved for command */\n-\tu8\treserved[7];\n-\t__le32\taddr_high;\n-\t__le32\taddr_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);\n-\n-/* expect an array of these structs in the response buffer */\n-struct i40e_aqc_switch_resource_alloc_element_resp {\n-\tu8\tresource_type;\n-#define I40E_AQ_RESOURCE_TYPE_VEB\t\t0x0\n-#define I40E_AQ_RESOURCE_TYPE_VSI\t\t0x1\n-#define I40E_AQ_RESOURCE_TYPE_MACADDR\t\t0x2\n-#define I40E_AQ_RESOURCE_TYPE_STAG\t\t0x3\n-#define I40E_AQ_RESOURCE_TYPE_ETAG\t\t0x4\n-#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH\t0x5\n-#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH\t0x6\n-#define I40E_AQ_RESOURCE_TYPE_VLAN\t\t0x7\n-#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY\t0x8\n-#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY\t0x9\n-#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL\t0xA\n-#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE\t0xB\n-#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS\t0xC\n-#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS\t0xD\n-#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS\t0xF\n-#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS\t0x10\n-#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS\t0x11\n-#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS\t\t0x12\n-#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS\t0x13\n-\tu8\treserved1;\n-\t__le16\tguaranteed;\n-\t__le16\ttotal;\n-\t__le16\tused;\n-\t__le16\ttotal_unalloced;\n-\tu8\treserved2[6];\n-};\n-\n-I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);\n-\n-/* Set Switch Configuration (direct 0x0205) */\n-struct i40e_aqc_set_switch_config {\n-\t__le16\tflags;\n-/* flags used for both fields below */\n-#define I40E_AQ_SET_SWITCH_CFG_PROMISC\t\t0x0001\n-#define I40E_AQ_SET_SWITCH_CFG_L2_FILTER\t0x0002\n-\t__le16\tvalid_flags;\n-\t/* The ethertype in switch_tag is dropped on ingress and used\n-\t * internally by the switch. Set this to zero for the default\n-\t * of 0x88a8 (802.1ad). Should be zero for firmware API\n-\t * versions lower than 1.7.\n-\t */\n-\t__le16\tswitch_tag;\n-\t/* The ethertypes in first_tag and second_tag are used to\n-\t * match the outer and inner VLAN tags (respectively) when HW\n-\t * double VLAN tagging is enabled via the set port parameters\n-\t * AQ command. Otherwise these are both ignored. Set them to\n-\t * zero for their defaults of 0x8100 (802.1Q). Should be zero\n-\t * for firmware API versions lower than 1.7.\n-\t */\n-\t__le16\tfirst_tag;\n-\t__le16\tsecond_tag;\n-\tu8\treserved[6];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);\n-\n-/* Read Receive control registers (direct 0x0206)\n- * Write Receive control registers (direct 0x0207)\n- * used for accessing Rx control registers that can be\n- * slow and need special handling when under high Rx load\n- */\n-struct i40e_aqc_rx_ctl_reg_read_write {\n-\t__le32 reserved1;\n-\t__le32 address;\n-\t__le32 reserved2;\n-\t__le32 value;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);\n-\n-/* Add VSI (indirect 0x0210)\n- * this indirect command uses struct i40e_aqc_vsi_properties_data\n- * as the indirect buffer (128 bytes)\n- *\n- * Update VSI (indirect 0x211)\n- * uses the same data structure as Add VSI\n- *\n- * Get VSI (indirect 0x0212)\n- * uses the same completion and data structure as Add VSI\n- */\n-struct i40e_aqc_add_get_update_vsi {\n-\t__le16\tuplink_seid;\n-\tu8\tconnection_type;\n-#define I40E_AQ_VSI_CONN_TYPE_NORMAL\t0x1\n-#define I40E_AQ_VSI_CONN_TYPE_DEFAULT\t0x2\n-#define I40E_AQ_VSI_CONN_TYPE_CASCADED\t0x3\n-\tu8\treserved1;\n-\tu8\tvf_id;\n-\tu8\treserved2;\n-\t__le16\tvsi_flags;\n-#define I40E_AQ_VSI_TYPE_SHIFT\t\t0x0\n-#define I40E_AQ_VSI_TYPE_MASK\t\t(0x3 << I40E_AQ_VSI_TYPE_SHIFT)\n-#define I40E_AQ_VSI_TYPE_VF\t\t0x0\n-#define I40E_AQ_VSI_TYPE_VMDQ2\t\t0x1\n-#define I40E_AQ_VSI_TYPE_PF\t\t0x2\n-#define I40E_AQ_VSI_TYPE_EMP_MNG\t0x3\n-#define I40E_AQ_VSI_FLAG_CASCADED_PV\t0x4\n-\t__le32\taddr_high;\n-\t__le32\taddr_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);\n-\n-struct i40e_aqc_add_get_update_vsi_completion {\n-\t__le16 seid;\n-\t__le16 vsi_number;\n-\t__le16 vsi_used;\n-\t__le16 vsi_free;\n-\t__le32 addr_high;\n-\t__le32 addr_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);\n-\n struct i40e_aqc_vsi_properties_data {\n \t/* first 96 byte are written by SW */\n \t__le16\tvalid_sections;\n@@ -952,87 +441,6 @@ struct i40e_aqc_vsi_properties_data {\n \n I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);\n \n-/* Add Port Virtualizer (direct 0x0220)\n- * also used for update PV (direct 0x0221) but only flags are used\n- * (IS_CTRL_PORT only works on add PV)\n- */\n-struct i40e_aqc_add_update_pv {\n-\t__le16\tcommand_flags;\n-#define I40E_AQC_PV_FLAG_PV_TYPE\t\t0x1\n-#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN\t0x2\n-#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN\t0x4\n-#define I40E_AQC_PV_FLAG_IS_CTRL_PORT\t\t0x8\n-\t__le16\tuplink_seid;\n-\t__le16\tconnected_seid;\n-\tu8\treserved[10];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);\n-\n-struct i40e_aqc_add_update_pv_completion {\n-\t/* reserved for update; for add also encodes error if rc == ENOSPC */\n-\t__le16\tpv_seid;\n-#define I40E_AQC_PV_ERR_FLAG_NO_PV\t0x1\n-#define I40E_AQC_PV_ERR_FLAG_NO_SCHED\t0x2\n-#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER\t0x4\n-#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY\t0x8\n-\tu8\treserved[14];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);\n-\n-/* Get PV Params (direct 0x0222)\n- * uses i40e_aqc_switch_seid for the descriptor\n- */\n-\n-struct i40e_aqc_get_pv_params_completion {\n-\t__le16\tseid;\n-\t__le16\tdefault_stag;\n-\t__le16\tpv_flags; /* same flags as add_pv */\n-#define I40E_AQC_GET_PV_PV_TYPE\t\t\t0x1\n-#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG\t0x2\n-#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG\t0x4\n-\tu8\treserved[8];\n-\t__le16\tdefault_port_seid;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);\n-\n-/* Add VEB (direct 0x0230) */\n-struct i40e_aqc_add_veb {\n-\t__le16\tuplink_seid;\n-\t__le16\tdownlink_seid;\n-\t__le16\tveb_flags;\n-#define I40E_AQC_ADD_VEB_FLOATING\t\t0x1\n-#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT\t1\n-#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK\t\t(0x3 << \\\n-\t\t\t\t\tI40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)\n-#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT\t0x2\n-#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA\t\t0x4\n-#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER\t0x8 /* deprecated */\n-#define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS\t0x10\n-\tu8\tenable_tcs;\n-\tu8\treserved[9];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);\n-\n-struct i40e_aqc_add_veb_completion {\n-\tu8\treserved[6];\n-\t__le16\tswitch_seid;\n-\t/* also encodes error if rc == ENOSPC; codes are the same as add_pv */\n-\t__le16\tveb_seid;\n-#define I40E_AQC_VEB_ERR_FLAG_NO_VEB\t\t0x1\n-#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED\t\t0x2\n-#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER\t0x4\n-#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY\t\t0x8\n-\t__le16\tstatistic_index;\n-\t__le16\tvebs_used;\n-\t__le16\tvebs_free;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);\n-\n /* Get VEB Parameters (direct 0x0232)\n * uses i40e_aqc_switch_seid for the descriptor\n */\n@@ -1048,1670 +456,73 @@ struct i40e_aqc_get_veb_parameters_completion {\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);\n \n-/* Delete Element (direct 0x0243)\n- * uses the generic i40e_aqc_switch_seid\n- */\n-\n-/* Add MAC-VLAN (indirect 0x0250) */\n-\n-/* used for the command for most vlan commands */\n-struct i40e_aqc_macvlan {\n-\t__le16\tnum_addresses;\n-\t__le16\tseid[3];\n-#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT\t0\n-#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK\t(0x3FF << \\\n-\t\t\t\t\tI40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)\n-#define I40E_AQC_MACVLAN_CMD_SEID_VALID\t\t0x8000\n-\t__le32\taddr_high;\n-\t__le32\taddr_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);\n-\n-/* indirect data for command and response */\n-struct i40e_aqc_add_macvlan_element_data {\n-\tu8\tmac_addr[6];\n-\t__le16\tvlan_tag;\n-\t__le16\tflags;\n-#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH\t0x0001\n-#define I40E_AQC_MACVLAN_ADD_HASH_MATCH\t\t0x0002\n-#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN\t0x0004\n-#define I40E_AQC_MACVLAN_ADD_TO_QUEUE\t\t0x0008\n-#define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC\t0x0010\n-\t__le16\tqueue_number;\n-#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT\t0\n-#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK\t\t(0x7FF << \\\n-\t\t\t\t\tI40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)\n-\t/* response section */\n-\tu8\tmatch_method;\n-#define I40E_AQC_MM_PERFECT_MATCH\t0x01\n-#define I40E_AQC_MM_HASH_MATCH\t\t0x02\n-#define I40E_AQC_MM_ERR_NO_RES\t\t0xFF\n-\tu8\treserved1[3];\n-};\n-\n-struct i40e_aqc_add_remove_macvlan_completion {\n-\t__le16 perfect_mac_used;\n-\t__le16 perfect_mac_free;\n-\t__le16 unicast_hash_free;\n-\t__le16 multicast_hash_free;\n-\t__le32 addr_high;\n-\t__le32 addr_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);\n-\n-/* Remove MAC-VLAN (indirect 0x0251)\n- * uses i40e_aqc_macvlan for the descriptor\n- * data points to an array of num_addresses of elements\n- */\n+#define I40E_LINK_SPEED_100MB_SHIFT\t0x1\n+#define I40E_LINK_SPEED_1000MB_SHIFT\t0x2\n+#define I40E_LINK_SPEED_10GB_SHIFT\t0x3\n+#define I40E_LINK_SPEED_40GB_SHIFT\t0x4\n+#define I40E_LINK_SPEED_20GB_SHIFT\t0x5\n+#define I40E_LINK_SPEED_25GB_SHIFT\t0x6\n \n-struct i40e_aqc_remove_macvlan_element_data {\n-\tu8\tmac_addr[6];\n-\t__le16\tvlan_tag;\n-\tu8\tflags;\n-#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH\t0x01\n-#define I40E_AQC_MACVLAN_DEL_HASH_MATCH\t\t0x02\n-#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN\t0x08\n-#define I40E_AQC_MACVLAN_DEL_ALL_VSIS\t\t0x10\n-\tu8\treserved[3];\n-\t/* reply section */\n-\tu8\terror_code;\n-#define I40E_AQC_REMOVE_MACVLAN_SUCCESS\t\t0x0\n-#define I40E_AQC_REMOVE_MACVLAN_FAIL\t\t0xFF\n-\tu8\treply_reserved[3];\n+enum i40e_aq_link_speed {\n+\tI40E_LINK_SPEED_UNKNOWN\t= 0,\n+\tI40E_LINK_SPEED_100MB\t= BIT(I40E_LINK_SPEED_100MB_SHIFT),\n+\tI40E_LINK_SPEED_1GB\t= BIT(I40E_LINK_SPEED_1000MB_SHIFT),\n+\tI40E_LINK_SPEED_10GB\t= BIT(I40E_LINK_SPEED_10GB_SHIFT),\n+\tI40E_LINK_SPEED_40GB\t= BIT(I40E_LINK_SPEED_40GB_SHIFT),\n+\tI40E_LINK_SPEED_20GB\t= BIT(I40E_LINK_SPEED_20GB_SHIFT),\n+\tI40E_LINK_SPEED_25GB\t= BIT(I40E_LINK_SPEED_25GB_SHIFT),\n };\n \n-/* Add VLAN (indirect 0x0252)\n- * Remove VLAN (indirect 0x0253)\n- * use the generic i40e_aqc_macvlan for the command\n+/* Send to PF command (indirect 0x0801) id is only used by PF\n+ * Send to VF command (indirect 0x0802) id is only used by PF\n+ * Send to Peer PF command (indirect 0x0803)\n */\n-struct i40e_aqc_add_remove_vlan_element_data {\n-\t__le16\tvlan_tag;\n-\tu8\tvlan_flags;\n-/* flags for add VLAN */\n-#define I40E_AQC_ADD_VLAN_LOCAL\t\t\t0x1\n-#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT\t\t1\n-#define I40E_AQC_ADD_PVLAN_TYPE_MASK\t(0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)\n-#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR\t\t0x0\n-#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY\t\t0x2\n-#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY\t0x4\n-#define I40E_AQC_VLAN_PTYPE_SHIFT\t\t3\n-#define I40E_AQC_VLAN_PTYPE_MASK\t(0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)\n-#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI\t\t0x0\n-#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI\t\t0x8\n-#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI\t0x10\n-#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI\t0x18\n-/* flags for remove VLAN */\n-#define I40E_AQC_REMOVE_VLAN_ALL\t0x1\n-\tu8\treserved;\n-\tu8\tresult;\n-/* flags for add VLAN */\n-#define I40E_AQC_ADD_VLAN_SUCCESS\t0x0\n-#define I40E_AQC_ADD_VLAN_FAIL_REQUEST\t0xFE\n-#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE\t0xFF\n-/* flags for remove VLAN */\n-#define I40E_AQC_REMOVE_VLAN_SUCCESS\t0x0\n-#define I40E_AQC_REMOVE_VLAN_FAIL\t0xFF\n-\tu8\treserved1[3];\n-};\n-\n-struct i40e_aqc_add_remove_vlan_completion {\n+struct i40e_aqc_pf_vf_message {\n+\t__le32\tid;\n \tu8\treserved[4];\n-\t__le16\tvlans_used;\n-\t__le16\tvlans_free;\n \t__le32\taddr_high;\n \t__le32\taddr_low;\n };\n \n-/* Set VSI Promiscuous Modes (direct 0x0254) */\n-struct i40e_aqc_set_vsi_promiscuous_modes {\n-\t__le16\tpromiscuous_flags;\n-\t__le16\tvalid_flags;\n-/* flags used for both fields above */\n-#define I40E_AQC_SET_VSI_PROMISC_UNICAST\t0x01\n-#define I40E_AQC_SET_VSI_PROMISC_MULTICAST\t0x02\n-#define I40E_AQC_SET_VSI_PROMISC_BROADCAST\t0x04\n-#define I40E_AQC_SET_VSI_DEFAULT\t\t0x08\n-#define I40E_AQC_SET_VSI_PROMISC_VLAN\t\t0x10\n-#define I40E_AQC_SET_VSI_PROMISC_TX\t\t0x8000\n-\t__le16\tseid;\n-#define I40E_AQC_VSI_PROM_CMD_SEID_MASK\t\t0x3FF\n-\t__le16\tvlan_tag;\n-#define I40E_AQC_SET_VSI_VLAN_MASK\t\t0x0FFF\n-#define I40E_AQC_SET_VSI_VLAN_VALID\t\t0x8000\n-\tu8\treserved[8];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);\n-\n-/* Add S/E-tag command (direct 0x0255)\n- * Uses generic i40e_aqc_add_remove_tag_completion for completion\n- */\n-struct i40e_aqc_add_tag {\n-\t__le16\tflags;\n-#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE\t\t0x0001\n-\t__le16\tseid;\n-#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT\t0\n-#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK\t(0x3FF << \\\n-\t\t\t\t\tI40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)\n-\t__le16\ttag;\n-\t__le16\tqueue_number;\n-\tu8\treserved[8];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);\n-\n-struct i40e_aqc_add_remove_tag_completion {\n-\tu8\treserved[12];\n-\t__le16\ttags_used;\n-\t__le16\ttags_free;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);\n-\n-/* Remove S/E-tag command (direct 0x0256)\n- * Uses generic i40e_aqc_add_remove_tag_completion for completion\n- */\n-struct i40e_aqc_remove_tag {\n-\t__le16\tseid;\n-#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT\t0\n-#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK\t(0x3FF << \\\n-\t\t\t\t\tI40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)\n-\t__le16\ttag;\n-\tu8\treserved[12];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);\n-\n-/* Add multicast E-Tag (direct 0x0257)\n- * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields\n- * and no external data\n- */\n-struct i40e_aqc_add_remove_mcast_etag {\n-\t__le16\tpv_seid;\n-\t__le16\tetag;\n-\tu8\tnum_unicast_etags;\n-\tu8\treserved[3];\n-\t__le32\taddr_high; /* address of array of 2-byte s-tags */\n-\t__le32\taddr_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);\n+I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);\n \n-struct i40e_aqc_add_remove_mcast_etag_completion {\n-\tu8\treserved[4];\n-\t__le16\tmcast_etags_used;\n-\t__le16\tmcast_etags_free;\n+struct i40e_aqc_get_set_rss_key {\n+#define I40E_AQC_SET_RSS_KEY_VSI_VALID\t\tBIT(15)\n+#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT\t0\n+#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK\t(0x3FF << \\\n+\t\t\t\t\tI40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)\n+\t__le16\tvsi_id;\n+\tu8\treserved[6];\n \t__le32\taddr_high;\n \t__le32\taddr_low;\n-\n };\n \n-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);\n+I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);\n \n-/* Update S/E-Tag (direct 0x0259) */\n-struct i40e_aqc_update_tag {\n-\t__le16\tseid;\n-#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT\t0\n-#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK\t(0x3FF << \\\n-\t\t\t\t\tI40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)\n-\t__le16\told_tag;\n-\t__le16\tnew_tag;\n-\tu8\treserved[10];\n+struct i40e_aqc_get_set_rss_key_data {\n+\tu8 standard_rss_key[0x28];\n+\tu8 extended_hash_key[0xc];\n };\n \n-I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);\n-\n-struct i40e_aqc_update_tag_completion {\n-\tu8\treserved[12];\n-\t__le16\ttags_used;\n-\t__le16\ttags_free;\n-};\n+I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);\n \n-I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);\n+struct i40e_aqc_get_set_rss_lut {\n+#define I40E_AQC_SET_RSS_LUT_VSI_VALID\t\tBIT(15)\n+#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT\t0\n+#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK\t(0x3FF << \\\n+\t\t\t\t\tI40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)\n+\t__le16\tvsi_id;\n+#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT\t0\n+#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK \\\n+\t\t\t\tBIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)\n \n-/* Add Control Packet filter (direct 0x025A)\n- * Remove Control Packet filter (direct 0x025B)\n- * uses the i40e_aqc_add_oveb_cloud,\n- * and the generic direct completion structure\n- */\n-struct i40e_aqc_add_remove_control_packet_filter {\n-\tu8\tmac[6];\n-\t__le16\tetype;\n+#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI\t0\n+#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF\t1\n \t__le16\tflags;\n-#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC\t0x0001\n-#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP\t\t0x0002\n-#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE\t0x0004\n-#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX\t\t0x0008\n-#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX\t\t0x0000\n-\t__le16\tseid;\n-#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT\t0\n-#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK\t(0x3FF << \\\n-\t\t\t\tI40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)\n-\t__le16\tqueue;\n-\tu8\treserved[2];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);\n-\n-struct i40e_aqc_add_remove_control_packet_filter_completion {\n-\t__le16\tmac_etype_used;\n-\t__le16\tetype_used;\n-\t__le16\tmac_etype_free;\n-\t__le16\tetype_free;\n-\tu8\treserved[8];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);\n-\n-/* Add Cloud filters (indirect 0x025C)\n- * Remove Cloud filters (indirect 0x025D)\n- * uses the i40e_aqc_add_remove_cloud_filters,\n- * and the generic indirect completion structure\n- */\n-struct i40e_aqc_add_remove_cloud_filters {\n-\tu8\tnum_filters;\n-\tu8\treserved;\n-\t__le16\tseid;\n-#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT\t0\n-#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK\t(0x3FF << \\\n-\t\t\t\t\tI40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)\n-\tu8\tbig_buffer_flag;\n-#define I40E_AQC_ADD_CLOUD_CMD_BB\t1\n-\tu8\treserved2[3];\n-\t__le32\taddr_high;\n-\t__le32\taddr_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);\n-\n-struct i40e_aqc_cloud_filters_element_data {\n-\tu8\touter_mac[6];\n-\tu8\tinner_mac[6];\n-\t__le16\tinner_vlan;\n-\tunion {\n-\t\tstruct {\n-\t\t\tu8 reserved[12];\n-\t\t\tu8 data[4];\n-\t\t} v4;\n-\t\tstruct {\n-\t\t\tu8 data[16];\n-\t\t} v6;\n-\t\tstruct {\n-\t\t\t__le16 data[8];\n-\t\t} raw_v6;\n-\t} ipaddr;\n-\t__le16\tflags;\n-#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT\t\t\t0\n-#define I40E_AQC_ADD_CLOUD_FILTER_MASK\t(0x3F << \\\n-\t\t\t\t\tI40E_AQC_ADD_CLOUD_FILTER_SHIFT)\n-/* 0x0000 reserved */\n-#define I40E_AQC_ADD_CLOUD_FILTER_OIP\t\t\t0x0001\n-/* 0x0002 reserved */\n-#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN\t\t0x0003\n-#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID\t0x0004\n-/* 0x0005 reserved */\n-#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID\t\t0x0006\n-/* 0x0007 reserved */\n-/* 0x0008 reserved */\n-#define I40E_AQC_ADD_CLOUD_FILTER_OMAC\t\t\t0x0009\n-#define I40E_AQC_ADD_CLOUD_FILTER_IMAC\t\t\t0x000A\n-#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC\t0x000B\n-#define I40E_AQC_ADD_CLOUD_FILTER_IIP\t\t\t0x000C\n-/* 0x0010 to 0x0017 is for custom filters */\n-#define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT\t\t0x0010 /* Dest IP + L4 Port */\n-#define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT\t\t0x0011 /* Dest MAC + L4 Port */\n-#define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT\t\t0x0012 /* Dest MAC + VLAN + L4 Port */\n-\n-#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE\t\t0x0080\n-#define I40E_AQC_ADD_CLOUD_VNK_SHIFT\t\t\t6\n-#define I40E_AQC_ADD_CLOUD_VNK_MASK\t\t\t0x00C0\n-#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4\t\t\t0\n-#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6\t\t\t0x0100\n-\n-#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT\t\t9\n-#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK\t\t0x1E00\n-#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN\t\t0\n-#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC\t\t1\n-#define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE\t\t2\n-#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP\t\t\t3\n-#define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED\t\t4\n-#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE\t\t5\n-\n-#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC\t0x2000\n-#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC\t0x4000\n-#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP\t0x8000\n-\n-\t__le32\ttenant_id;\n-\tu8\treserved[4];\n-\t__le16\tqueue_number;\n-#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT\t\t0\n-#define I40E_AQC_ADD_CLOUD_QUEUE_MASK\t\t(0x7FF << \\\n-\t\t\t\t\t\t I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)\n-\tu8\treserved2[14];\n-\t/* response section */\n-\tu8\tallocation_result;\n-#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS\t0x0\n-#define I40E_AQC_ADD_CLOUD_FILTER_FAIL\t\t0xFF\n-\tu8\tresponse_reserved[7];\n-};\n-\n-I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data);\n-\n-/* i40e_aqc_cloud_filters_element_bb is used when\n- * I40E_AQC_ADD_CLOUD_CMD_BB flag is set.\n- */\n-struct i40e_aqc_cloud_filters_element_bb {\n-\tstruct i40e_aqc_cloud_filters_element_data element;\n-\tu16 general_fields[32];\n-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0\t0\n-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1\t1\n-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2\t2\n-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0\t3\n-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1\t4\n-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2\t5\n-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0\t6\n-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1\t7\n-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2\t8\n-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0\t9\n-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1\t10\n-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2\t11\n-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0\t12\n-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1\t13\n-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2\t14\n-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0\t15\n-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1\t16\n-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2\t17\n-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3\t18\n-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4\t19\n-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5\t20\n-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6\t21\n-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7\t22\n-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0\t23\n-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1\t24\n-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2\t25\n-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3\t26\n-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4\t27\n-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5\t28\n-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6\t29\n-#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7\t30\n-};\n-\n-I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb);\n-\n-struct i40e_aqc_remove_cloud_filters_completion {\n-\t__le16 perfect_ovlan_used;\n-\t__le16 perfect_ovlan_free;\n-\t__le16 vlan_used;\n-\t__le16 vlan_free;\n-\t__le32 addr_high;\n-\t__le32 addr_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);\n-\n-/* Replace filter Command 0x025F\n- * uses the i40e_aqc_replace_cloud_filters,\n- * and the generic indirect completion structure\n- */\n-struct i40e_filter_data {\n-\tu8 filter_type;\n-\tu8 input[3];\n-};\n-\n-I40E_CHECK_STRUCT_LEN(4, i40e_filter_data);\n-\n-struct i40e_aqc_replace_cloud_filters_cmd {\n-\tu8 valid_flags;\n-#define I40E_AQC_REPLACE_L1_FILTER\t\t0x0\n-#define I40E_AQC_REPLACE_CLOUD_FILTER\t\t0x1\n-#define I40E_AQC_GET_CLOUD_FILTERS\t\t0x2\n-#define I40E_AQC_MIRROR_CLOUD_FILTER\t\t0x4\n-#define I40E_AQC_HIGH_PRIORITY_CLOUD_FILTER\t0x8\n-\tu8 old_filter_type;\n-\tu8 new_filter_type;\n-\tu8 tr_bit;\n-\tu8 reserved[4];\n-\t__le32 addr_high;\n-\t__le32 addr_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_replace_cloud_filters_cmd);\n-\n-struct i40e_aqc_replace_cloud_filters_cmd_buf {\n-\tu8 data[32];\n-/* Filter type INPUT codes*/\n-#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX\t3\n-#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED\tBIT(7)\n-\n-/* Field Vector offsets */\n-#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA\t0\n-#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH\t6\n-#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG\t7\n-#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN\t8\n-#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN\t9\n-#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN\t10\n-#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY\t11\n-#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC\t12\n-/* big FLU */\n-#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA\t14\n-/* big FLU */\n-#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA\t15\n-\n-#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN\t37\n-\tstruct i40e_filter_data filters[8];\n-};\n-\n-I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf);\n-\n-/* Add Mirror Rule (indirect or direct 0x0260)\n- * Delete Mirror Rule (indirect or direct 0x0261)\n- * note: some rule types (4,5) do not use an external buffer.\n- * take care to set the flags correctly.\n- */\n-struct i40e_aqc_add_delete_mirror_rule {\n-\t__le16 seid;\n-\t__le16 rule_type;\n-#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT\t\t0\n-#define I40E_AQC_MIRROR_RULE_TYPE_MASK\t\t(0x7 << \\\n-\t\t\t\t\t\tI40E_AQC_MIRROR_RULE_TYPE_SHIFT)\n-#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS\t1\n-#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS\t2\n-#define I40E_AQC_MIRROR_RULE_TYPE_VLAN\t\t3\n-#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS\t4\n-#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS\t5\n-\t__le16 num_entries;\n-\t__le16 destination; /* VSI for add, rule id for delete */\n-\t__le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */\n-\t__le32 addr_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);\n-\n-struct i40e_aqc_add_delete_mirror_rule_completion {\n-\tu8\treserved[2];\n-\t__le16\trule_id; /* only used on add */\n-\t__le16\tmirror_rules_used;\n-\t__le16\tmirror_rules_free;\n-\t__le32\taddr_high;\n-\t__le32\taddr_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);\n-\n-/* Dynamic Device Personalization */\n-struct i40e_aqc_write_personalization_profile {\n-\tu8 flags;\n-\tu8 reserved[3];\n-\t__le32 profile_track_id;\n-\t__le32 addr_high;\n-\t__le32 addr_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile);\n-\n-struct i40e_aqc_write_ddp_resp {\n-\t__le32 error_offset;\n-\t__le32 error_info;\n-\t__le32 addr_high;\n-\t__le32 addr_low;\n-};\n-\n-struct i40e_aqc_get_applied_profiles {\n-\tu8 flags;\n-#define I40E_AQC_GET_DDP_GET_CONF\t0x1\n-#define I40E_AQC_GET_DDP_GET_RDPU_CONF\t0x2\n-\tu8 rsv[3];\n-\t__le32 reserved;\n-\t__le32 addr_high;\n-\t__le32 addr_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles);\n-\n-/* DCB 0x03xx*/\n-\n-/* PFC Ignore (direct 0x0301)\n- * the command and response use the same descriptor structure\n- */\n-struct i40e_aqc_pfc_ignore {\n-\tu8\ttc_bitmap;\n-\tu8\tcommand_flags; /* unused on response */\n-#define I40E_AQC_PFC_IGNORE_SET\t\t0x80\n-#define I40E_AQC_PFC_IGNORE_CLEAR\t0x0\n-\tu8\treserved[14];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);\n-\n-/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure\n- * with no parameters\n- */\n-\n-/* TX scheduler 0x04xx */\n-\n-/* Almost all the indirect commands use\n- * this generic struct to pass the SEID in param0\n- */\n-struct i40e_aqc_tx_sched_ind {\n-\t__le16\tvsi_seid;\n-\tu8\treserved[6];\n-\t__le32\taddr_high;\n-\t__le32\taddr_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);\n-\n-/* Several commands respond with a set of queue set handles */\n-struct i40e_aqc_qs_handles_resp {\n-\t__le16 qs_handles[8];\n-};\n-\n-/* Configure VSI BW limits (direct 0x0400) */\n-struct i40e_aqc_configure_vsi_bw_limit {\n-\t__le16\tvsi_seid;\n-\tu8\treserved[2];\n-\t__le16\tcredit;\n-\tu8\treserved1[2];\n-\tu8\tmax_credit; /* 0-3, limit = 2^max */\n-\tu8\treserved2[7];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);\n-\n-/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)\n- * responds with i40e_aqc_qs_handles_resp\n- */\n-struct i40e_aqc_configure_vsi_ets_sla_bw_data {\n-\tu8\ttc_valid_bits;\n-\tu8\treserved[15];\n-\t__le16\ttc_bw_credits[8]; /* FW writesback QS handles here */\n-\n-\t/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */\n-\t__le16\ttc_bw_max[2];\n-\tu8\treserved1[28];\n-};\n-\n-I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);\n-\n-/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)\n- * responds with i40e_aqc_qs_handles_resp\n- */\n-struct i40e_aqc_configure_vsi_tc_bw_data {\n-\tu8\ttc_valid_bits;\n-\tu8\treserved[3];\n-\tu8\ttc_bw_credits[8];\n-\tu8\treserved1[4];\n-\t__le16\tqs_handles[8];\n-};\n-\n-I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);\n-\n-/* Query vsi bw configuration (indirect 0x0408) */\n-struct i40e_aqc_query_vsi_bw_config_resp {\n-\tu8\ttc_valid_bits;\n-\tu8\ttc_suspended_bits;\n-\tu8\treserved[14];\n-\t__le16\tqs_handles[8];\n-\tu8\treserved1[4];\n-\t__le16\tport_bw_limit;\n-\tu8\treserved2[2];\n-\tu8\tmax_bw; /* 0-3, limit = 2^max */\n-\tu8\treserved3[23];\n-};\n-\n-I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);\n-\n-/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */\n-struct i40e_aqc_query_vsi_ets_sla_config_resp {\n-\tu8\ttc_valid_bits;\n-\tu8\treserved[3];\n-\tu8\tshare_credits[8];\n-\t__le16\tcredits[8];\n-\n-\t/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */\n-\t__le16\ttc_bw_max[2];\n-};\n-\n-I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);\n-\n-/* Configure Switching Component Bandwidth Limit (direct 0x0410) */\n-struct i40e_aqc_configure_switching_comp_bw_limit {\n-\t__le16\tseid;\n-\tu8\treserved[2];\n-\t__le16\tcredit;\n-\tu8\treserved1[2];\n-\tu8\tmax_bw; /* 0-3, limit = 2^max */\n-\tu8\treserved2[7];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);\n-\n-/* Enable Physical Port ETS (indirect 0x0413)\n- * Modify Physical Port ETS (indirect 0x0414)\n- * Disable Physical Port ETS (indirect 0x0415)\n- */\n-struct i40e_aqc_configure_switching_comp_ets_data {\n-\tu8\treserved[4];\n-\tu8\ttc_valid_bits;\n-\tu8\tseepage;\n-#define I40E_AQ_ETS_SEEPAGE_EN_MASK\t0x1\n-\tu8\ttc_strict_priority_flags;\n-\tu8\treserved1[17];\n-\tu8\ttc_bw_share_credits[8];\n-\tu8\treserved2[96];\n-};\n-\n-I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);\n-\n-/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */\n-struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {\n-\tu8\ttc_valid_bits;\n-\tu8\treserved[15];\n-\t__le16\ttc_bw_credit[8];\n-\n-\t/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */\n-\t__le16\ttc_bw_max[2];\n-\tu8\treserved1[28];\n-};\n-\n-I40E_CHECK_STRUCT_LEN(0x40,\n-\t\t i40e_aqc_configure_switching_comp_ets_bw_limit_data);\n-\n-/* Configure Switching Component Bandwidth Allocation per Tc\n- * (indirect 0x0417)\n- */\n-struct i40e_aqc_configure_switching_comp_bw_config_data {\n-\tu8\ttc_valid_bits;\n-\tu8\treserved[2];\n-\tu8\tabsolute_credits; /* bool */\n-\tu8\ttc_bw_share_credits[8];\n-\tu8\treserved1[20];\n-};\n-\n-I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);\n-\n-/* Query Switching Component Configuration (indirect 0x0418) */\n-struct i40e_aqc_query_switching_comp_ets_config_resp {\n-\tu8\ttc_valid_bits;\n-\tu8\treserved[35];\n-\t__le16\tport_bw_limit;\n-\tu8\treserved1[2];\n-\tu8\ttc_bw_max; /* 0-3, limit = 2^max */\n-\tu8\treserved2[23];\n-};\n-\n-I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);\n-\n-/* Query PhysicalPort ETS Configuration (indirect 0x0419) */\n-struct i40e_aqc_query_port_ets_config_resp {\n-\tu8\treserved[4];\n-\tu8\ttc_valid_bits;\n-\tu8\treserved1;\n-\tu8\ttc_strict_priority_bits;\n-\tu8\treserved2;\n-\tu8\ttc_bw_share_credits[8];\n-\t__le16\ttc_bw_limits[8];\n-\n-\t/* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */\n-\t__le16\ttc_bw_max[2];\n-\tu8\treserved3[32];\n-};\n-\n-I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);\n-\n-/* Query Switching Component Bandwidth Allocation per Traffic Type\n- * (indirect 0x041A)\n- */\n-struct i40e_aqc_query_switching_comp_bw_config_resp {\n-\tu8\ttc_valid_bits;\n-\tu8\treserved[2];\n-\tu8\tabsolute_credits_enable; /* bool */\n-\tu8\ttc_bw_share_credits[8];\n-\t__le16\ttc_bw_limits[8];\n-\n-\t/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */\n-\t__le16\ttc_bw_max[2];\n-};\n-\n-I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);\n-\n-/* Suspend/resume port TX traffic\n- * (direct 0x041B and 0x041C) uses the generic SEID struct\n- */\n-\n-/* Configure partition BW\n- * (indirect 0x041D)\n- */\n-struct i40e_aqc_configure_partition_bw_data {\n-\t__le16\tpf_valid_bits;\n-\tu8\tmin_bw[16]; /* guaranteed bandwidth */\n-\tu8\tmax_bw[16]; /* bandwidth limit */\n-};\n-\n-I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);\n-\n-/* Get and set the active HMC resource profile and status.\n- * (direct 0x0500) and (direct 0x0501)\n- */\n-struct i40e_aq_get_set_hmc_resource_profile {\n-\tu8\tpm_profile;\n-\tu8\tpe_vf_enabled;\n-\tu8\treserved[14];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);\n-\n-enum i40e_aq_hmc_profile {\n-\t/* I40E_HMC_PROFILE_NO_CHANGE\t= 0, reserved */\n-\tI40E_HMC_PROFILE_DEFAULT\t= 1,\n-\tI40E_HMC_PROFILE_FAVOR_VF\t= 2,\n-\tI40E_HMC_PROFILE_EQUAL\t\t= 3,\n-};\n-\n-/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */\n-\n-/* set in param0 for get phy abilities to report qualified modules */\n-#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES\t0x0001\n-#define I40E_AQ_PHY_REPORT_INITIAL_VALUES\t0x0002\n-\n-enum i40e_aq_phy_type {\n-\tI40E_PHY_TYPE_SGMII\t\t\t= 0x0,\n-\tI40E_PHY_TYPE_1000BASE_KX\t\t= 0x1,\n-\tI40E_PHY_TYPE_10GBASE_KX4\t\t= 0x2,\n-\tI40E_PHY_TYPE_10GBASE_KR\t\t= 0x3,\n-\tI40E_PHY_TYPE_40GBASE_KR4\t\t= 0x4,\n-\tI40E_PHY_TYPE_XAUI\t\t\t= 0x5,\n-\tI40E_PHY_TYPE_XFI\t\t\t= 0x6,\n-\tI40E_PHY_TYPE_SFI\t\t\t= 0x7,\n-\tI40E_PHY_TYPE_XLAUI\t\t\t= 0x8,\n-\tI40E_PHY_TYPE_XLPPI\t\t\t= 0x9,\n-\tI40E_PHY_TYPE_40GBASE_CR4_CU\t\t= 0xA,\n-\tI40E_PHY_TYPE_10GBASE_CR1_CU\t\t= 0xB,\n-\tI40E_PHY_TYPE_10GBASE_AOC\t\t= 0xC,\n-\tI40E_PHY_TYPE_40GBASE_AOC\t\t= 0xD,\n-\tI40E_PHY_TYPE_UNRECOGNIZED\t\t= 0xE,\n-\tI40E_PHY_TYPE_UNSUPPORTED\t\t= 0xF,\n-\tI40E_PHY_TYPE_100BASE_TX\t\t= 0x11,\n-\tI40E_PHY_TYPE_1000BASE_T\t\t= 0x12,\n-\tI40E_PHY_TYPE_10GBASE_T\t\t\t= 0x13,\n-\tI40E_PHY_TYPE_10GBASE_SR\t\t= 0x14,\n-\tI40E_PHY_TYPE_10GBASE_LR\t\t= 0x15,\n-\tI40E_PHY_TYPE_10GBASE_SFPP_CU\t\t= 0x16,\n-\tI40E_PHY_TYPE_10GBASE_CR1\t\t= 0x17,\n-\tI40E_PHY_TYPE_40GBASE_CR4\t\t= 0x18,\n-\tI40E_PHY_TYPE_40GBASE_SR4\t\t= 0x19,\n-\tI40E_PHY_TYPE_40GBASE_LR4\t\t= 0x1A,\n-\tI40E_PHY_TYPE_1000BASE_SX\t\t= 0x1B,\n-\tI40E_PHY_TYPE_1000BASE_LX\t\t= 0x1C,\n-\tI40E_PHY_TYPE_1000BASE_T_OPTICAL\t= 0x1D,\n-\tI40E_PHY_TYPE_20GBASE_KR2\t\t= 0x1E,\n-\tI40E_PHY_TYPE_25GBASE_KR\t\t= 0x1F,\n-\tI40E_PHY_TYPE_25GBASE_CR\t\t= 0x20,\n-\tI40E_PHY_TYPE_25GBASE_SR\t\t= 0x21,\n-\tI40E_PHY_TYPE_25GBASE_LR\t\t= 0x22,\n-\tI40E_PHY_TYPE_25GBASE_AOC\t\t= 0x23,\n-\tI40E_PHY_TYPE_25GBASE_ACC\t\t= 0x24,\n-\tI40E_PHY_TYPE_MAX,\n-\tI40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP\t= 0xFD,\n-\tI40E_PHY_TYPE_EMPTY\t\t\t= 0xFE,\n-\tI40E_PHY_TYPE_DEFAULT\t\t\t= 0xFF,\n-};\n-\n-#define I40E_LINK_SPEED_100MB_SHIFT\t0x1\n-#define I40E_LINK_SPEED_1000MB_SHIFT\t0x2\n-#define I40E_LINK_SPEED_10GB_SHIFT\t0x3\n-#define I40E_LINK_SPEED_40GB_SHIFT\t0x4\n-#define I40E_LINK_SPEED_20GB_SHIFT\t0x5\n-#define I40E_LINK_SPEED_25GB_SHIFT\t0x6\n-\n-enum i40e_aq_link_speed {\n-\tI40E_LINK_SPEED_UNKNOWN\t= 0,\n-\tI40E_LINK_SPEED_100MB\t= BIT(I40E_LINK_SPEED_100MB_SHIFT),\n-\tI40E_LINK_SPEED_1GB\t= BIT(I40E_LINK_SPEED_1000MB_SHIFT),\n-\tI40E_LINK_SPEED_10GB\t= BIT(I40E_LINK_SPEED_10GB_SHIFT),\n-\tI40E_LINK_SPEED_40GB\t= BIT(I40E_LINK_SPEED_40GB_SHIFT),\n-\tI40E_LINK_SPEED_20GB\t= BIT(I40E_LINK_SPEED_20GB_SHIFT),\n-\tI40E_LINK_SPEED_25GB\t= BIT(I40E_LINK_SPEED_25GB_SHIFT),\n-};\n-\n-struct i40e_aqc_module_desc {\n-\tu8 oui[3];\n-\tu8 reserved1;\n-\tu8 part_number[16];\n-\tu8 revision[4];\n-\tu8 reserved2[8];\n-};\n-\n-I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);\n-\n-struct i40e_aq_get_phy_abilities_resp {\n-\t__le32\tphy_type; /* bitmap using the above enum for offsets */\n-\tu8\tlink_speed; /* bitmap using the above enum bit patterns */\n-\tu8\tabilities;\n-#define I40E_AQ_PHY_FLAG_PAUSE_TX\t0x01\n-#define I40E_AQ_PHY_FLAG_PAUSE_RX\t0x02\n-#define I40E_AQ_PHY_FLAG_LOW_POWER\t0x04\n-#define I40E_AQ_PHY_LINK_ENABLED\t0x08\n-#define I40E_AQ_PHY_AN_ENABLED\t\t0x10\n-#define I40E_AQ_PHY_FLAG_MODULE_QUAL\t0x20\n-#define I40E_AQ_PHY_FEC_ABILITY_KR\t0x40\n-#define I40E_AQ_PHY_FEC_ABILITY_RS\t0x80\n-\t__le16\teee_capability;\n-#define I40E_AQ_EEE_100BASE_TX\t\t0x0002\n-#define I40E_AQ_EEE_1000BASE_T\t\t0x0004\n-#define I40E_AQ_EEE_10GBASE_T\t\t0x0008\n-#define I40E_AQ_EEE_1000BASE_KX\t\t0x0010\n-#define I40E_AQ_EEE_10GBASE_KX4\t\t0x0020\n-#define I40E_AQ_EEE_10GBASE_KR\t\t0x0040\n-\t__le32\teeer_val;\n-\tu8\td3_lpan;\n-#define I40E_AQ_SET_PHY_D3_LPAN_ENA\t0x01\n-\tu8\tphy_type_ext;\n-#define I40E_AQ_PHY_TYPE_EXT_25G_KR\t0X01\n-#define I40E_AQ_PHY_TYPE_EXT_25G_CR\t0X02\n-#define I40E_AQ_PHY_TYPE_EXT_25G_SR\t0x04\n-#define I40E_AQ_PHY_TYPE_EXT_25G_LR\t0x08\n-#define I40E_AQ_PHY_TYPE_EXT_25G_AOC\t0x10\n-#define I40E_AQ_PHY_TYPE_EXT_25G_ACC\t0x20\n-\tu8\tfec_cfg_curr_mod_ext_info;\n-#define I40E_AQ_ENABLE_FEC_KR\t\t0x01\n-#define I40E_AQ_ENABLE_FEC_RS\t\t0x02\n-#define I40E_AQ_REQUEST_FEC_KR\t\t0x04\n-#define I40E_AQ_REQUEST_FEC_RS\t\t0x08\n-#define I40E_AQ_ENABLE_FEC_AUTO\t\t0x10\n-#define I40E_AQ_FEC\n-#define I40E_AQ_MODULE_TYPE_EXT_MASK\t0xE0\n-#define I40E_AQ_MODULE_TYPE_EXT_SHIFT\t5\n-\n-\tu8\text_comp_code;\n-\tu8\tphy_id[4];\n-\tu8\tmodule_type[3];\n-\tu8\tqualified_module_count;\n-#define I40E_AQ_PHY_MAX_QMS\t\t16\n-\tstruct i40e_aqc_module_desc\tqualified_module[I40E_AQ_PHY_MAX_QMS];\n-};\n-\n-I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);\n-\n-/* Set PHY Config (direct 0x0601) */\n-struct i40e_aq_set_phy_config { /* same bits as above in all */\n-\t__le32\tphy_type;\n-\tu8\tlink_speed;\n-\tu8\tabilities;\n-/* bits 0-2 use the values from get_phy_abilities_resp */\n-#define I40E_AQ_PHY_ENABLE_LINK\t\t0x08\n-#define I40E_AQ_PHY_ENABLE_AN\t\t0x10\n-#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK\t0x20\n-\t__le16\teee_capability;\n-\t__le32\teeer;\n-\tu8\tlow_power_ctrl;\n-\tu8\tphy_type_ext;\n-#define I40E_AQ_PHY_TYPE_EXT_25G_KR\t0X01\n-#define I40E_AQ_PHY_TYPE_EXT_25G_CR\t0X02\n-#define I40E_AQ_PHY_TYPE_EXT_25G_SR\t0x04\n-#define I40E_AQ_PHY_TYPE_EXT_25G_LR\t0x08\n-\tu8\tfec_config;\n-#define I40E_AQ_SET_FEC_ABILITY_KR\tBIT(0)\n-#define I40E_AQ_SET_FEC_ABILITY_RS\tBIT(1)\n-#define I40E_AQ_SET_FEC_REQUEST_KR\tBIT(2)\n-#define I40E_AQ_SET_FEC_REQUEST_RS\tBIT(3)\n-#define I40E_AQ_SET_FEC_AUTO\t\tBIT(4)\n-#define I40E_AQ_PHY_FEC_CONFIG_SHIFT\t0x0\n-#define I40E_AQ_PHY_FEC_CONFIG_MASK\t(0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT)\n-\tu8\treserved;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);\n-\n-/* Set MAC Config command data structure (direct 0x0603) */\n-struct i40e_aq_set_mac_config {\n-\t__le16\tmax_frame_size;\n-\tu8\tparams;\n-#define I40E_AQ_SET_MAC_CONFIG_CRC_EN\t\t0x04\n-#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK\t0x78\n-#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT\t3\n-#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE\t0x0\n-#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX\t0xF\n-#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX\t0x9\n-#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX\t0x8\n-#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX\t0x7\n-#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX\t0x6\n-#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX\t0x5\n-#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX\t0x4\n-#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX\t0x3\n-#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX\t0x2\n-#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX\t0x1\n-\tu8\ttx_timer_priority; /* bitmap */\n-\t__le16\ttx_timer_value;\n-\t__le16\tfc_refresh_threshold;\n-\tu8\treserved[8];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);\n-\n-/* Restart Auto-Negotiation (direct 0x605) */\n-struct i40e_aqc_set_link_restart_an {\n-\tu8\tcommand;\n-#define I40E_AQ_PHY_RESTART_AN\t0x02\n-#define I40E_AQ_PHY_LINK_ENABLE\t0x04\n-\tu8\treserved[15];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);\n-\n-/* Get Link Status cmd & response data structure (direct 0x0607) */\n-struct i40e_aqc_get_link_status {\n-\t__le16\tcommand_flags; /* only field set on command */\n-#define I40E_AQ_LSE_MASK\t\t0x3\n-#define I40E_AQ_LSE_NOP\t\t\t0x0\n-#define I40E_AQ_LSE_DISABLE\t\t0x2\n-#define I40E_AQ_LSE_ENABLE\t\t0x3\n-/* only response uses this flag */\n-#define I40E_AQ_LSE_IS_ENABLED\t\t0x1\n-\tu8\tphy_type; /* i40e_aq_phy_type */\n-\tu8\tlink_speed; /* i40e_aq_link_speed */\n-\tu8\tlink_info;\n-#define I40E_AQ_LINK_UP\t\t\t0x01 /* obsolete */\n-#define I40E_AQ_LINK_UP_FUNCTION\t0x01\n-#define I40E_AQ_LINK_FAULT\t\t0x02\n-#define I40E_AQ_LINK_FAULT_TX\t\t0x04\n-#define I40E_AQ_LINK_FAULT_RX\t\t0x08\n-#define I40E_AQ_LINK_FAULT_REMOTE\t0x10\n-#define I40E_AQ_LINK_UP_PORT\t\t0x20\n-#define I40E_AQ_MEDIA_AVAILABLE\t\t0x40\n-#define I40E_AQ_SIGNAL_DETECT\t\t0x80\n-\tu8\tan_info;\n-#define I40E_AQ_AN_COMPLETED\t\t0x01\n-#define I40E_AQ_LP_AN_ABILITY\t\t0x02\n-#define I40E_AQ_PD_FAULT\t\t0x04\n-#define I40E_AQ_FEC_EN\t\t\t0x08\n-#define I40E_AQ_PHY_LOW_POWER\t\t0x10\n-#define I40E_AQ_LINK_PAUSE_TX\t\t0x20\n-#define I40E_AQ_LINK_PAUSE_RX\t\t0x40\n-#define I40E_AQ_QUALIFIED_MODULE\t0x80\n-\tu8\text_info;\n-#define I40E_AQ_LINK_PHY_TEMP_ALARM\t0x01\n-#define I40E_AQ_LINK_XCESSIVE_ERRORS\t0x02\n-#define I40E_AQ_LINK_TX_SHIFT\t\t0x02\n-#define I40E_AQ_LINK_TX_MASK\t\t(0x03 << I40E_AQ_LINK_TX_SHIFT)\n-#define I40E_AQ_LINK_TX_ACTIVE\t\t0x00\n-#define I40E_AQ_LINK_TX_DRAINED\t\t0x01\n-#define I40E_AQ_LINK_TX_FLUSHED\t\t0x03\n-#define I40E_AQ_LINK_FORCED_40G\t\t0x10\n-/* 25G Error Codes */\n-#define I40E_AQ_25G_NO_ERR\t\t0X00\n-#define I40E_AQ_25G_NOT_PRESENT\t\t0X01\n-#define I40E_AQ_25G_NVM_CRC_ERR\t\t0X02\n-#define I40E_AQ_25G_SBUS_UCODE_ERR\t0X03\n-#define I40E_AQ_25G_SERDES_UCODE_ERR\t0X04\n-#define I40E_AQ_25G_NIMB_UCODE_ERR\t0X05\n-\tu8\tloopback; /* use defines from i40e_aqc_set_lb_mode */\n-/* Since firmware API 1.7 loopback field keeps power class info as well */\n-#define I40E_AQ_LOOPBACK_MASK\t\t0x07\n-#define I40E_AQ_PWR_CLASS_SHIFT_LB\t6\n-#define I40E_AQ_PWR_CLASS_MASK_LB\t(0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB)\n-\t__le16\tmax_frame_size;\n-\tu8\tconfig;\n-#define I40E_AQ_CONFIG_FEC_KR_ENA\t0x01\n-#define I40E_AQ_CONFIG_FEC_RS_ENA\t0x02\n-#define I40E_AQ_CONFIG_CRC_ENA\t\t0x04\n-#define I40E_AQ_CONFIG_PACING_MASK\t0x78\n-\tunion {\n-\t\tstruct {\n-\t\t\tu8\tpower_desc;\n-#define I40E_AQ_LINK_POWER_CLASS_1\t0x00\n-#define I40E_AQ_LINK_POWER_CLASS_2\t0x01\n-#define I40E_AQ_LINK_POWER_CLASS_3\t0x02\n-#define I40E_AQ_LINK_POWER_CLASS_4\t0x03\n-#define I40E_AQ_PWR_CLASS_MASK\t\t0x03\n-\t\t\tu8\treserved[4];\n-\t\t};\n-\t\tstruct {\n-\t\t\tu8\tlink_type[4];\n-\t\t\tu8\tlink_type_ext;\n-\t\t};\n-\t};\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);\n-\n-/* Set event mask command (direct 0x613) */\n-struct i40e_aqc_set_phy_int_mask {\n-\tu8\treserved[8];\n-\t__le16\tevent_mask;\n-#define I40E_AQ_EVENT_LINK_UPDOWN\t0x0002\n-#define I40E_AQ_EVENT_MEDIA_NA\t\t0x0004\n-#define I40E_AQ_EVENT_LINK_FAULT\t0x0008\n-#define I40E_AQ_EVENT_PHY_TEMP_ALARM\t0x0010\n-#define I40E_AQ_EVENT_EXCESSIVE_ERRORS\t0x0020\n-#define I40E_AQ_EVENT_SIGNAL_DETECT\t0x0040\n-#define I40E_AQ_EVENT_AN_COMPLETED\t0x0080\n-#define I40E_AQ_EVENT_MODULE_QUAL_FAIL\t0x0100\n-#define I40E_AQ_EVENT_PORT_TX_SUSPENDED\t0x0200\n-\tu8\treserved1[6];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);\n-\n-/* Get Local AN advt register (direct 0x0614)\n- * Set Local AN advt register (direct 0x0615)\n- * Get Link Partner AN advt register (direct 0x0616)\n- */\n-struct i40e_aqc_an_advt_reg {\n-\t__le32\tlocal_an_reg0;\n-\t__le16\tlocal_an_reg1;\n-\tu8\treserved[10];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);\n-\n-/* Set Loopback mode (0x0618) */\n-struct i40e_aqc_set_lb_mode {\n-\t__le16\tlb_mode;\n-#define I40E_AQ_LB_PHY_LOCAL\t0x01\n-#define I40E_AQ_LB_PHY_REMOTE\t0x02\n-#define I40E_AQ_LB_MAC_LOCAL\t0x04\n-\tu8\treserved[14];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);\n-\n-/* Set PHY Debug command (0x0622) */\n-struct i40e_aqc_set_phy_debug {\n-\tu8\tcommand_flags;\n-#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL\t0x02\n-#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT\t2\n-#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK\t(0x03 << \\\n-\t\t\t\t\tI40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)\n-#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE\t0x00\n-#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD\t0x01\n-#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT\t0x02\n-#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW\t0x10\n-\tu8\treserved[15];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);\n-\n-enum i40e_aq_phy_reg_type {\n-\tI40E_AQC_PHY_REG_INTERNAL\t= 0x1,\n-\tI40E_AQC_PHY_REG_EXERNAL_BASET\t= 0x2,\n-\tI40E_AQC_PHY_REG_EXERNAL_MODULE\t= 0x3\n-};\n-\n-/* Run PHY Activity (0x0626) */\n-struct i40e_aqc_run_phy_activity {\n-\t__le16 activity_id;\n-\tu8 flags;\n-\tu8 reserved1;\n-\t__le32 control;\n-\t__le32 data;\n-\tu8 reserved2[4];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);\n-\n-/* Set PHY Register command (0x0628) */\n-/* Get PHY Register command (0x0629) */\n-struct i40e_aqc_phy_register_access {\n-\tu8\tphy_interface;\n-#define I40E_AQ_PHY_REG_ACCESS_INTERNAL\t0\n-#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL\t1\n-#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE\t2\n-\tu8\tdev_address;\n-\tu8\treserved1[2];\n-\t__le32\treg_address;\n-\t__le32\treg_value;\n-\tu8\treserved2[4];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access);\n-\n-/* NVM Read command (indirect 0x0701)\n- * NVM Erase commands (direct 0x0702)\n- * NVM Update commands (indirect 0x0703)\n- */\n-struct i40e_aqc_nvm_update {\n-\tu8\tcommand_flags;\n-#define I40E_AQ_NVM_LAST_CMD\t\t\t0x01\n-#define I40E_AQ_NVM_REARRANGE_TO_FLAT\t\t0x20\n-#define I40E_AQ_NVM_REARRANGE_TO_STRUCT\t\t0x40\n-#define I40E_AQ_NVM_FLASH_ONLY\t\t\t0x80\n-#define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT\t1\n-#define I40E_AQ_NVM_PRESERVATION_FLAGS_MASK\t0x03\n-#define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED\t0x03\n-#define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL\t0x01\n-\tu8\tmodule_pointer;\n-\t__le16\tlength;\n-\t__le32\toffset;\n-\t__le32\taddr_high;\n-\t__le32\taddr_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);\n-\n-/* NVM Config Read (indirect 0x0704) */\n-struct i40e_aqc_nvm_config_read {\n-\t__le16\tcmd_flags;\n-#define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK\t1\n-#define I40E_AQ_ANVM_READ_SINGLE_FEATURE\t\t0\n-#define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES\t\t1\n-\t__le16\telement_count;\n-\t__le16\telement_id;\t/* Feature/field ID */\n-\t__le16\telement_id_msw;\t/* MSWord of field ID */\n-\t__le32\taddress_high;\n-\t__le32\taddress_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);\n-\n-/* NVM Config Write (indirect 0x0705) */\n-struct i40e_aqc_nvm_config_write {\n-\t__le16\tcmd_flags;\n-\t__le16\telement_count;\n-\tu8\treserved[4];\n-\t__le32\taddress_high;\n-\t__le32\taddress_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);\n-\n-/* Used for 0x0704 as well as for 0x0705 commands */\n-#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT\t\t1\n-#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \\\n-\t\t\t\tBIT(I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)\n-#define I40E_AQ_ANVM_FEATURE\t\t0\n-#define I40E_AQ_ANVM_IMMEDIATE_FIELD\tBIT(FEATURE_OR_IMMEDIATE_SHIFT)\n-struct i40e_aqc_nvm_config_data_feature {\n-\t__le16 feature_id;\n-#define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY\t\t0x01\n-#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP\t\t0x08\n-#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR\t\t0x10\n-\t__le16 feature_options;\n-\t__le16 feature_selection;\n-};\n-\n-I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);\n-\n-struct i40e_aqc_nvm_config_data_immediate_field {\n-\t__le32 field_id;\n-\t__le32 field_value;\n-\t__le16 field_options;\n-\t__le16 reserved;\n-};\n-\n-I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);\n-\n-/* OEM Post Update (indirect 0x0720)\n- * no command data struct used\n- */\n- struct i40e_aqc_nvm_oem_post_update {\n-#define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA\t0x01\n-\tu8 sel_data;\n-\tu8 reserved[7];\n-};\n-\n-I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);\n-\n-struct i40e_aqc_nvm_oem_post_update_buffer {\n-\tu8 str_len;\n-\tu8 dev_addr;\n-\t__le16 eeprom_addr;\n-\tu8 data[36];\n-};\n-\n-I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);\n-\n-/* Thermal Sensor (indirect 0x0721)\n- * read or set thermal sensor configs and values\n- * takes a sensor and command specific data buffer, not detailed here\n- */\n-struct i40e_aqc_thermal_sensor {\n-\tu8 sensor_action;\n-#define I40E_AQ_THERMAL_SENSOR_READ_CONFIG\t0\n-#define I40E_AQ_THERMAL_SENSOR_SET_CONFIG\t1\n-#define I40E_AQ_THERMAL_SENSOR_READ_TEMP\t2\n-\tu8 reserved[7];\n-\t__le32\taddr_high;\n-\t__le32\taddr_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);\n-\n-/* Send to PF command (indirect 0x0801) id is only used by PF\n- * Send to VF command (indirect 0x0802) id is only used by PF\n- * Send to Peer PF command (indirect 0x0803)\n- */\n-struct i40e_aqc_pf_vf_message {\n-\t__le32\tid;\n-\tu8\treserved[4];\n-\t__le32\taddr_high;\n-\t__le32\taddr_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);\n-\n-/* Alternate structure */\n-\n-/* Direct write (direct 0x0900)\n- * Direct read (direct 0x0902)\n- */\n-struct i40e_aqc_alternate_write {\n-\t__le32 address0;\n-\t__le32 data0;\n-\t__le32 address1;\n-\t__le32 data1;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);\n-\n-/* Indirect write (indirect 0x0901)\n- * Indirect read (indirect 0x0903)\n- */\n-\n-struct i40e_aqc_alternate_ind_write {\n-\t__le32 address;\n-\t__le32 length;\n-\t__le32 addr_high;\n-\t__le32 addr_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);\n-\n-/* Done alternate write (direct 0x0904)\n- * uses i40e_aq_desc\n- */\n-struct i40e_aqc_alternate_write_done {\n-\t__le16\tcmd_flags;\n-#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK\t1\n-#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY\t0\n-#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI\t1\n-#define I40E_AQ_ALTERNATE_RESET_NEEDED\t\t2\n-\tu8\treserved[14];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);\n-\n-/* Set OEM mode (direct 0x0905) */\n-struct i40e_aqc_alternate_set_mode {\n-\t__le32\tmode;\n-#define I40E_AQ_ALTERNATE_MODE_NONE\t0\n-#define I40E_AQ_ALTERNATE_MODE_OEM\t1\n-\tu8\treserved[12];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);\n-\n-/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */\n-\n-/* async events 0x10xx */\n-\n-/* Lan Queue Overflow Event (direct, 0x1001) */\n-struct i40e_aqc_lan_overflow {\n-\t__le32\tprtdcb_rupto;\n-\t__le32\totx_ctl;\n-\tu8\treserved[8];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);\n-\n-/* Get LLDP MIB (indirect 0x0A00) */\n-struct i40e_aqc_lldp_get_mib {\n-\tu8\ttype;\n-\tu8\treserved1;\n-#define I40E_AQ_LLDP_MIB_TYPE_MASK\t\t0x3\n-#define I40E_AQ_LLDP_MIB_LOCAL\t\t\t0x0\n-#define I40E_AQ_LLDP_MIB_REMOTE\t\t\t0x1\n-#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE\t0x2\n-#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK\t\t0xC\n-#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT\t\t0x2\n-#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE\t0x0\n-#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR\t0x1\n-#define I40E_AQ_LLDP_TX_SHIFT\t\t\t0x4\n-#define I40E_AQ_LLDP_TX_MASK\t\t\t(0x03 << I40E_AQ_LLDP_TX_SHIFT)\n-/* TX pause flags use I40E_AQ_LINK_TX_* above */\n-\t__le16\tlocal_len;\n-\t__le16\tremote_len;\n-\tu8\treserved2[2];\n-\t__le32\taddr_high;\n-\t__le32\taddr_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);\n-\n-/* Configure LLDP MIB Change Event (direct 0x0A01)\n- * also used for the event (with type in the command field)\n- */\n-struct i40e_aqc_lldp_update_mib {\n-\tu8\tcommand;\n-#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE\t0x0\n-#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE\t0x1\n-\tu8\treserved[7];\n-\t__le32\taddr_high;\n-\t__le32\taddr_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);\n-\n-/* Add LLDP TLV (indirect 0x0A02)\n- * Delete LLDP TLV (indirect 0x0A04)\n- */\n-struct i40e_aqc_lldp_add_tlv {\n-\tu8\ttype; /* only nearest bridge and non-TPMR from 0x0A00 */\n-\tu8\treserved1[1];\n-\t__le16\tlen;\n-\tu8\treserved2[4];\n-\t__le32\taddr_high;\n-\t__le32\taddr_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);\n-\n-/* Update LLDP TLV (indirect 0x0A03) */\n-struct i40e_aqc_lldp_update_tlv {\n-\tu8\ttype; /* only nearest bridge and non-TPMR from 0x0A00 */\n-\tu8\treserved;\n-\t__le16\told_len;\n-\t__le16\tnew_offset;\n-\t__le16\tnew_len;\n-\t__le32\taddr_high;\n-\t__le32\taddr_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);\n-\n-/* Stop LLDP (direct 0x0A05) */\n-struct i40e_aqc_lldp_stop {\n-\tu8\tcommand;\n-#define I40E_AQ_LLDP_AGENT_STOP\t\t0x0\n-#define I40E_AQ_LLDP_AGENT_SHUTDOWN\t0x1\n-\tu8\treserved[15];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);\n-\n-/* Start LLDP (direct 0x0A06) */\n-\n-struct i40e_aqc_lldp_start {\n-\tu8\tcommand;\n-#define I40E_AQ_LLDP_AGENT_START\t0x1\n-\tu8\treserved[15];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);\n-\n-/* Set DCB (direct 0x0303) */\n-struct i40e_aqc_set_dcb_parameters {\n-\tu8 command;\n-#define I40E_AQ_DCB_SET_AGENT\t0x1\n-#define I40E_DCB_VALID\t\t0x1\n-\tu8 valid_flags;\n-\tu8 reserved[14];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters);\n-\n-/* Apply MIB changes (0x0A07)\n- * uses the generic struc as it contains no data\n- */\n-\n-/* Add Udp Tunnel command and completion (direct 0x0B00) */\n-struct i40e_aqc_add_udp_tunnel {\n-\t__le16\tudp_port;\n-\tu8\treserved0[3];\n-\tu8\tprotocol_type;\n-#define I40E_AQC_TUNNEL_TYPE_VXLAN\t0x00\n-#define I40E_AQC_TUNNEL_TYPE_NGE\t0x01\n-#define I40E_AQC_TUNNEL_TYPE_TEREDO\t0x10\n-#define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE\t0x11\n-\tu8\treserved1[10];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);\n-\n-struct i40e_aqc_add_udp_tunnel_completion {\n-\t__le16 udp_port;\n-\tu8\tfilter_entry_index;\n-\tu8\tmultiple_pfs;\n-#define I40E_AQC_SINGLE_PF\t\t0x0\n-#define I40E_AQC_MULTIPLE_PFS\t\t0x1\n-\tu8\ttotal_filters;\n-\tu8\treserved[11];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);\n-\n-/* remove UDP Tunnel command (0x0B01) */\n-struct i40e_aqc_remove_udp_tunnel {\n-\tu8\treserved[2];\n-\tu8\tindex; /* 0 to 15 */\n-\tu8\treserved2[13];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);\n-\n-struct i40e_aqc_del_udp_tunnel_completion {\n-\t__le16\tudp_port;\n-\tu8\tindex; /* 0 to 15 */\n-\tu8\tmultiple_pfs;\n-\tu8\ttotal_filters_used;\n-\tu8\treserved1[11];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);\n-\n-struct i40e_aqc_get_set_rss_key {\n-#define I40E_AQC_SET_RSS_KEY_VSI_VALID\t\tBIT(15)\n-#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT\t0\n-#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK\t(0x3FF << \\\n-\t\t\t\t\tI40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)\n-\t__le16\tvsi_id;\n-\tu8\treserved[6];\n-\t__le32\taddr_high;\n-\t__le32\taddr_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);\n-\n-struct i40e_aqc_get_set_rss_key_data {\n-\tu8 standard_rss_key[0x28];\n-\tu8 extended_hash_key[0xc];\n-};\n-\n-I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);\n-\n-struct i40e_aqc_get_set_rss_lut {\n-#define I40E_AQC_SET_RSS_LUT_VSI_VALID\t\tBIT(15)\n-#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT\t0\n-#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK\t(0x3FF << \\\n-\t\t\t\t\tI40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)\n-\t__le16\tvsi_id;\n-#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT\t0\n-#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK \\\n-\t\t\t\tBIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)\n-\n-#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI\t0\n-#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF\t1\n-\t__le16\tflags;\n-\tu8\treserved[4];\n+\tu8\treserved[4];\n \t__le32\taddr_high;\n \t__le32\taddr_low;\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);\n-\n-/* tunnel key structure 0x0B10 */\n-\n-struct i40e_aqc_tunnel_key_structure_A0 {\n-\t__le16 key1_off;\n-\t__le16 key1_len;\n-\t__le16 key2_off;\n-\t__le16 key2_len;\n-\t__le16 flags;\n-#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01\n-/* response flags */\n-#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01\n-#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02\n-#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03\n-\tu8 resreved[6];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure_A0);\n-\n-struct i40e_aqc_tunnel_key_structure {\n-\tu8\tkey1_off;\n-\tu8\tkey2_off;\n-\tu8\tkey1_len; /* 0 to 15 */\n-\tu8\tkey2_len; /* 0 to 15 */\n-\tu8\tflags;\n-#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE\t0x01\n-/* response flags */\n-#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS\t0x01\n-#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED\t0x02\n-#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN\t0x03\n-\tu8\tnetwork_key_index;\n-#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN\t\t0x0\n-#define I40E_AQC_NETWORK_KEY_INDEX_NGE\t\t\t0x1\n-#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP\t0x2\n-#define I40E_AQC_NETWORK_KEY_INDEX_GRE\t\t\t0x3\n-\tu8\treserved[10];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);\n-\n-/* OEM mode commands (direct 0xFE0x) */\n-struct i40e_aqc_oem_param_change {\n-\t__le32\tparam_type;\n-#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL\t0\n-#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL\t1\n-#define I40E_AQ_OEM_PARAM_MAC\t\t2\n-\t__le32\tparam_value1;\n-\t__le16\tparam_value2;\n-\tu8\treserved[6];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);\n-\n-struct i40e_aqc_oem_state_change {\n-\t__le32\tstate;\n-#define I40E_AQ_OEM_STATE_LINK_DOWN\t0x0\n-#define I40E_AQ_OEM_STATE_LINK_UP\t0x1\n-\tu8\treserved[12];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);\n-\n-/* Initialize OCSD (0xFE02, direct) */\n-struct i40e_aqc_opc_oem_ocsd_initialize {\n-\tu8 type_status;\n-\tu8 reserved1[3];\n-\t__le32 ocsd_memory_block_addr_high;\n-\t__le32 ocsd_memory_block_addr_low;\n-\t__le32 requested_update_interval;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);\n-\n-/* Initialize OCBB (0xFE03, direct) */\n-struct i40e_aqc_opc_oem_ocbb_initialize {\n-\tu8 type_status;\n-\tu8 reserved1[3];\n-\t__le32 ocbb_memory_block_addr_high;\n-\t__le32 ocbb_memory_block_addr_low;\n-\tu8 reserved2[4];\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);\n-\n-/* debug commands */\n-\n-/* get device id (0xFF00) uses the generic structure */\n-\n-/* set test more (0xFF01, internal) */\n-\n-struct i40e_acq_set_test_mode {\n-\tu8\tmode;\n-#define I40E_AQ_TEST_PARTIAL\t0\n-#define I40E_AQ_TEST_FULL\t1\n-#define I40E_AQ_TEST_NVM\t2\n-\tu8\treserved[3];\n-\tu8\tcommand;\n-#define I40E_AQ_TEST_OPEN\t0\n-#define I40E_AQ_TEST_CLOSE\t1\n-#define I40E_AQ_TEST_INC\t2\n-\tu8\treserved2[3];\n-\t__le32\taddress_high;\n-\t__le32\taddress_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);\n-\n-/* Debug Read Register command (0xFF03)\n- * Debug Write Register command (0xFF04)\n- */\n-struct i40e_aqc_debug_reg_read_write {\n-\t__le32 reserved;\n-\t__le32 address;\n-\t__le32 value_high;\n-\t__le32 value_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);\n-\n-/* Scatter/gather Reg Read (indirect 0xFF05)\n- * Scatter/gather Reg Write (indirect 0xFF06)\n- */\n-\n-/* i40e_aq_desc is used for the command */\n-struct i40e_aqc_debug_reg_sg_element_data {\n-\t__le32 address;\n-\t__le32 value;\n-};\n-\n-/* Debug Modify register (direct 0xFF07) */\n-struct i40e_aqc_debug_modify_reg {\n-\t__le32 address;\n-\t__le32 value;\n-\t__le32 clear_mask;\n-\t__le32 set_mask;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);\n-\n-/* dump internal data (0xFF08, indirect) */\n-\n-#define I40E_AQ_CLUSTER_ID_AUX\t\t0\n-#define I40E_AQ_CLUSTER_ID_SWITCH_FLU\t1\n-#define I40E_AQ_CLUSTER_ID_TXSCHED\t2\n-#define I40E_AQ_CLUSTER_ID_HMC\t\t3\n-#define I40E_AQ_CLUSTER_ID_MAC0\t\t4\n-#define I40E_AQ_CLUSTER_ID_MAC1\t\t5\n-#define I40E_AQ_CLUSTER_ID_MAC2\t\t6\n-#define I40E_AQ_CLUSTER_ID_MAC3\t\t7\n-#define I40E_AQ_CLUSTER_ID_DCB\t\t8\n-#define I40E_AQ_CLUSTER_ID_EMP_MEM\t9\n-#define I40E_AQ_CLUSTER_ID_PKT_BUF\t10\n-#define I40E_AQ_CLUSTER_ID_ALTRAM\t11\n-\n-struct i40e_aqc_debug_dump_internals {\n-\tu8\tcluster_id;\n-\tu8\ttable_id;\n-\t__le16\tdata_size;\n-\t__le32\tidx;\n-\t__le32\taddress_high;\n-\t__le32\taddress_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);\n-\n-struct i40e_aqc_debug_modify_internals {\n-\tu8\tcluster_id;\n-\tu8\tcluster_specific_params[7];\n-\t__le32\taddress_high;\n-\t__le32\taddress_low;\n-};\n-\n-I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);\n-\n #endif /* _I40E_ADMINQ_CMD_H_ */\ndiff --git a/drivers/net/ethernet/intel/iavf/i40e_common.c b/drivers/net/ethernet/intel/iavf/i40e_common.c\nindex eea280ba411e..6ebca11f039e 100644\n--- a/drivers/net/ethernet/intel/iavf/i40e_common.c\n+++ b/drivers/net/ethernet/intel/iavf/i40e_common.c\n@@ -891,135 +891,6 @@ struct i40e_rx_ptype_decoded i40evf_ptype_lookup[] = {\n \tI40E_PTT_UNUSED_ENTRY(255)\n };\n \n-/**\n- * i40evf_aq_rx_ctl_read_register - use FW to read from an Rx control register\n- * @hw: pointer to the hw struct\n- * @reg_addr: register address\n- * @reg_val: ptr to register value\n- * @cmd_details: pointer to command details structure or NULL\n- *\n- * Use the firmware to read the Rx control register,\n- * especially useful if the Rx unit is under heavy pressure\n- **/\n-i40e_status i40evf_aq_rx_ctl_read_register(struct i40e_hw *hw,\n-\t\t\t\tu32 reg_addr, u32 *reg_val,\n-\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n-{\n-\tstruct i40e_aq_desc desc;\n-\tstruct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =\n-\t\t(struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;\n-\ti40e_status status;\n-\n-\tif (!reg_val)\n-\t\treturn I40E_ERR_PARAM;\n-\n-\ti40evf_fill_default_direct_cmd_desc(&desc,\n-\t\t\t\t\t i40e_aqc_opc_rx_ctl_reg_read);\n-\n-\tcmd_resp->address = cpu_to_le32(reg_addr);\n-\n-\tstatus = i40evf_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n-\n-\tif (status == 0)\n-\t\t*reg_val = le32_to_cpu(cmd_resp->value);\n-\n-\treturn status;\n-}\n-\n-/**\n- * i40evf_read_rx_ctl - read from an Rx control register\n- * @hw: pointer to the hw struct\n- * @reg_addr: register address\n- **/\n-u32 i40evf_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)\n-{\n-\ti40e_status status = 0;\n-\tbool use_register;\n-\tint retry = 5;\n-\tu32 val = 0;\n-\n-\tuse_register = (((hw->aq.api_maj_ver == 1) &&\n-\t\t\t(hw->aq.api_min_ver < 5)) ||\n-\t\t\t(hw->mac.type == I40E_MAC_X722));\n-\tif (!use_register) {\n-do_retry:\n-\t\tstatus = i40evf_aq_rx_ctl_read_register(hw, reg_addr,\n-\t\t\t\t\t\t\t&val, NULL);\n-\t\tif (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {\n-\t\t\tusleep_range(1000, 2000);\n-\t\t\tretry--;\n-\t\t\tgoto do_retry;\n-\t\t}\n-\t}\n-\n-\t/* if the AQ access failed, try the old-fashioned way */\n-\tif (status || use_register)\n-\t\tval = rd32(hw, reg_addr);\n-\n-\treturn val;\n-}\n-\n-/**\n- * i40evf_aq_rx_ctl_write_register\n- * @hw: pointer to the hw struct\n- * @reg_addr: register address\n- * @reg_val: register value\n- * @cmd_details: pointer to command details structure or NULL\n- *\n- * Use the firmware to write to an Rx control register,\n- * especially useful if the Rx unit is under heavy pressure\n- **/\n-i40e_status i40evf_aq_rx_ctl_write_register(struct i40e_hw *hw,\n-\t\t\t\tu32 reg_addr, u32 reg_val,\n-\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n-{\n-\tstruct i40e_aq_desc desc;\n-\tstruct i40e_aqc_rx_ctl_reg_read_write *cmd =\n-\t\t(struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;\n-\ti40e_status status;\n-\n-\ti40evf_fill_default_direct_cmd_desc(&desc,\n-\t\t\t\t\t i40e_aqc_opc_rx_ctl_reg_write);\n-\n-\tcmd->address = cpu_to_le32(reg_addr);\n-\tcmd->value = cpu_to_le32(reg_val);\n-\n-\tstatus = i40evf_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n-\n-\treturn status;\n-}\n-\n-/**\n- * i40evf_write_rx_ctl - write to an Rx control register\n- * @hw: pointer to the hw struct\n- * @reg_addr: register address\n- * @reg_val: register value\n- **/\n-void i40evf_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)\n-{\n-\ti40e_status status = 0;\n-\tbool use_register;\n-\tint retry = 5;\n-\n-\tuse_register = (((hw->aq.api_maj_ver == 1) &&\n-\t\t\t(hw->aq.api_min_ver < 5)) ||\n-\t\t\t(hw->mac.type == I40E_MAC_X722));\n-\tif (!use_register) {\n-do_retry:\n-\t\tstatus = i40evf_aq_rx_ctl_write_register(hw, reg_addr,\n-\t\t\t\t\t\t\t reg_val, NULL);\n-\t\tif (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {\n-\t\t\tusleep_range(1000, 2000);\n-\t\t\tretry--;\n-\t\t\tgoto do_retry;\n-\t\t}\n-\t}\n-\n-\t/* if the AQ access failed, try the old-fashioned way */\n-\tif (status || use_register)\n-\t\twr32(hw, reg_addr, reg_val);\n-}\n-\n /**\n * i40e_aq_send_msg_to_pf\n * @hw: pointer to the hardware structure\n@@ -1110,211 +981,3 @@ i40e_status i40e_vf_reset(struct i40e_hw *hw)\n \treturn i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,\n \t\t\t\t 0, NULL, 0, NULL);\n }\n-\n-/**\n- * i40evf_aq_write_ddp - Write dynamic device personalization (ddp)\n- * @hw: pointer to the hw struct\n- * @buff: command buffer (size in bytes = buff_size)\n- * @buff_size: buffer size in bytes\n- * @track_id: package tracking id\n- * @error_offset: returns error offset\n- * @error_info: returns error information\n- * @cmd_details: pointer to command details structure or NULL\n- **/\n-enum\n-i40e_status_code i40evf_aq_write_ddp(struct i40e_hw *hw, void *buff,\n-\t\t\t\t u16 buff_size, u32 track_id,\n-\t\t\t\t u32 *error_offset, u32 *error_info,\n-\t\t\t\t struct i40e_asq_cmd_details *cmd_details)\n-{\n-\tstruct i40e_aq_desc desc;\n-\tstruct i40e_aqc_write_personalization_profile *cmd =\n-\t\t(struct i40e_aqc_write_personalization_profile *)\n-\t\t&desc.params.raw;\n-\tstruct i40e_aqc_write_ddp_resp *resp;\n-\ti40e_status status;\n-\n-\ti40evf_fill_default_direct_cmd_desc(&desc,\n-\t\t\t\t\t i40e_aqc_opc_write_personalization_profile);\n-\n-\tdesc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);\n-\tif (buff_size > I40E_AQ_LARGE_BUF)\n-\t\tdesc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);\n-\n-\tdesc.datalen = cpu_to_le16(buff_size);\n-\n-\tcmd->profile_track_id = cpu_to_le32(track_id);\n-\n-\tstatus = i40evf_asq_send_command(hw, &desc, buff, buff_size, cmd_details);\n-\tif (!status) {\n-\t\tresp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;\n-\t\tif (error_offset)\n-\t\t\t*error_offset = le32_to_cpu(resp->error_offset);\n-\t\tif (error_info)\n-\t\t\t*error_info = le32_to_cpu(resp->error_info);\n-\t}\n-\n-\treturn status;\n-}\n-\n-/**\n- * i40evf_aq_get_ddp_list - Read dynamic device personalization (ddp)\n- * @hw: pointer to the hw struct\n- * @buff: command buffer (size in bytes = buff_size)\n- * @buff_size: buffer size in bytes\n- * @flags: AdminQ command flags\n- * @cmd_details: pointer to command details structure or NULL\n- **/\n-enum\n-i40e_status_code i40evf_aq_get_ddp_list(struct i40e_hw *hw, void *buff,\n-\t\t\t\t\tu16 buff_size, u8 flags,\n-\t\t\t\t struct i40e_asq_cmd_details *cmd_details)\n-{\n-\tstruct i40e_aq_desc desc;\n-\tstruct i40e_aqc_get_applied_profiles *cmd =\n-\t\t(struct i40e_aqc_get_applied_profiles *)&desc.params.raw;\n-\ti40e_status status;\n-\n-\ti40evf_fill_default_direct_cmd_desc(&desc,\n-\t\t\t\t\t i40e_aqc_opc_get_personalization_profile_list);\n-\n-\tdesc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);\n-\tif (buff_size > I40E_AQ_LARGE_BUF)\n-\t\tdesc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);\n-\tdesc.datalen = cpu_to_le16(buff_size);\n-\n-\tcmd->flags = flags;\n-\n-\tstatus = i40evf_asq_send_command(hw, &desc, buff, buff_size, cmd_details);\n-\n-\treturn status;\n-}\n-\n-/**\n- * i40evf_find_segment_in_package\n- * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)\n- * @pkg_hdr: pointer to the package header to be searched\n- *\n- * This function searches a package file for a particular segment type. On\n- * success it returns a pointer to the segment header, otherwise it will\n- * return NULL.\n- **/\n-struct i40e_generic_seg_header *\n-i40evf_find_segment_in_package(u32 segment_type,\n-\t\t\t struct i40e_package_header *pkg_hdr)\n-{\n-\tstruct i40e_generic_seg_header *segment;\n-\tu32 i;\n-\n-\t/* Search all package segments for the requested segment type */\n-\tfor (i = 0; i < pkg_hdr->segment_count; i++) {\n-\t\tsegment =\n-\t\t\t(struct i40e_generic_seg_header *)((u8 *)pkg_hdr +\n-\t\t\t pkg_hdr->segment_offset[i]);\n-\n-\t\tif (segment->type == segment_type)\n-\t\t\treturn segment;\n-\t}\n-\n-\treturn NULL;\n-}\n-\n-/**\n- * i40evf_write_profile\n- * @hw: pointer to the hardware structure\n- * @profile: pointer to the profile segment of the package to be downloaded\n- * @track_id: package tracking id\n- *\n- * Handles the download of a complete package.\n- */\n-enum i40e_status_code\n-i40evf_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,\n-\t\t u32 track_id)\n-{\n-\ti40e_status status = 0;\n-\tstruct i40e_section_table *sec_tbl;\n-\tstruct i40e_profile_section_header *sec = NULL;\n-\tu32 dev_cnt;\n-\tu32 vendor_dev_id;\n-\tu32 *nvm;\n-\tu32 section_size = 0;\n-\tu32 offset = 0, info = 0;\n-\tu32 i;\n-\n-\tdev_cnt = profile->device_table_count;\n-\n-\tfor (i = 0; i < dev_cnt; i++) {\n-\t\tvendor_dev_id = profile->device_table[i].vendor_dev_id;\n-\t\tif ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL)\n-\t\t\tif (hw->device_id == (vendor_dev_id & 0xFFFF))\n-\t\t\t\tbreak;\n-\t}\n-\tif (i == dev_cnt) {\n-\t\ti40e_debug(hw, I40E_DEBUG_PACKAGE, \"Device doesn't support DDP\");\n-\t\treturn I40E_ERR_DEVICE_NOT_SUPPORTED;\n-\t}\n-\n-\tnvm = (u32 *)&profile->device_table[dev_cnt];\n-\tsec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1];\n-\n-\tfor (i = 0; i < sec_tbl->section_count; i++) {\n-\t\tsec = (struct i40e_profile_section_header *)((u8 *)profile +\n-\t\t\t\t\t sec_tbl->section_offset[i]);\n-\n-\t\t/* Skip 'AQ', 'note' and 'name' sections */\n-\t\tif (sec->section.type != SECTION_TYPE_MMIO)\n-\t\t\tcontinue;\n-\n-\t\tsection_size = sec->section.size +\n-\t\t\tsizeof(struct i40e_profile_section_header);\n-\n-\t\t/* Write profile */\n-\t\tstatus = i40evf_aq_write_ddp(hw, (void *)sec, (u16)section_size,\n-\t\t\t\t\t track_id, &offset, &info, NULL);\n-\t\tif (status) {\n-\t\t\ti40e_debug(hw, I40E_DEBUG_PACKAGE,\n-\t\t\t\t \"Failed to write profile: offset %d, info %d\",\n-\t\t\t\t offset, info);\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-\treturn status;\n-}\n-\n-/**\n- * i40evf_add_pinfo_to_list\n- * @hw: pointer to the hardware structure\n- * @profile: pointer to the profile segment of the package\n- * @profile_info_sec: buffer for information section\n- * @track_id: package tracking id\n- *\n- * Register a profile to the list of loaded profiles.\n- */\n-enum i40e_status_code\n-i40evf_add_pinfo_to_list(struct i40e_hw *hw,\n-\t\t\t struct i40e_profile_segment *profile,\n-\t\t\t u8 *profile_info_sec, u32 track_id)\n-{\n-\ti40e_status status = 0;\n-\tstruct i40e_profile_section_header *sec = NULL;\n-\tstruct i40e_profile_info *pinfo;\n-\tu32 offset = 0, info = 0;\n-\n-\tsec = (struct i40e_profile_section_header *)profile_info_sec;\n-\tsec->tbl_size = 1;\n-\tsec->data_end = sizeof(struct i40e_profile_section_header) +\n-\t\t\tsizeof(struct i40e_profile_info);\n-\tsec->section.type = SECTION_TYPE_INFO;\n-\tsec->section.offset = sizeof(struct i40e_profile_section_header);\n-\tsec->section.size = sizeof(struct i40e_profile_info);\n-\tpinfo = (struct i40e_profile_info *)(profile_info_sec +\n-\t\t\t\t\t sec->section.offset);\n-\tpinfo->track_id = track_id;\n-\tpinfo->version = profile->version;\n-\tpinfo->op = I40E_DDP_ADD_TRACKID;\n-\tmemcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE);\n-\n-\tstatus = i40evf_aq_write_ddp(hw, (void *)sec, sec->data_end,\n-\t\t\t\t track_id, &offset, &info, NULL);\n-\treturn status;\n-}\ndiff --git a/drivers/net/ethernet/intel/iavf/i40e_hmc.h b/drivers/net/ethernet/intel/iavf/i40e_hmc.h\ndeleted file mode 100644\nindex 1c78de838857..000000000000\n--- a/drivers/net/ethernet/intel/iavf/i40e_hmc.h\n+++ /dev/null\n@@ -1,215 +0,0 @@\n-/* SPDX-License-Identifier: GPL-2.0 */\n-/* Copyright(c) 2013 - 2018 Intel Corporation. */\n-\n-#ifndef _I40E_HMC_H_\n-#define _I40E_HMC_H_\n-\n-#define I40E_HMC_MAX_BP_COUNT 512\n-\n-/* forward-declare the HW struct for the compiler */\n-struct i40e_hw;\n-\n-#define I40E_HMC_INFO_SIGNATURE\t\t0x484D5347 /* HMSG */\n-#define I40E_HMC_PD_CNT_IN_SD\t\t512\n-#define I40E_HMC_DIRECT_BP_SIZE\t\t0x200000 /* 2M */\n-#define I40E_HMC_PAGED_BP_SIZE\t\t4096\n-#define I40E_HMC_PD_BP_BUF_ALIGNMENT\t4096\n-#define I40E_FIRST_VF_FPM_ID\t\t16\n-\n-struct i40e_hmc_obj_info {\n-\tu64 base;\t/* base addr in FPM */\n-\tu32 max_cnt;\t/* max count available for this hmc func */\n-\tu32 cnt;\t/* count of objects driver actually wants to create */\n-\tu64 size;\t/* size in bytes of one object */\n-};\n-\n-enum i40e_sd_entry_type {\n-\tI40E_SD_TYPE_INVALID = 0,\n-\tI40E_SD_TYPE_PAGED = 1,\n-\tI40E_SD_TYPE_DIRECT = 2\n-};\n-\n-struct i40e_hmc_bp {\n-\tenum i40e_sd_entry_type entry_type;\n-\tstruct i40e_dma_mem addr; /* populate to be used by hw */\n-\tu32 sd_pd_index;\n-\tu32 ref_cnt;\n-};\n-\n-struct i40e_hmc_pd_entry {\n-\tstruct i40e_hmc_bp bp;\n-\tu32 sd_index;\n-\tbool rsrc_pg;\n-\tbool valid;\n-};\n-\n-struct i40e_hmc_pd_table {\n-\tstruct i40e_dma_mem pd_page_addr; /* populate to be used by hw */\n-\tstruct i40e_hmc_pd_entry *pd_entry; /* [512] for sw book keeping */\n-\tstruct i40e_virt_mem pd_entry_virt_mem; /* virt mem for pd_entry */\n-\n-\tu32 ref_cnt;\n-\tu32 sd_index;\n-};\n-\n-struct i40e_hmc_sd_entry {\n-\tenum i40e_sd_entry_type entry_type;\n-\tbool valid;\n-\n-\tunion {\n-\t\tstruct i40e_hmc_pd_table pd_table;\n-\t\tstruct i40e_hmc_bp bp;\n-\t} u;\n-};\n-\n-struct i40e_hmc_sd_table {\n-\tstruct i40e_virt_mem addr; /* used to track sd_entry allocations */\n-\tu32 sd_cnt;\n-\tu32 ref_cnt;\n-\tstruct i40e_hmc_sd_entry *sd_entry; /* (sd_cnt*512) entries max */\n-};\n-\n-struct i40e_hmc_info {\n-\tu32 signature;\n-\t/* equals to pci func num for PF and dynamically allocated for VFs */\n-\tu8 hmc_fn_id;\n-\tu16 first_sd_index; /* index of the first available SD */\n-\n-\t/* hmc objects */\n-\tstruct i40e_hmc_obj_info *hmc_obj;\n-\tstruct i40e_virt_mem hmc_obj_virt_mem;\n-\tstruct i40e_hmc_sd_table sd_table;\n-};\n-\n-#define I40E_INC_SD_REFCNT(sd_table)\t((sd_table)->ref_cnt++)\n-#define I40E_INC_PD_REFCNT(pd_table)\t((pd_table)->ref_cnt++)\n-#define I40E_INC_BP_REFCNT(bp)\t\t((bp)->ref_cnt++)\n-\n-#define I40E_DEC_SD_REFCNT(sd_table)\t((sd_table)->ref_cnt--)\n-#define I40E_DEC_PD_REFCNT(pd_table)\t((pd_table)->ref_cnt--)\n-#define I40E_DEC_BP_REFCNT(bp)\t\t((bp)->ref_cnt--)\n-\n-/**\n- * I40E_SET_PF_SD_ENTRY - marks the sd entry as valid in the hardware\n- * @hw: pointer to our hw struct\n- * @pa: pointer to physical address\n- * @sd_index: segment descriptor index\n- * @type: if sd entry is direct or paged\n- **/\n-#define I40E_SET_PF_SD_ENTRY(hw, pa, sd_index, type)\t\t\t\\\n-{\t\t\t\t\t\t\t\t\t\\\n-\tu32 val1, val2, val3;\t\t\t\t\t\t\\\n-\tval1 = (u32)(upper_32_bits(pa));\t\t\t\t\\\n-\tval2 = (u32)(pa) | (I40E_HMC_MAX_BP_COUNT <<\t\t\t\\\n-\t\t I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) |\t\t\\\n-\t\t((((type) == I40E_SD_TYPE_PAGED) ? 0 : 1) <<\t\t\\\n-\t\tI40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT) |\t\t\t\\\n-\t\tBIT(I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT);\t\t\\\n-\tval3 = (sd_index) | BIT_ULL(I40E_PFHMC_SDCMD_PMSDWR_SHIFT);\t\\\n-\twr32((hw), I40E_PFHMC_SDDATAHIGH, val1);\t\t\t\\\n-\twr32((hw), I40E_PFHMC_SDDATALOW, val2);\t\t\t\t\\\n-\twr32((hw), I40E_PFHMC_SDCMD, val3);\t\t\t\t\\\n-}\n-\n-/**\n- * I40E_CLEAR_PF_SD_ENTRY - marks the sd entry as invalid in the hardware\n- * @hw: pointer to our hw struct\n- * @sd_index: segment descriptor index\n- * @type: if sd entry is direct or paged\n- **/\n-#define I40E_CLEAR_PF_SD_ENTRY(hw, sd_index, type)\t\t\t\\\n-{\t\t\t\t\t\t\t\t\t\\\n-\tu32 val2, val3;\t\t\t\t\t\t\t\\\n-\tval2 = (I40E_HMC_MAX_BP_COUNT <<\t\t\t\t\\\n-\t\tI40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) |\t\t\\\n-\t\t((((type) == I40E_SD_TYPE_PAGED) ? 0 : 1) <<\t\t\\\n-\t\tI40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT);\t\t\t\\\n-\tval3 = (sd_index) | BIT_ULL(I40E_PFHMC_SDCMD_PMSDWR_SHIFT);\t\\\n-\twr32((hw), I40E_PFHMC_SDDATAHIGH, 0);\t\t\t\t\\\n-\twr32((hw), I40E_PFHMC_SDDATALOW, val2);\t\t\t\t\\\n-\twr32((hw), I40E_PFHMC_SDCMD, val3);\t\t\t\t\\\n-}\n-\n-/**\n- * I40E_INVALIDATE_PF_HMC_PD - Invalidates the pd cache in the hardware\n- * @hw: pointer to our hw struct\n- * @sd_idx: segment descriptor index\n- * @pd_idx: page descriptor index\n- **/\n-#define I40E_INVALIDATE_PF_HMC_PD(hw, sd_idx, pd_idx)\t\t\t\\\n-\twr32((hw), I40E_PFHMC_PDINV,\t\t\t\t\t\\\n-\t (((sd_idx) << I40E_PFHMC_PDINV_PMSDIDX_SHIFT) |\t\t\\\n-\t ((pd_idx) << I40E_PFHMC_PDINV_PMPDIDX_SHIFT)))\n-\n-/**\n- * I40E_FIND_SD_INDEX_LIMIT - finds segment descriptor index limit\n- * @hmc_info: pointer to the HMC configuration information structure\n- * @type: type of HMC resources we're searching\n- * @index: starting index for the object\n- * @cnt: number of objects we're trying to create\n- * @sd_idx: pointer to return index of the segment descriptor in question\n- * @sd_limit: pointer to return the maximum number of segment descriptors\n- *\n- * This function calculates the segment descriptor index and index limit\n- * for the resource defined by i40e_hmc_rsrc_type.\n- **/\n-#define I40E_FIND_SD_INDEX_LIMIT(hmc_info, type, index, cnt, sd_idx, sd_limit)\\\n-{\t\t\t\t\t\t\t\t\t\\\n-\tu64 fpm_addr, fpm_limit;\t\t\t\t\t\\\n-\tfpm_addr = (hmc_info)->hmc_obj[(type)].base +\t\t\t\\\n-\t\t (hmc_info)->hmc_obj[(type)].size * (index);\t\t\\\n-\tfpm_limit = fpm_addr + (hmc_info)->hmc_obj[(type)].size * (cnt);\\\n-\t*(sd_idx) = (u32)(fpm_addr / I40E_HMC_DIRECT_BP_SIZE);\t\t\\\n-\t*(sd_limit) = (u32)((fpm_limit - 1) / I40E_HMC_DIRECT_BP_SIZE);\t\\\n-\t/* add one more to the limit to correct our range */\t\t\\\n-\t*(sd_limit) += 1;\t\t\t\t\t\t\\\n-}\n-\n-/**\n- * I40E_FIND_PD_INDEX_LIMIT - finds page descriptor index limit\n- * @hmc_info: pointer to the HMC configuration information struct\n- * @type: HMC resource type we're examining\n- * @idx: starting index for the object\n- * @cnt: number of objects we're trying to create\n- * @pd_index: pointer to return page descriptor index\n- * @pd_limit: pointer to return page descriptor index limit\n- *\n- * Calculates the page descriptor index and index limit for the resource\n- * defined by i40e_hmc_rsrc_type.\n- **/\n-#define I40E_FIND_PD_INDEX_LIMIT(hmc_info, type, idx, cnt, pd_index, pd_limit)\\\n-{\t\t\t\t\t\t\t\t\t\\\n-\tu64 fpm_adr, fpm_limit;\t\t\t\t\t\t\\\n-\tfpm_adr = (hmc_info)->hmc_obj[(type)].base +\t\t\t\\\n-\t\t (hmc_info)->hmc_obj[(type)].size * (idx);\t\t\\\n-\tfpm_limit = fpm_adr + (hmc_info)->hmc_obj[(type)].size * (cnt);\t\\\n-\t*(pd_index) = (u32)(fpm_adr / I40E_HMC_PAGED_BP_SIZE);\t\t\\\n-\t*(pd_limit) = (u32)((fpm_limit - 1) / I40E_HMC_PAGED_BP_SIZE);\t\\\n-\t/* add one more to the limit to correct our range */\t\t\\\n-\t*(pd_limit) += 1;\t\t\t\t\t\t\\\n-}\n-i40e_status i40e_add_sd_table_entry(struct i40e_hw *hw,\n-\t\t\t\t\t struct i40e_hmc_info *hmc_info,\n-\t\t\t\t\t u32 sd_index,\n-\t\t\t\t\t enum i40e_sd_entry_type type,\n-\t\t\t\t\t u64 direct_mode_sz);\n-\n-i40e_status i40e_add_pd_table_entry(struct i40e_hw *hw,\n-\t\t\t\t\t struct i40e_hmc_info *hmc_info,\n-\t\t\t\t\t u32 pd_index,\n-\t\t\t\t\t struct i40e_dma_mem *rsrc_pg);\n-i40e_status i40e_remove_pd_bp(struct i40e_hw *hw,\n-\t\t\t\t\tstruct i40e_hmc_info *hmc_info,\n-\t\t\t\t\tu32 idx);\n-i40e_status i40e_prep_remove_sd_bp(struct i40e_hmc_info *hmc_info,\n-\t\t\t\t\t u32 idx);\n-i40e_status i40e_remove_sd_bp_new(struct i40e_hw *hw,\n-\t\t\t\t\t struct i40e_hmc_info *hmc_info,\n-\t\t\t\t\t u32 idx, bool is_pf);\n-i40e_status i40e_prep_remove_pd_page(struct i40e_hmc_info *hmc_info,\n-\t\t\t\t\t u32 idx);\n-i40e_status i40e_remove_pd_page_new(struct i40e_hw *hw,\n-\t\t\t\t\t struct i40e_hmc_info *hmc_info,\n-\t\t\t\t\t u32 idx, bool is_pf);\n-\n-#endif /* _I40E_HMC_H_ */\ndiff --git a/drivers/net/ethernet/intel/iavf/i40e_lan_hmc.h b/drivers/net/ethernet/intel/iavf/i40e_lan_hmc.h\ndeleted file mode 100644\nindex 82b00f70a632..000000000000\n--- a/drivers/net/ethernet/intel/iavf/i40e_lan_hmc.h\n+++ /dev/null\n@@ -1,158 +0,0 @@\n-/* SPDX-License-Identifier: GPL-2.0 */\n-/* Copyright(c) 2013 - 2018 Intel Corporation. */\n-\n-#ifndef _I40E_LAN_HMC_H_\n-#define _I40E_LAN_HMC_H_\n-\n-/* forward-declare the HW struct for the compiler */\n-struct i40e_hw;\n-\n-/* HMC element context information */\n-\n-/* Rx queue context data\n- *\n- * The sizes of the variables may be larger than needed due to crossing byte\n- * boundaries. If we do not have the width of the variable set to the correct\n- * size then we could end up shifting bits off the top of the variable when the\n- * variable is at the top of a byte and crosses over into the next byte.\n- */\n-struct i40e_hmc_obj_rxq {\n-\tu16 head;\n-\tu16 cpuid; /* bigger than needed, see above for reason */\n-\tu64 base;\n-\tu16 qlen;\n-#define I40E_RXQ_CTX_DBUFF_SHIFT 7\n-\tu16 dbuff; /* bigger than needed, see above for reason */\n-#define I40E_RXQ_CTX_HBUFF_SHIFT 6\n-\tu16 hbuff; /* bigger than needed, see above for reason */\n-\tu8 dtype;\n-\tu8 dsize;\n-\tu8 crcstrip;\n-\tu8 fc_ena;\n-\tu8 l2tsel;\n-\tu8 hsplit_0;\n-\tu8 hsplit_1;\n-\tu8 showiv;\n-\tu32 rxmax; /* bigger than needed, see above for reason */\n-\tu8 tphrdesc_ena;\n-\tu8 tphwdesc_ena;\n-\tu8 tphdata_ena;\n-\tu8 tphhead_ena;\n-\tu16 lrxqthresh; /* bigger than needed, see above for reason */\n-\tu8 prefena;\t/* NOTE: normally must be set to 1 at init */\n-};\n-\n-/* Tx queue context data\n-*\n-* The sizes of the variables may be larger than needed due to crossing byte\n-* boundaries. If we do not have the width of the variable set to the correct\n-* size then we could end up shifting bits off the top of the variable when the\n-* variable is at the top of a byte and crosses over into the next byte.\n-*/\n-struct i40e_hmc_obj_txq {\n-\tu16 head;\n-\tu8 new_context;\n-\tu64 base;\n-\tu8 fc_ena;\n-\tu8 timesync_ena;\n-\tu8 fd_ena;\n-\tu8 alt_vlan_ena;\n-\tu16 thead_wb;\n-\tu8 cpuid;\n-\tu8 head_wb_ena;\n-\tu16 qlen;\n-\tu8 tphrdesc_ena;\n-\tu8 tphrpacket_ena;\n-\tu8 tphwdesc_ena;\n-\tu64 head_wb_addr;\n-\tu32 crc;\n-\tu16 rdylist;\n-\tu8 rdylist_act;\n-};\n-\n-/* for hsplit_0 field of Rx HMC context */\n-enum i40e_hmc_obj_rx_hsplit_0 {\n-\tI40E_HMC_OBJ_RX_HSPLIT_0_NO_SPLIT = 0,\n-\tI40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_L2 = 1,\n-\tI40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_IP = 2,\n-\tI40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_TCP_UDP = 4,\n-\tI40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_SCTP = 8,\n-};\n-\n-/* fcoe_cntx and fcoe_filt are for debugging purpose only */\n-struct i40e_hmc_obj_fcoe_cntx {\n-\tu32 rsv[32];\n-};\n-\n-struct i40e_hmc_obj_fcoe_filt {\n-\tu32 rsv[8];\n-};\n-\n-/* Context sizes for LAN objects */\n-enum i40e_hmc_lan_object_size {\n-\tI40E_HMC_LAN_OBJ_SZ_8 = 0x3,\n-\tI40E_HMC_LAN_OBJ_SZ_16 = 0x4,\n-\tI40E_HMC_LAN_OBJ_SZ_32 = 0x5,\n-\tI40E_HMC_LAN_OBJ_SZ_64 = 0x6,\n-\tI40E_HMC_LAN_OBJ_SZ_128 = 0x7,\n-\tI40E_HMC_LAN_OBJ_SZ_256 = 0x8,\n-\tI40E_HMC_LAN_OBJ_SZ_512 = 0x9,\n-};\n-\n-#define I40E_HMC_L2OBJ_BASE_ALIGNMENT 512\n-#define I40E_HMC_OBJ_SIZE_TXQ 128\n-#define I40E_HMC_OBJ_SIZE_RXQ 32\n-#define I40E_HMC_OBJ_SIZE_FCOE_CNTX 128\n-#define I40E_HMC_OBJ_SIZE_FCOE_FILT 64\n-\n-enum i40e_hmc_lan_rsrc_type {\n-\tI40E_HMC_LAN_FULL = 0,\n-\tI40E_HMC_LAN_TX = 1,\n-\tI40E_HMC_LAN_RX = 2,\n-\tI40E_HMC_FCOE_CTX = 3,\n-\tI40E_HMC_FCOE_FILT = 4,\n-\tI40E_HMC_LAN_MAX = 5\n-};\n-\n-enum i40e_hmc_model {\n-\tI40E_HMC_MODEL_DIRECT_PREFERRED = 0,\n-\tI40E_HMC_MODEL_DIRECT_ONLY = 1,\n-\tI40E_HMC_MODEL_PAGED_ONLY = 2,\n-\tI40E_HMC_MODEL_UNKNOWN,\n-};\n-\n-struct i40e_hmc_lan_create_obj_info {\n-\tstruct i40e_hmc_info *hmc_info;\n-\tu32 rsrc_type;\n-\tu32 start_idx;\n-\tu32 count;\n-\tenum i40e_sd_entry_type entry_type;\n-\tu64 direct_mode_sz;\n-};\n-\n-struct i40e_hmc_lan_delete_obj_info {\n-\tstruct i40e_hmc_info *hmc_info;\n-\tu32 rsrc_type;\n-\tu32 start_idx;\n-\tu32 count;\n-};\n-\n-i40e_status i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,\n-\t\t\t\t\tu32 rxq_num, u32 fcoe_cntx_num,\n-\t\t\t\t\tu32 fcoe_filt_num);\n-i40e_status i40e_configure_lan_hmc(struct i40e_hw *hw,\n-\t\t\t\t\t enum i40e_hmc_model model);\n-i40e_status i40e_shutdown_lan_hmc(struct i40e_hw *hw);\n-\n-i40e_status i40e_clear_lan_tx_queue_context(struct i40e_hw *hw,\n-\t\t\t\t\t\t u16 queue);\n-i40e_status i40e_set_lan_tx_queue_context(struct i40e_hw *hw,\n-\t\t\t\t\t\t u16 queue,\n-\t\t\t\t\t\t struct i40e_hmc_obj_txq *s);\n-i40e_status i40e_clear_lan_rx_queue_context(struct i40e_hw *hw,\n-\t\t\t\t\t\t u16 queue);\n-i40e_status i40e_set_lan_rx_queue_context(struct i40e_hw *hw,\n-\t\t\t\t\t\t u16 queue,\n-\t\t\t\t\t\t struct i40e_hmc_obj_rxq *s);\n-\n-#endif /* _I40E_LAN_HMC_H_ */\ndiff --git a/drivers/net/ethernet/intel/iavf/i40e_prototype.h b/drivers/net/ethernet/intel/iavf/i40e_prototype.h\nindex a358f4b9d5aa..ef7f74489bfc 100644\n--- a/drivers/net/ethernet/intel/iavf/i40e_prototype.h\n+++ b/drivers/net/ethernet/intel/iavf/i40e_prototype.h\n@@ -60,71 +60,12 @@ static inline struct i40e_rx_ptype_decoded decode_rx_desc_ptype(u8 ptype)\n \treturn i40evf_ptype_lookup[ptype];\n }\n \n-/* prototype for functions used for SW locks */\n-\n /* i40e_common for VF drivers*/\n void i40e_vf_parse_hw_config(struct i40e_hw *hw,\n \t\t\t struct virtchnl_vf_resource *msg);\n i40e_status i40e_vf_reset(struct i40e_hw *hw);\n i40e_status i40e_aq_send_msg_to_pf(struct i40e_hw *hw,\n-\t\t\t\tenum virtchnl_ops v_opcode,\n-\t\t\t\ti40e_status v_retval,\n-\t\t\t\tu8 *msg, u16 msglen,\n-\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\n-i40e_status i40e_set_filter_control(struct i40e_hw *hw,\n-\t\t\t\tstruct i40e_filter_control_settings *settings);\n-i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,\n-\t\t\t\tu8 *mac_addr, u16 ethtype, u16 flags,\n-\t\t\t\tu16 vsi_seid, u16 queue, bool is_add,\n-\t\t\t\tstruct i40e_control_filter_stats *stats,\n-\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\n-void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,\n-\t\t\t\t\t\t u16 vsi_seid);\n-i40e_status i40evf_aq_rx_ctl_read_register(struct i40e_hw *hw,\n-\t\t\t\tu32 reg_addr, u32 *reg_val,\n-\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\n-u32 i40evf_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr);\n-i40e_status i40evf_aq_rx_ctl_write_register(struct i40e_hw *hw,\n-\t\t\t\tu32 reg_addr, u32 reg_val,\n-\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\n-void i40evf_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val);\n-i40e_status i40e_aq_set_phy_register(struct i40e_hw *hw,\n-\t\t\t\t u8 phy_select, u8 dev_addr,\n-\t\t\t\t u32 reg_addr, u32 reg_val,\n-\t\t\t\t struct i40e_asq_cmd_details *cmd_details);\n-i40e_status i40e_aq_get_phy_register(struct i40e_hw *hw,\n-\t\t\t\t u8 phy_select, u8 dev_addr,\n-\t\t\t\t u32 reg_addr, u32 *reg_val,\n-\t\t\t\t struct i40e_asq_cmd_details *cmd_details);\n-\n-i40e_status i40e_read_phy_register(struct i40e_hw *hw, u8 page,\n-\t\t\t\t u16 reg, u8 phy_addr, u16 *value);\n-i40e_status i40e_write_phy_register(struct i40e_hw *hw, u8 page,\n-\t\t\t\t u16 reg, u8 phy_addr, u16 value);\n-i40e_status i40e_read_phy_register(struct i40e_hw *hw, u8 page, u16 reg,\n-\t\t\t\t u8 phy_addr, u16 *value);\n-i40e_status i40e_write_phy_register(struct i40e_hw *hw, u8 page, u16 reg,\n-\t\t\t\t u8 phy_addr, u16 value);\n-u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num);\n-i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,\n-\t\t\t\t u32 time, u32 interval);\n-i40e_status i40evf_aq_write_ddp(struct i40e_hw *hw, void *buff,\n-\t\t\t\tu16 buff_size, u32 track_id,\n-\t\t\t\tu32 *error_offset, u32 *error_info,\n-\t\t\t\tstruct i40e_asq_cmd_details *\n-\t\t\t\tcmd_details);\n-i40e_status i40evf_aq_get_ddp_list(struct i40e_hw *hw, void *buff,\n-\t\t\t\t u16 buff_size, u8 flags,\n-\t\t\t\t struct i40e_asq_cmd_details *\n-\t\t\t\t cmd_details);\n-struct i40e_generic_seg_header *\n-i40evf_find_segment_in_package(u32 segment_type,\n-\t\t\t struct i40e_package_header *pkg_header);\n-enum i40e_status_code\n-i40evf_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *i40e_seg,\n-\t\t u32 track_id);\n-enum i40e_status_code\n-i40evf_add_pinfo_to_list(struct i40e_hw *hw,\n-\t\t\t struct i40e_profile_segment *profile,\n-\t\t\t u8 *profile_info_sec, u32 track_id);\n+\t\t\t\t enum virtchnl_ops v_opcode,\n+\t\t\t\t i40e_status v_retval, u8 *msg, u16 msglen,\n+\t\t\t\t struct i40e_asq_cmd_details *cmd_details);\n #endif /* _I40E_PROTOTYPE_H_ */\ndiff --git a/drivers/net/ethernet/intel/iavf/i40e_register.h b/drivers/net/ethernet/intel/iavf/i40e_register.h\nindex 49e1f57d99cc..20b464ac1542 100644\n--- a/drivers/net/ethernet/intel/iavf/i40e_register.h\n+++ b/drivers/net/ethernet/intel/iavf/i40e_register.h\n@@ -4,40 +4,12 @@\n #ifndef _I40E_REGISTER_H_\n #define _I40E_REGISTER_H_\n \n-#define I40E_VFMSIX_PBA1(_i) (0x00002000 + ((_i) * 4)) /* _i=0...19 */ /* Reset: VFLR */\n-#define I40E_VFMSIX_PBA1_MAX_INDEX 19\n-#define I40E_VFMSIX_PBA1_PENBIT_SHIFT 0\n-#define I40E_VFMSIX_PBA1_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_PBA1_PENBIT_SHIFT)\n-#define I40E_VFMSIX_TADD1(_i) (0x00002100 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */\n-#define I40E_VFMSIX_TADD1_MAX_INDEX 639\n-#define I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT 0\n-#define I40E_VFMSIX_TADD1_MSIXTADD10_MASK I40E_MASK(0x3, I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT)\n-#define I40E_VFMSIX_TADD1_MSIXTADD_SHIFT 2\n-#define I40E_VFMSIX_TADD1_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_VFMSIX_TADD1_MSIXTADD_SHIFT)\n-#define I40E_VFMSIX_TMSG1(_i) (0x00002108 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */\n-#define I40E_VFMSIX_TMSG1_MAX_INDEX 639\n-#define I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT 0\n-#define I40E_VFMSIX_TMSG1_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT)\n-#define I40E_VFMSIX_TUADD1(_i) (0x00002104 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */\n-#define I40E_VFMSIX_TUADD1_MAX_INDEX 639\n-#define I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT 0\n-#define I40E_VFMSIX_TUADD1_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT)\n-#define I40E_VFMSIX_TVCTRL1(_i) (0x0000210C + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */\n-#define I40E_VFMSIX_TVCTRL1_MAX_INDEX 639\n-#define I40E_VFMSIX_TVCTRL1_MASK_SHIFT 0\n-#define I40E_VFMSIX_TVCTRL1_MASK_MASK I40E_MASK(0x1, I40E_VFMSIX_TVCTRL1_MASK_SHIFT)\n #define I40E_VF_ARQBAH1 0x00006000 /* Reset: EMPR */\n-#define I40E_VF_ARQBAH1_ARQBAH_SHIFT 0\n-#define I40E_VF_ARQBAH1_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAH1_ARQBAH_SHIFT)\n #define I40E_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */\n-#define I40E_VF_ARQBAL1_ARQBAL_SHIFT 0\n-#define I40E_VF_ARQBAL1_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAL1_ARQBAL_SHIFT)\n #define I40E_VF_ARQH1 0x00007400 /* Reset: EMPR */\n #define I40E_VF_ARQH1_ARQH_SHIFT 0\n #define I40E_VF_ARQH1_ARQH_MASK I40E_MASK(0x3FF, I40E_VF_ARQH1_ARQH_SHIFT)\n #define I40E_VF_ARQLEN1 0x00008000 /* Reset: EMPR */\n-#define I40E_VF_ARQLEN1_ARQLEN_SHIFT 0\n-#define I40E_VF_ARQLEN1_ARQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ARQLEN1_ARQLEN_SHIFT)\n #define I40E_VF_ARQLEN1_ARQVFE_SHIFT 28\n #define I40E_VF_ARQLEN1_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQVFE_SHIFT)\n #define I40E_VF_ARQLEN1_ARQOVFL_SHIFT 29\n@@ -47,20 +19,10 @@\n #define I40E_VF_ARQLEN1_ARQENABLE_SHIFT 31\n #define I40E_VF_ARQLEN1_ARQENABLE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQENABLE_SHIFT)\n #define I40E_VF_ARQT1 0x00007000 /* Reset: EMPR */\n-#define I40E_VF_ARQT1_ARQT_SHIFT 0\n-#define I40E_VF_ARQT1_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT1_ARQT_SHIFT)\n #define I40E_VF_ATQBAH1 0x00007800 /* Reset: EMPR */\n-#define I40E_VF_ATQBAH1_ATQBAH_SHIFT 0\n-#define I40E_VF_ATQBAH1_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH1_ATQBAH_SHIFT)\n #define I40E_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */\n-#define I40E_VF_ATQBAL1_ATQBAL_SHIFT 0\n-#define I40E_VF_ATQBAL1_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAL1_ATQBAL_SHIFT)\n #define I40E_VF_ATQH1 0x00006400 /* Reset: EMPR */\n-#define I40E_VF_ATQH1_ATQH_SHIFT 0\n-#define I40E_VF_ATQH1_ATQH_MASK I40E_MASK(0x3FF, I40E_VF_ATQH1_ATQH_SHIFT)\n #define I40E_VF_ATQLEN1 0x00006800 /* Reset: EMPR */\n-#define I40E_VF_ATQLEN1_ATQLEN_SHIFT 0\n-#define I40E_VF_ATQLEN1_ATQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ATQLEN1_ATQLEN_SHIFT)\n #define I40E_VF_ATQLEN1_ATQVFE_SHIFT 28\n #define I40E_VF_ATQLEN1_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQVFE_SHIFT)\n #define I40E_VF_ATQLEN1_ATQOVFL_SHIFT 29\n@@ -70,244 +32,37 @@\n #define I40E_VF_ATQLEN1_ATQENABLE_SHIFT 31\n #define I40E_VF_ATQLEN1_ATQENABLE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQENABLE_SHIFT)\n #define I40E_VF_ATQT1 0x00008400 /* Reset: EMPR */\n-#define I40E_VF_ATQT1_ATQT_SHIFT 0\n-#define I40E_VF_ATQT1_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT1_ATQT_SHIFT)\n #define I40E_VFGEN_RSTAT 0x00008800 /* Reset: VFR */\n #define I40E_VFGEN_RSTAT_VFR_STATE_SHIFT 0\n #define I40E_VFGEN_RSTAT_VFR_STATE_MASK I40E_MASK(0x3, I40E_VFGEN_RSTAT_VFR_STATE_SHIFT)\n #define I40E_VFINT_DYN_CTL01 0x00005C00 /* Reset: VFR */\n #define I40E_VFINT_DYN_CTL01_INTENA_SHIFT 0\n #define I40E_VFINT_DYN_CTL01_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_INTENA_SHIFT)\n-#define I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT 1\n-#define I40E_VFINT_DYN_CTL01_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT)\n-#define I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT 2\n-#define I40E_VFINT_DYN_CTL01_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT)\n #define I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT 3\n #define I40E_VFINT_DYN_CTL01_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT)\n-#define I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT 5\n-#define I40E_VFINT_DYN_CTL01_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT)\n-#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT 24\n-#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT)\n-#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT 25\n-#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT)\n-#define I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT 31\n-#define I40E_VFINT_DYN_CTL01_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT)\n #define I40E_VFINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */\n-#define I40E_VFINT_DYN_CTLN1_MAX_INDEX 15\n #define I40E_VFINT_DYN_CTLN1_INTENA_SHIFT 0\n #define I40E_VFINT_DYN_CTLN1_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_INTENA_SHIFT)\n-#define I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT 1\n-#define I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT)\n #define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT 2\n #define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT)\n #define I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT 3\n #define I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT)\n #define I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT 5\n-#define I40E_VFINT_DYN_CTLN1_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT)\n #define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT 24\n #define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT)\n-#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT 25\n-#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT)\n-#define I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT 31\n-#define I40E_VFINT_DYN_CTLN1_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT)\n #define I40E_VFINT_ICR0_ENA1 0x00005000 /* Reset: CORER */\n-#define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT 25\n-#define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT)\n #define I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT 30\n #define I40E_VFINT_ICR0_ENA1_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT)\n #define I40E_VFINT_ICR0_ENA1_RSVD_SHIFT 31\n-#define I40E_VFINT_ICR0_ENA1_RSVD_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_RSVD_SHIFT)\n #define I40E_VFINT_ICR01 0x00004800 /* Reset: CORER */\n-#define I40E_VFINT_ICR01_INTEVENT_SHIFT 0\n-#define I40E_VFINT_ICR01_INTEVENT_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_INTEVENT_SHIFT)\n-#define I40E_VFINT_ICR01_QUEUE_0_SHIFT 1\n-#define I40E_VFINT_ICR01_QUEUE_0_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_0_SHIFT)\n-#define I40E_VFINT_ICR01_QUEUE_1_SHIFT 2\n-#define I40E_VFINT_ICR01_QUEUE_1_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_1_SHIFT)\n-#define I40E_VFINT_ICR01_QUEUE_2_SHIFT 3\n-#define I40E_VFINT_ICR01_QUEUE_2_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_2_SHIFT)\n-#define I40E_VFINT_ICR01_QUEUE_3_SHIFT 4\n-#define I40E_VFINT_ICR01_QUEUE_3_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_3_SHIFT)\n-#define I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT 25\n-#define I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT)\n-#define I40E_VFINT_ICR01_ADMINQ_SHIFT 30\n-#define I40E_VFINT_ICR01_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_ADMINQ_SHIFT)\n-#define I40E_VFINT_ICR01_SWINT_SHIFT 31\n-#define I40E_VFINT_ICR01_SWINT_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_SWINT_SHIFT)\n-#define I40E_VFINT_ITR01(_i) (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset: VFR */\n-#define I40E_VFINT_ITR01_MAX_INDEX 2\n-#define I40E_VFINT_ITR01_INTERVAL_SHIFT 0\n-#define I40E_VFINT_ITR01_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITR01_INTERVAL_SHIFT)\n #define I40E_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */ /* Reset: VFR */\n-#define I40E_VFINT_ITRN1_MAX_INDEX 2\n-#define I40E_VFINT_ITRN1_INTERVAL_SHIFT 0\n-#define I40E_VFINT_ITRN1_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITRN1_INTERVAL_SHIFT)\n-#define I40E_VFINT_STAT_CTL01 0x00005400 /* Reset: CORER */\n-#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT 2\n-#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT)\n #define I40E_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: CORER */\n-#define I40E_QRX_TAIL1_MAX_INDEX 15\n-#define I40E_QRX_TAIL1_TAIL_SHIFT 0\n-#define I40E_QRX_TAIL1_TAIL_MASK I40E_MASK(0x1FFF, I40E_QRX_TAIL1_TAIL_SHIFT)\n #define I40E_QTX_TAIL1(_Q) (0x00000000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: PFR */\n-#define I40E_QTX_TAIL1_MAX_INDEX 15\n-#define I40E_QTX_TAIL1_TAIL_SHIFT 0\n-#define I40E_QTX_TAIL1_TAIL_MASK I40E_MASK(0x1FFF, I40E_QTX_TAIL1_TAIL_SHIFT)\n-#define I40E_VFMSIX_PBA 0x00002000 /* Reset: VFLR */\n-#define I40E_VFMSIX_PBA_PENBIT_SHIFT 0\n-#define I40E_VFMSIX_PBA_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_PBA_PENBIT_SHIFT)\n-#define I40E_VFMSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */\n-#define I40E_VFMSIX_TADD_MAX_INDEX 16\n-#define I40E_VFMSIX_TADD_MSIXTADD10_SHIFT 0\n-#define I40E_VFMSIX_TADD_MSIXTADD10_MASK I40E_MASK(0x3, I40E_VFMSIX_TADD_MSIXTADD10_SHIFT)\n-#define I40E_VFMSIX_TADD_MSIXTADD_SHIFT 2\n-#define I40E_VFMSIX_TADD_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_VFMSIX_TADD_MSIXTADD_SHIFT)\n-#define I40E_VFMSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */\n-#define I40E_VFMSIX_TMSG_MAX_INDEX 16\n-#define I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT 0\n-#define I40E_VFMSIX_TMSG_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT)\n-#define I40E_VFMSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */\n-#define I40E_VFMSIX_TUADD_MAX_INDEX 16\n-#define I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT 0\n-#define I40E_VFMSIX_TUADD_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT)\n-#define I40E_VFMSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */\n-#define I40E_VFMSIX_TVCTRL_MAX_INDEX 16\n-#define I40E_VFMSIX_TVCTRL_MASK_SHIFT 0\n-#define I40E_VFMSIX_TVCTRL_MASK_MASK I40E_MASK(0x1, I40E_VFMSIX_TVCTRL_MASK_SHIFT)\n-#define I40E_VFCM_PE_ERRDATA 0x0000DC00 /* Reset: VFR */\n-#define I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT 0\n-#define I40E_VFCM_PE_ERRDATA_ERROR_CODE_MASK I40E_MASK(0xF, I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT)\n-#define I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT 4\n-#define I40E_VFCM_PE_ERRDATA_Q_TYPE_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT)\n-#define I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT 8\n-#define I40E_VFCM_PE_ERRDATA_Q_NUM_MASK I40E_MASK(0x3FFFF, I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT)\n-#define I40E_VFCM_PE_ERRINFO 0x0000D800 /* Reset: VFR */\n-#define I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT 0\n-#define I40E_VFCM_PE_ERRINFO_ERROR_VALID_MASK I40E_MASK(0x1, I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT)\n-#define I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT 4\n-#define I40E_VFCM_PE_ERRINFO_ERROR_INST_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT)\n-#define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT 8\n-#define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT)\n-#define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT 16\n-#define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT)\n-#define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT 24\n-#define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT)\n #define I40E_VFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */\n-#define I40E_VFQF_HENA_MAX_INDEX 1\n-#define I40E_VFQF_HENA_PTYPE_ENA_SHIFT 0\n-#define I40E_VFQF_HENA_PTYPE_ENA_MASK I40E_MASK(0xFFFFFFFF, I40E_VFQF_HENA_PTYPE_ENA_SHIFT)\n #define I40E_VFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */\n #define I40E_VFQF_HKEY_MAX_INDEX 12\n-#define I40E_VFQF_HKEY_KEY_0_SHIFT 0\n-#define I40E_VFQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_0_SHIFT)\n-#define I40E_VFQF_HKEY_KEY_1_SHIFT 8\n-#define I40E_VFQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_1_SHIFT)\n-#define I40E_VFQF_HKEY_KEY_2_SHIFT 16\n-#define I40E_VFQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_2_SHIFT)\n-#define I40E_VFQF_HKEY_KEY_3_SHIFT 24\n-#define I40E_VFQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_3_SHIFT)\n #define I40E_VFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */\n #define I40E_VFQF_HLUT_MAX_INDEX 15\n-#define I40E_VFQF_HLUT_LUT0_SHIFT 0\n-#define I40E_VFQF_HLUT_LUT0_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT0_SHIFT)\n-#define I40E_VFQF_HLUT_LUT1_SHIFT 8\n-#define I40E_VFQF_HLUT_LUT1_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT1_SHIFT)\n-#define I40E_VFQF_HLUT_LUT2_SHIFT 16\n-#define I40E_VFQF_HLUT_LUT2_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT2_SHIFT)\n-#define I40E_VFQF_HLUT_LUT3_SHIFT 24\n-#define I40E_VFQF_HLUT_LUT3_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT3_SHIFT)\n-#define I40E_VFQF_HREGION(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */\n-#define I40E_VFQF_HREGION_MAX_INDEX 7\n-#define I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT 0\n-#define I40E_VFQF_HREGION_OVERRIDE_ENA_0_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT)\n-#define I40E_VFQF_HREGION_REGION_0_SHIFT 1\n-#define I40E_VFQF_HREGION_REGION_0_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_0_SHIFT)\n-#define I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT 4\n-#define I40E_VFQF_HREGION_OVERRIDE_ENA_1_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT)\n-#define I40E_VFQF_HREGION_REGION_1_SHIFT 5\n-#define I40E_VFQF_HREGION_REGION_1_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_1_SHIFT)\n-#define I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT 8\n-#define I40E_VFQF_HREGION_OVERRIDE_ENA_2_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT)\n-#define I40E_VFQF_HREGION_REGION_2_SHIFT 9\n-#define I40E_VFQF_HREGION_REGION_2_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_2_SHIFT)\n-#define I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT 12\n-#define I40E_VFQF_HREGION_OVERRIDE_ENA_3_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT)\n-#define I40E_VFQF_HREGION_REGION_3_SHIFT 13\n-#define I40E_VFQF_HREGION_REGION_3_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_3_SHIFT)\n-#define I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT 16\n-#define I40E_VFQF_HREGION_OVERRIDE_ENA_4_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT)\n-#define I40E_VFQF_HREGION_REGION_4_SHIFT 17\n-#define I40E_VFQF_HREGION_REGION_4_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_4_SHIFT)\n-#define I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT 20\n-#define I40E_VFQF_HREGION_OVERRIDE_ENA_5_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT)\n-#define I40E_VFQF_HREGION_REGION_5_SHIFT 21\n-#define I40E_VFQF_HREGION_REGION_5_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_5_SHIFT)\n-#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24\n-#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT)\n-#define I40E_VFQF_HREGION_REGION_6_SHIFT 25\n-#define I40E_VFQF_HREGION_REGION_6_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_6_SHIFT)\n-#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28\n-#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT)\n-#define I40E_VFQF_HREGION_REGION_7_SHIFT 29\n-#define I40E_VFQF_HREGION_REGION_7_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_7_SHIFT)\n-#define I40E_VFINT_DYN_CTL01_WB_ON_ITR_SHIFT 30\n-#define I40E_VFINT_DYN_CTL01_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_WB_ON_ITR_SHIFT)\n #define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT 30\n #define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT)\n-#define I40E_VFPE_AEQALLOC1 0x0000A400 /* Reset: VFR */\n-#define I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT 0\n-#define I40E_VFPE_AEQALLOC1_AECOUNT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT)\n-#define I40E_VFPE_CCQPHIGH1 0x00009800 /* Reset: VFR */\n-#define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT 0\n-#define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT)\n-#define I40E_VFPE_CCQPLOW1 0x0000AC00 /* Reset: VFR */\n-#define I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT 0\n-#define I40E_VFPE_CCQPLOW1_PECCQPLOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT)\n-#define I40E_VFPE_CCQPSTATUS1 0x0000B800 /* Reset: VFR */\n-#define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT 0\n-#define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT)\n-#define I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT 4\n-#define I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_MASK I40E_MASK(0x7, I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT)\n-#define I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT 16\n-#define I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_MASK I40E_MASK(0x3F, I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT)\n-#define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT 31\n-#define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT)\n-#define I40E_VFPE_CQACK1 0x0000B000 /* Reset: VFR */\n-#define I40E_VFPE_CQACK1_PECQID_SHIFT 0\n-#define I40E_VFPE_CQACK1_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQACK1_PECQID_SHIFT)\n-#define I40E_VFPE_CQARM1 0x0000B400 /* Reset: VFR */\n-#define I40E_VFPE_CQARM1_PECQID_SHIFT 0\n-#define I40E_VFPE_CQARM1_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQARM1_PECQID_SHIFT)\n-#define I40E_VFPE_CQPDB1 0x0000BC00 /* Reset: VFR */\n-#define I40E_VFPE_CQPDB1_WQHEAD_SHIFT 0\n-#define I40E_VFPE_CQPDB1_WQHEAD_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPDB1_WQHEAD_SHIFT)\n-#define I40E_VFPE_CQPERRCODES1 0x00009C00 /* Reset: VFR */\n-#define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT 0\n-#define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT)\n-#define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT 16\n-#define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT)\n-#define I40E_VFPE_CQPTAIL1 0x0000A000 /* Reset: VFR */\n-#define I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT 0\n-#define I40E_VFPE_CQPTAIL1_WQTAIL_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT)\n-#define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT 31\n-#define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT)\n-#define I40E_VFPE_IPCONFIG01 0x00008C00 /* Reset: VFR */\n-#define I40E_VFPE_IPCONFIG01_PEIPID_SHIFT 0\n-#define I40E_VFPE_IPCONFIG01_PEIPID_MASK I40E_MASK(0xFFFF, I40E_VFPE_IPCONFIG01_PEIPID_SHIFT)\n-#define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT 16\n-#define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_MASK I40E_MASK(0x1, I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT)\n-#define I40E_VFPE_MRTEIDXMASK1 0x00009000 /* Reset: VFR */\n-#define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT 0\n-#define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_MASK I40E_MASK(0x1F, I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT)\n-#define I40E_VFPE_RCVUNEXPECTEDERROR1 0x00009400 /* Reset: VFR */\n-#define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT 0\n-#define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_MASK I40E_MASK(0xFFFFFF, I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT)\n-#define I40E_VFPE_TCPNOWTIMER1 0x0000A800 /* Reset: VFR */\n-#define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT 0\n-#define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT)\n-#define I40E_VFPE_WQEALLOC1 0x0000C000 /* Reset: VFR */\n-#define I40E_VFPE_WQEALLOC1_PEQPID_SHIFT 0\n-#define I40E_VFPE_WQEALLOC1_PEQPID_MASK I40E_MASK(0x3FFFF, I40E_VFPE_WQEALLOC1_PEQPID_SHIFT)\n-#define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT 20\n-#define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_MASK I40E_MASK(0xFFF, I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT)\n #endif /* _I40E_REGISTER_H_ */\ndiff --git a/drivers/net/ethernet/intel/iavf/i40e_type.h b/drivers/net/ethernet/intel/iavf/i40e_type.h\nindex 094387db3c11..8f1344094bc9 100644\n--- a/drivers/net/ethernet/intel/iavf/i40e_type.h\n+++ b/drivers/net/ethernet/intel/iavf/i40e_type.h\n@@ -8,26 +8,16 @@\n #include \"i40e_osdep.h\"\n #include \"i40e_register.h\"\n #include \"i40e_adminq.h\"\n-#include \"i40e_hmc.h\"\n-#include \"i40e_lan_hmc.h\"\n #include \"i40e_devids.h\"\n \n+#define I40E_RXQ_CTX_DBUFF_SHIFT 7\n+\n /* I40E_MASK is a macro used on 32 bit registers */\n #define I40E_MASK(mask, shift) ((u32)(mask) << (shift))\n \n #define I40E_MAX_VSI_QP\t\t\t16\n #define I40E_MAX_VF_VSI\t\t\t3\n #define I40E_MAX_CHAINED_RX_BUFFERS\t5\n-#define I40E_MAX_PF_UDP_OFFLOAD_PORTS\t16\n-\n-/* Max default timeout in ms, */\n-#define I40E_MAX_NVM_TIMEOUT\t\t18000\n-\n-/* Max timeout in ms for the phy to respond */\n-#define I40E_MAX_PHY_TIMEOUT\t\t500\n-\n-/* Switch from ms to the 1usec global time (this is the GTIME resolution) */\n-#define I40E_MS_TO_GTIME(time)\t\t((time) * 1000)\n \n /* forward declaration */\n struct i40e_hw;\n@@ -88,33 +78,6 @@ enum i40e_mac_type {\n \tI40E_MAC_GENERIC,\n };\n \n-enum i40e_media_type {\n-\tI40E_MEDIA_TYPE_UNKNOWN = 0,\n-\tI40E_MEDIA_TYPE_FIBER,\n-\tI40E_MEDIA_TYPE_BASET,\n-\tI40E_MEDIA_TYPE_BACKPLANE,\n-\tI40E_MEDIA_TYPE_CX4,\n-\tI40E_MEDIA_TYPE_DA,\n-\tI40E_MEDIA_TYPE_VIRTUAL\n-};\n-\n-enum i40e_fc_mode {\n-\tI40E_FC_NONE = 0,\n-\tI40E_FC_RX_PAUSE,\n-\tI40E_FC_TX_PAUSE,\n-\tI40E_FC_FULL,\n-\tI40E_FC_PFC,\n-\tI40E_FC_DEFAULT\n-};\n-\n-enum i40e_set_fc_aq_failures {\n-\tI40E_SET_FC_AQ_FAIL_NONE = 0,\n-\tI40E_SET_FC_AQ_FAIL_GET = 1,\n-\tI40E_SET_FC_AQ_FAIL_SET = 2,\n-\tI40E_SET_FC_AQ_FAIL_UPDATE = 4,\n-\tI40E_SET_FC_AQ_FAIL_SET_UPDATE = 6\n-};\n-\n enum i40e_vsi_type {\n \tI40E_VSI_MAIN\t= 0,\n \tI40E_VSI_VMDQ1\t= 1,\n@@ -134,162 +97,16 @@ enum i40e_queue_type {\n \tI40E_QUEUE_TYPE_UNKNOWN\n };\n \n-struct i40e_link_status {\n-\tenum i40e_aq_phy_type phy_type;\n-\tenum i40e_aq_link_speed link_speed;\n-\tu8 link_info;\n-\tu8 an_info;\n-\tu8 req_fec_info;\n-\tu8 fec_info;\n-\tu8 ext_info;\n-\tu8 loopback;\n-\t/* is Link Status Event notification to SW enabled */\n-\tbool lse_enable;\n-\tu16 max_frame_size;\n-\tbool crc_enable;\n-\tu8 pacing;\n-\tu8 requested_speeds;\n-\tu8 module_type[3];\n-\t/* 1st byte: module identifier */\n-#define I40E_MODULE_TYPE_SFP\t\t0x03\n-#define I40E_MODULE_TYPE_QSFP\t\t0x0D\n-\t/* 2nd byte: ethernet compliance codes for 10/40G */\n-#define I40E_MODULE_TYPE_40G_ACTIVE\t0x01\n-#define I40E_MODULE_TYPE_40G_LR4\t0x02\n-#define I40E_MODULE_TYPE_40G_SR4\t0x04\n-#define I40E_MODULE_TYPE_40G_CR4\t0x08\n-#define I40E_MODULE_TYPE_10G_BASE_SR\t0x10\n-#define I40E_MODULE_TYPE_10G_BASE_LR\t0x20\n-#define I40E_MODULE_TYPE_10G_BASE_LRM\t0x40\n-#define I40E_MODULE_TYPE_10G_BASE_ER\t0x80\n-\t/* 3rd byte: ethernet compliance codes for 1G */\n-#define I40E_MODULE_TYPE_1000BASE_SX\t0x01\n-#define I40E_MODULE_TYPE_1000BASE_LX\t0x02\n-#define I40E_MODULE_TYPE_1000BASE_CX\t0x04\n-#define I40E_MODULE_TYPE_1000BASE_T\t0x08\n-};\n-\n-struct i40e_phy_info {\n-\tstruct i40e_link_status link_info;\n-\tstruct i40e_link_status link_info_old;\n-\tbool get_link_info;\n-\tenum i40e_media_type media_type;\n-\t/* all the phy types the NVM is capable of */\n-\tu64 phy_types;\n-};\n-\n-#define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)\n-#define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)\n-#define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)\n-#define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)\n-#define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)\n-#define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)\n-#define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)\n-#define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)\n-#define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)\n-#define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)\n-#define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)\n-#define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)\n-#define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)\n-#define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)\n-#define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)\n-#define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)\n-#define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)\n-#define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)\n-#define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)\n-#define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)\n-#define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)\n-#define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)\n-#define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)\n-#define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)\n-#define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)\n-#define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)\n-#define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \\\n-\t\t\t\tBIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)\n-#define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)\n-/* Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some\n- * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit\n- * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,\n- * a shift is needed to adjust for this with values larger than 31. The\n- * only affected values are I40E_PHY_TYPE_25GBASE_*.\n- */\n-#define I40E_PHY_TYPE_OFFSET 1\n-#define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \\\n-\t\t\t\t\t I40E_PHY_TYPE_OFFSET)\n-#define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \\\n-\t\t\t\t\t I40E_PHY_TYPE_OFFSET)\n-#define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \\\n-\t\t\t\t\t I40E_PHY_TYPE_OFFSET)\n-#define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \\\n-\t\t\t\t\t I40E_PHY_TYPE_OFFSET)\n-#define I40E_HW_CAP_MAX_GPIO\t\t\t30\n+#define I40E_HW_CAP_MAX_GPIO\t\t30\n /* Capabilities of a PF or a VF or the whole device */\n struct i40e_hw_capabilities {\n-\tu32 switch_mode;\n-#define I40E_NVM_IMAGE_TYPE_EVB\t\t0x0\n-#define I40E_NVM_IMAGE_TYPE_CLOUD\t0x2\n-#define I40E_NVM_IMAGE_TYPE_UDP_CLOUD\t0x3\n-\n-\tu32 management_mode;\n-\tu32 mng_protocols_over_mctp;\n-#define I40E_MNG_PROTOCOL_PLDM\t\t0x2\n-#define I40E_MNG_PROTOCOL_OEM_COMMANDS\t0x4\n-#define I40E_MNG_PROTOCOL_NCSI\t\t0x8\n-\tu32 npar_enable;\n-\tu32 os2bmc;\n-\tu32 valid_functions;\n-\tbool sr_iov_1_1;\n-\tbool vmdq;\n-\tbool evb_802_1_qbg; /* Edge Virtual Bridging */\n-\tbool evb_802_1_qbh; /* Bridge Port Extension */\n \tbool dcb;\n \tbool fcoe;\n-\tbool iscsi; /* Indicates iSCSI enabled */\n-\tbool flex10_enable;\n-\tbool flex10_capable;\n-\tu32 flex10_mode;\n-#define I40E_FLEX10_MODE_UNKNOWN\t0x0\n-#define I40E_FLEX10_MODE_DCC\t\t0x1\n-#define I40E_FLEX10_MODE_DCI\t\t0x2\n-\n-\tu32 flex10_status;\n-#define I40E_FLEX10_STATUS_DCC_ERROR\t0x1\n-#define I40E_FLEX10_STATUS_VC_MODE\t0x2\n-\n-\tbool sec_rev_disabled;\n-\tbool update_disabled;\n-#define I40E_NVM_MGMT_SEC_REV_DISABLED\t0x1\n-#define I40E_NVM_MGMT_UPDATE_DISABLED\t0x2\n-\n-\tbool mgmt_cem;\n-\tbool ieee_1588;\n-\tbool iwarp;\n-\tbool fd;\n-\tu32 fd_filters_guaranteed;\n-\tu32 fd_filters_best_effort;\n-\tbool rss;\n-\tu32 rss_table_size;\n-\tu32 rss_table_entry_width;\n-\tbool led[I40E_HW_CAP_MAX_GPIO];\n-\tbool sdp[I40E_HW_CAP_MAX_GPIO];\n-\tu32 nvm_image_type;\n-\tu32 num_flow_director_filters;\n-\tu32 num_vfs;\n-\tu32 vf_base_id;\n \tu32 num_vsis;\n \tu32 num_rx_qp;\n \tu32 num_tx_qp;\n \tu32 base_queue;\n-\tu32 num_msix_vectors;\n \tu32 num_msix_vectors_vf;\n-\tu32 led_pin_num;\n-\tu32 sdp_pin_num;\n-\tu32 mdio_port_num;\n-\tu32 mdio_port_mode;\n-\tu8 rx_buf_chain_len;\n-\tu32 enabled_tcmap;\n-\tu32 maxtc;\n-\tu64 wr_csr_prot;\n };\n \n struct i40e_mac_info {\n@@ -300,106 +117,6 @@ struct i40e_mac_info {\n \tu16 max_fcoeq;\n };\n \n-enum i40e_aq_resources_ids {\n-\tI40E_NVM_RESOURCE_ID = 1\n-};\n-\n-enum i40e_aq_resource_access_type {\n-\tI40E_RESOURCE_READ = 1,\n-\tI40E_RESOURCE_WRITE\n-};\n-\n-struct i40e_nvm_info {\n-\tu64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */\n-\tu32 timeout; /* [ms] */\n-\tu16 sr_size; /* Shadow RAM size in words */\n-\tbool blank_nvm_mode; /* is NVM empty (no FW present)*/\n-\tu16 version; /* NVM package version */\n-\tu32 eetrack; /* NVM data version */\n-\tu32 oem_ver; /* OEM version info */\n-};\n-\n-/* definitions used in NVM update support */\n-\n-enum i40e_nvmupd_cmd {\n-\tI40E_NVMUPD_INVALID,\n-\tI40E_NVMUPD_READ_CON,\n-\tI40E_NVMUPD_READ_SNT,\n-\tI40E_NVMUPD_READ_LCB,\n-\tI40E_NVMUPD_READ_SA,\n-\tI40E_NVMUPD_WRITE_ERA,\n-\tI40E_NVMUPD_WRITE_CON,\n-\tI40E_NVMUPD_WRITE_SNT,\n-\tI40E_NVMUPD_WRITE_LCB,\n-\tI40E_NVMUPD_WRITE_SA,\n-\tI40E_NVMUPD_CSUM_CON,\n-\tI40E_NVMUPD_CSUM_SA,\n-\tI40E_NVMUPD_CSUM_LCB,\n-\tI40E_NVMUPD_STATUS,\n-\tI40E_NVMUPD_EXEC_AQ,\n-\tI40E_NVMUPD_GET_AQ_RESULT,\n-\tI40E_NVMUPD_GET_AQ_EVENT,\n-};\n-\n-enum i40e_nvmupd_state {\n-\tI40E_NVMUPD_STATE_INIT,\n-\tI40E_NVMUPD_STATE_READING,\n-\tI40E_NVMUPD_STATE_WRITING,\n-\tI40E_NVMUPD_STATE_INIT_WAIT,\n-\tI40E_NVMUPD_STATE_WRITE_WAIT,\n-\tI40E_NVMUPD_STATE_ERROR\n-};\n-\n-/* nvm_access definition and its masks/shifts need to be accessible to\n- * application, core driver, and shared code. Where is the right file?\n- */\n-#define I40E_NVM_READ\t0xB\n-#define I40E_NVM_WRITE\t0xC\n-\n-#define I40E_NVM_MOD_PNT_MASK 0xFF\n-\n-#define I40E_NVM_TRANS_SHIFT\t\t\t8\n-#define I40E_NVM_TRANS_MASK\t\t\t(0xf << I40E_NVM_TRANS_SHIFT)\n-#define I40E_NVM_PRESERVATION_FLAGS_SHIFT\t12\n-#define I40E_NVM_PRESERVATION_FLAGS_MASK \\\n-\t\t\t\t(0x3 << I40E_NVM_PRESERVATION_FLAGS_SHIFT)\n-#define I40E_NVM_PRESERVATION_FLAGS_SELECTED\t0x01\n-#define I40E_NVM_PRESERVATION_FLAGS_ALL\t\t0x02\n-#define I40E_NVM_CON\t\t\t\t0x0\n-#define I40E_NVM_SNT\t\t\t\t0x1\n-#define I40E_NVM_LCB\t\t\t\t0x2\n-#define I40E_NVM_SA\t\t\t\t(I40E_NVM_SNT | I40E_NVM_LCB)\n-#define I40E_NVM_ERA\t\t\t\t0x4\n-#define I40E_NVM_CSUM\t\t\t\t0x8\n-#define I40E_NVM_AQE\t\t\t\t0xe\n-#define I40E_NVM_EXEC\t\t\t\t0xf\n-\n-#define I40E_NVM_ADAPT_SHIFT\t16\n-#define I40E_NVM_ADAPT_MASK\t(0xffff << I40E_NVM_ADAPT_SHIFT)\n-\n-#define I40E_NVMUPD_MAX_DATA\t4096\n-#define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */\n-\n-struct i40e_nvm_access {\n-\tu32 command;\n-\tu32 config;\n-\tu32 offset;\t/* in bytes */\n-\tu32 data_size;\t/* in bytes */\n-\tu8 data[1];\n-};\n-\n-/* (Q)SFP module access definitions */\n-#define I40E_I2C_EEPROM_DEV_ADDR\t0xA0\n-#define I40E_I2C_EEPROM_DEV_ADDR2\t0xA2\n-#define I40E_MODULE_TYPE_ADDR\t\t0x00\n-#define I40E_MODULE_REVISION_ADDR\t0x01\n-#define I40E_MODULE_SFF_8472_COMP\t0x5E\n-#define I40E_MODULE_SFF_8472_SWAP\t0x5C\n-#define I40E_MODULE_SFF_ADDR_MODE\t0x04\n-#define I40E_MODULE_TYPE_QSFP_PLUS\t0x0D\n-#define I40E_MODULE_TYPE_QSFP28\t\t0x11\n-#define I40E_MODULE_QSFP_MAX_LEN\t640\n-\n /* PCI bus types */\n enum i40e_bus_type {\n \ti40e_bus_type_unknown = 0,\n@@ -447,69 +164,16 @@ struct i40e_bus_info {\n \tu16 bus_id;\n };\n \n-/* Flow control (FC) parameters */\n-struct i40e_fc_info {\n-\tenum i40e_fc_mode current_mode; /* FC mode in effect */\n-\tenum i40e_fc_mode requested_mode; /* FC mode requested by caller */\n-};\n-\n #define I40E_MAX_TRAFFIC_CLASS\t\t8\n #define I40E_MAX_USER_PRIORITY\t\t8\n-#define I40E_DCBX_MAX_APPS\t\t32\n-#define I40E_LLDPDU_SIZE\t\t1500\n-\n-/* IEEE 802.1Qaz ETS Configuration data */\n-struct i40e_ieee_ets_config {\n-\tu8 willing;\n-\tu8 cbs;\n-\tu8 maxtcs;\n-\tu8 prioritytable[I40E_MAX_TRAFFIC_CLASS];\n-\tu8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];\n-\tu8 tsatable[I40E_MAX_TRAFFIC_CLASS];\n-};\n-\n-/* IEEE 802.1Qaz ETS Recommendation data */\n-struct i40e_ieee_ets_recommend {\n-\tu8 prioritytable[I40E_MAX_TRAFFIC_CLASS];\n-\tu8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];\n-\tu8 tsatable[I40E_MAX_TRAFFIC_CLASS];\n-};\n-\n-/* IEEE 802.1Qaz PFC Configuration data */\n-struct i40e_ieee_pfc_config {\n-\tu8 willing;\n-\tu8 mbc;\n-\tu8 pfccap;\n-\tu8 pfcenable;\n-};\n-\n-/* IEEE 802.1Qaz Application Priority data */\n-struct i40e_ieee_app_priority_table {\n-\tu8 priority;\n-\tu8 selector;\n-\tu16 protocolid;\n-};\n-\n-struct i40e_dcbx_config {\n-\tu32 numapps;\n-\tu32 tlv_status; /* CEE mode TLV status */\n-\tstruct i40e_ieee_ets_config etscfg;\n-\tstruct i40e_ieee_ets_recommend etsrec;\n-\tstruct i40e_ieee_pfc_config pfc;\n-\tstruct i40e_ieee_app_priority_table app[I40E_DCBX_MAX_APPS];\n-};\n-\n /* Port hardware description */\n struct i40e_hw {\n \tu8 __iomem *hw_addr;\n \tvoid *back;\n \n \t/* subsystem structs */\n-\tstruct i40e_phy_info phy;\n \tstruct i40e_mac_info mac;\n \tstruct i40e_bus_info bus;\n-\tstruct i40e_nvm_info nvm;\n-\tstruct i40e_fc_info fc;\n \n \t/* pci info */\n \tu16 device_id;\n@@ -517,58 +181,13 @@ struct i40e_hw {\n \tu16 subsystem_device_id;\n \tu16 subsystem_vendor_id;\n \tu8 revision_id;\n-\tu8 port;\n-\tbool adapter_stopped;\n \n \t/* capabilities for entire device and PCI func */\n \tstruct i40e_hw_capabilities dev_caps;\n-\tstruct i40e_hw_capabilities func_caps;\n-\n-\t/* Flow Director shared filter space */\n-\tu16 fdir_shared_filter_count;\n-\n-\t/* device profile info */\n-\tu8 pf_id;\n-\tu16 main_vsi_seid;\n-\n-\t/* for multi-function MACs */\n-\tu16 partition_id;\n-\tu16 num_partitions;\n-\tu16 num_ports;\n-\n-\t/* Closest numa node to the device */\n-\tu16 numa_node;\n \n \t/* Admin Queue info */\n \tstruct i40e_adminq_info aq;\n \n-\t/* state of nvm update process */\n-\tenum i40e_nvmupd_state nvmupd_state;\n-\tstruct i40e_aq_desc nvm_wb_desc;\n-\tstruct i40e_aq_desc nvm_aq_event_desc;\n-\tstruct i40e_virt_mem nvm_buff;\n-\tbool nvm_release_on_done;\n-\tu16 nvm_wait_opcode;\n-\n-\t/* HMC info */\n-\tstruct i40e_hmc_info hmc; /* HMC info struct */\n-\n-\t/* LLDP/DCBX Status */\n-\tu16 dcbx_status;\n-\n-#define I40E_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1)\n-#define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2)\n-\n-\t/* DCBX info */\n-\tstruct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */\n-\tstruct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */\n-\tstruct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */\n-\n-\t/* Used in set switch config AQ command */\n-\tu16 switch_tag;\n-\tu16 first_tag;\n-\tu16 second_tag;\n-\n \t/* debug mask */\n \tu32 debug_mask;\n \tchar err_str[16];\n@@ -962,9 +581,6 @@ struct i40e_tx_context_desc {\n \t__le64 type_cmd_tso_mss;\n };\n \n-#define I40E_TXD_CTX_QW1_DTYPE_SHIFT\t0\n-#define I40E_TXD_CTX_QW1_DTYPE_MASK\t(0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)\n-\n #define I40E_TXD_CTX_QW1_CMD_SHIFT\t4\n #define I40E_TXD_CTX_QW1_CMD_MASK\t(0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)\n \n@@ -1028,21 +644,6 @@ enum i40e_tx_ctx_desc_eipt_offload {\n \n #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT\t23\n #define I40E_TXD_CTX_QW0_L4T_CS_MASK\tBIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)\n-struct i40e_filter_program_desc {\n-\t__le32 qindex_flex_ptype_vsi;\n-\t__le32 rsvd;\n-\t__le32 dtype_cmd_cntindex;\n-\t__le32 fd_id;\n-};\n-#define I40E_TXD_FLTR_QW0_QINDEX_SHIFT\t0\n-#define I40E_TXD_FLTR_QW0_QINDEX_MASK\t(0x7FFUL << \\\n-\t\t\t\t\t I40E_TXD_FLTR_QW0_QINDEX_SHIFT)\n-#define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT\t11\n-#define I40E_TXD_FLTR_QW0_FLEXOFF_MASK\t(0x7UL << \\\n-\t\t\t\t\t I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)\n-#define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT\t17\n-#define I40E_TXD_FLTR_QW0_PCTYPE_MASK\t(0x3FUL << \\\n-\t\t\t\t\t I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)\n \n /* Packet Classifier Types for filters */\n enum i40e_filter_pctype {\n@@ -1076,58 +677,6 @@ enum i40e_filter_pctype {\n \tI40E_FILTER_PCTYPE_L2_PAYLOAD\t\t\t= 63,\n };\n \n-enum i40e_filter_program_desc_dest {\n-\tI40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET\t\t= 0x0,\n-\tI40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX\t= 0x1,\n-\tI40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER\t= 0x2,\n-};\n-\n-enum i40e_filter_program_desc_fd_status {\n-\tI40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE\t\t\t= 0x0,\n-\tI40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID\t\t= 0x1,\n-\tI40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES\t= 0x2,\n-\tI40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES\t\t= 0x3,\n-};\n-\n-#define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT\t23\n-#define I40E_TXD_FLTR_QW0_DEST_VSI_MASK\t(0x1FFUL << \\\n-\t\t\t\t\t I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)\n-\n-#define I40E_TXD_FLTR_QW1_CMD_SHIFT\t4\n-#define I40E_TXD_FLTR_QW1_CMD_MASK\t(0xFFFFULL << \\\n-\t\t\t\t\t I40E_TXD_FLTR_QW1_CMD_SHIFT)\n-\n-#define I40E_TXD_FLTR_QW1_PCMD_SHIFT\t(0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)\n-#define I40E_TXD_FLTR_QW1_PCMD_MASK\t(0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)\n-\n-enum i40e_filter_program_desc_pcmd {\n-\tI40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE\t= 0x1,\n-\tI40E_FILTER_PROGRAM_DESC_PCMD_REMOVE\t\t= 0x2,\n-};\n-\n-#define I40E_TXD_FLTR_QW1_DEST_SHIFT\t(0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)\n-#define I40E_TXD_FLTR_QW1_DEST_MASK\t(0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)\n-\n-#define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT\t(0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)\n-#define I40E_TXD_FLTR_QW1_CNT_ENA_MASK\tBIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)\n-\n-#define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT\t(0x9ULL + \\\n-\t\t\t\t\t\t I40E_TXD_FLTR_QW1_CMD_SHIFT)\n-#define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \\\n-\t\t\t\t\t I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)\n-\n-#define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20\n-#define I40E_TXD_FLTR_QW1_CNTINDEX_MASK\t(0x1FFUL << \\\n-\t\t\t\t\t I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)\n-\n-enum i40e_filter_type {\n-\tI40E_FLOW_DIRECTOR_FLTR = 0,\n-\tI40E_PE_QUAD_HASH_FLTR = 1,\n-\tI40E_ETHERTYPE_FLTR,\n-\tI40E_FCOE_CTX_FLTR,\n-\tI40E_MAC_VLAN_FLTR,\n-\tI40E_HASH_FLTR\n-};\n \n struct i40e_vsi_context {\n \tu16 seid;\n@@ -1167,330 +716,4 @@ struct i40e_eth_stats {\n \tu64 tx_discards;\t\t/* tdpc */\n \tu64 tx_errors;\t\t\t/* tepc */\n };\n-\n-/* Statistics collected per VEB per TC */\n-struct i40e_veb_tc_stats {\n-\tu64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];\n-\tu64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];\n-\tu64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];\n-\tu64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];\n-};\n-\n-/* Statistics collected by the MAC */\n-struct i40e_hw_port_stats {\n-\t/* eth stats collected by the port */\n-\tstruct i40e_eth_stats eth;\n-\n-\t/* additional port specific stats */\n-\tu64 tx_dropped_link_down;\t/* tdold */\n-\tu64 crc_errors;\t\t\t/* crcerrs */\n-\tu64 illegal_bytes;\t\t/* illerrc */\n-\tu64 error_bytes;\t\t/* errbc */\n-\tu64 mac_local_faults;\t\t/* mlfc */\n-\tu64 mac_remote_faults;\t\t/* mrfc */\n-\tu64 rx_length_errors;\t\t/* rlec */\n-\tu64 link_xon_rx;\t\t/* lxonrxc */\n-\tu64 link_xoff_rx;\t\t/* lxoffrxc */\n-\tu64 priority_xon_rx[8];\t\t/* pxonrxc[8] */\n-\tu64 priority_xoff_rx[8];\t/* pxoffrxc[8] */\n-\tu64 link_xon_tx;\t\t/* lxontxc */\n-\tu64 link_xoff_tx;\t\t/* lxofftxc */\n-\tu64 priority_xon_tx[8];\t\t/* pxontxc[8] */\n-\tu64 priority_xoff_tx[8];\t/* pxofftxc[8] */\n-\tu64 priority_xon_2_xoff[8];\t/* pxon2offc[8] */\n-\tu64 rx_size_64;\t\t\t/* prc64 */\n-\tu64 rx_size_127;\t\t/* prc127 */\n-\tu64 rx_size_255;\t\t/* prc255 */\n-\tu64 rx_size_511;\t\t/* prc511 */\n-\tu64 rx_size_1023;\t\t/* prc1023 */\n-\tu64 rx_size_1522;\t\t/* prc1522 */\n-\tu64 rx_size_big;\t\t/* prc9522 */\n-\tu64 rx_undersize;\t\t/* ruc */\n-\tu64 rx_fragments;\t\t/* rfc */\n-\tu64 rx_oversize;\t\t/* roc */\n-\tu64 rx_jabber;\t\t\t/* rjc */\n-\tu64 tx_size_64;\t\t\t/* ptc64 */\n-\tu64 tx_size_127;\t\t/* ptc127 */\n-\tu64 tx_size_255;\t\t/* ptc255 */\n-\tu64 tx_size_511;\t\t/* ptc511 */\n-\tu64 tx_size_1023;\t\t/* ptc1023 */\n-\tu64 tx_size_1522;\t\t/* ptc1522 */\n-\tu64 tx_size_big;\t\t/* ptc9522 */\n-\tu64 mac_short_packet_dropped;\t/* mspdc */\n-\tu64 checksum_error;\t\t/* xec */\n-\t/* flow director stats */\n-\tu64 fd_atr_match;\n-\tu64 fd_sb_match;\n-\tu64 fd_atr_tunnel_match;\n-\tu32 fd_atr_status;\n-\tu32 fd_sb_status;\n-\t/* EEE LPI */\n-\tu32 tx_lpi_status;\n-\tu32 rx_lpi_status;\n-\tu64 tx_lpi_count;\t\t/* etlpic */\n-\tu64 rx_lpi_count;\t\t/* erlpic */\n-};\n-\n-/* Checksum and Shadow RAM pointers */\n-#define I40E_SR_NVM_CONTROL_WORD\t\t0x00\n-#define I40E_EMP_MODULE_PTR\t\t\t0x0F\n-#define I40E_SR_EMP_MODULE_PTR\t\t\t0x48\n-#define I40E_NVM_OEM_VER_OFF\t\t\t0x83\n-#define I40E_SR_NVM_DEV_STARTER_VERSION\t\t0x18\n-#define I40E_SR_NVM_WAKE_ON_LAN\t\t\t0x19\n-#define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR\t0x27\n-#define I40E_SR_NVM_EETRACK_LO\t\t\t0x2D\n-#define I40E_SR_NVM_EETRACK_HI\t\t\t0x2E\n-#define I40E_SR_VPD_PTR\t\t\t\t0x2F\n-#define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR\t\t0x3E\n-#define I40E_SR_SW_CHECKSUM_WORD\t\t0x3F\n-\n-/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */\n-#define I40E_SR_VPD_MODULE_MAX_SIZE\t\t1024\n-#define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE\t1024\n-#define I40E_SR_CONTROL_WORD_1_SHIFT\t\t0x06\n-#define I40E_SR_CONTROL_WORD_1_MASK\t(0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)\n-#define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID\tBIT(5)\n-#define I40E_SR_NVM_MAP_STRUCTURE_TYPE\t\tBIT(12)\n-#define I40E_PTR_TYPE\t\t\t\tBIT(15)\n-\n-/* Shadow RAM related */\n-#define I40E_SR_SECTOR_SIZE_IN_WORDS\t0x800\n-#define I40E_SR_WORDS_IN_1KB\t\t512\n-/* Checksum should be calculated such that after adding all the words,\n- * including the checksum word itself, the sum should be 0xBABA.\n- */\n-#define I40E_SR_SW_CHECKSUM_BASE\t0xBABA\n-\n-#define I40E_SRRD_SRCTL_ATTEMPTS\t100000\n-\n-enum i40e_switch_element_types {\n-\tI40E_SWITCH_ELEMENT_TYPE_MAC\t= 1,\n-\tI40E_SWITCH_ELEMENT_TYPE_PF\t= 2,\n-\tI40E_SWITCH_ELEMENT_TYPE_VF\t= 3,\n-\tI40E_SWITCH_ELEMENT_TYPE_EMP\t= 4,\n-\tI40E_SWITCH_ELEMENT_TYPE_BMC\t= 6,\n-\tI40E_SWITCH_ELEMENT_TYPE_PE\t= 16,\n-\tI40E_SWITCH_ELEMENT_TYPE_VEB\t= 17,\n-\tI40E_SWITCH_ELEMENT_TYPE_PA\t= 18,\n-\tI40E_SWITCH_ELEMENT_TYPE_VSI\t= 19,\n-};\n-\n-/* Supported EtherType filters */\n-enum i40e_ether_type_index {\n-\tI40E_ETHER_TYPE_1588\t\t= 0,\n-\tI40E_ETHER_TYPE_FIP\t\t= 1,\n-\tI40E_ETHER_TYPE_OUI_EXTENDED\t= 2,\n-\tI40E_ETHER_TYPE_MAC_CONTROL\t= 3,\n-\tI40E_ETHER_TYPE_LLDP\t\t= 4,\n-\tI40E_ETHER_TYPE_EVB_PROTOCOL1\t= 5,\n-\tI40E_ETHER_TYPE_EVB_PROTOCOL2\t= 6,\n-\tI40E_ETHER_TYPE_QCN_CNM\t\t= 7,\n-\tI40E_ETHER_TYPE_8021X\t\t= 8,\n-\tI40E_ETHER_TYPE_ARP\t\t= 9,\n-\tI40E_ETHER_TYPE_RSV1\t\t= 10,\n-\tI40E_ETHER_TYPE_RSV2\t\t= 11,\n-};\n-\n-/* Filter context base size is 1K */\n-#define I40E_HASH_FILTER_BASE_SIZE\t1024\n-/* Supported Hash filter values */\n-enum i40e_hash_filter_size {\n-\tI40E_HASH_FILTER_SIZE_1K\t= 0,\n-\tI40E_HASH_FILTER_SIZE_2K\t= 1,\n-\tI40E_HASH_FILTER_SIZE_4K\t= 2,\n-\tI40E_HASH_FILTER_SIZE_8K\t= 3,\n-\tI40E_HASH_FILTER_SIZE_16K\t= 4,\n-\tI40E_HASH_FILTER_SIZE_32K\t= 5,\n-\tI40E_HASH_FILTER_SIZE_64K\t= 6,\n-\tI40E_HASH_FILTER_SIZE_128K\t= 7,\n-\tI40E_HASH_FILTER_SIZE_256K\t= 8,\n-\tI40E_HASH_FILTER_SIZE_512K\t= 9,\n-\tI40E_HASH_FILTER_SIZE_1M\t= 10,\n-};\n-\n-/* DMA context base size is 0.5K */\n-#define I40E_DMA_CNTX_BASE_SIZE\t\t512\n-/* Supported DMA context values */\n-enum i40e_dma_cntx_size {\n-\tI40E_DMA_CNTX_SIZE_512\t\t= 0,\n-\tI40E_DMA_CNTX_SIZE_1K\t\t= 1,\n-\tI40E_DMA_CNTX_SIZE_2K\t\t= 2,\n-\tI40E_DMA_CNTX_SIZE_4K\t\t= 3,\n-\tI40E_DMA_CNTX_SIZE_8K\t\t= 4,\n-\tI40E_DMA_CNTX_SIZE_16K\t\t= 5,\n-\tI40E_DMA_CNTX_SIZE_32K\t\t= 6,\n-\tI40E_DMA_CNTX_SIZE_64K\t\t= 7,\n-\tI40E_DMA_CNTX_SIZE_128K\t\t= 8,\n-\tI40E_DMA_CNTX_SIZE_256K\t\t= 9,\n-};\n-\n-/* Supported Hash look up table (LUT) sizes */\n-enum i40e_hash_lut_size {\n-\tI40E_HASH_LUT_SIZE_128\t\t= 0,\n-\tI40E_HASH_LUT_SIZE_512\t\t= 1,\n-};\n-\n-/* Structure to hold a per PF filter control settings */\n-struct i40e_filter_control_settings {\n-\t/* number of PE Quad Hash filter buckets */\n-\tenum i40e_hash_filter_size pe_filt_num;\n-\t/* number of PE Quad Hash contexts */\n-\tenum i40e_dma_cntx_size pe_cntx_num;\n-\t/* number of FCoE filter buckets */\n-\tenum i40e_hash_filter_size fcoe_filt_num;\n-\t/* number of FCoE DDP contexts */\n-\tenum i40e_dma_cntx_size fcoe_cntx_num;\n-\t/* size of the Hash LUT */\n-\tenum i40e_hash_lut_size\thash_lut_size;\n-\t/* enable FDIR filters for PF and its VFs */\n-\tbool enable_fdir;\n-\t/* enable Ethertype filters for PF and its VFs */\n-\tbool enable_ethtype;\n-\t/* enable MAC/VLAN filters for PF and its VFs */\n-\tbool enable_macvlan;\n-};\n-\n-/* Structure to hold device level control filter counts */\n-struct i40e_control_filter_stats {\n-\tu16 mac_etype_used; /* Used perfect match MAC/EtherType filters */\n-\tu16 etype_used; /* Used perfect EtherType filters */\n-\tu16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */\n-\tu16 etype_free; /* Un-used perfect EtherType filters */\n-};\n-\n-enum i40e_reset_type {\n-\tI40E_RESET_POR\t\t= 0,\n-\tI40E_RESET_CORER\t= 1,\n-\tI40E_RESET_GLOBR\t= 2,\n-\tI40E_RESET_EMPR\t\t= 3,\n-};\n-\n-/* IEEE 802.1AB LLDP Agent Variables from NVM */\n-#define I40E_NVM_LLDP_CFG_PTR\t0x06\n-#define I40E_SR_LLDP_CFG_PTR\t0x31\n-\n-/* RSS Hash Table Size */\n-#define I40E_PFQF_CTL_0_HASHLUTSIZE_512\t0x00010000\n-\n-/* INPUT SET MASK for RSS, flow director and flexible payload */\n-#define I40E_FD_INSET_L3_SRC_SHIFT\t\t47\n-#define I40E_FD_INSET_L3_SRC_WORD_MASK\t\t(0x3ULL << \\\n-\t\t\t\t\t\t I40E_FD_INSET_L3_SRC_SHIFT)\n-#define I40E_FD_INSET_L3_DST_SHIFT\t\t35\n-#define I40E_FD_INSET_L3_DST_WORD_MASK\t\t(0x3ULL << \\\n-\t\t\t\t\t\t I40E_FD_INSET_L3_DST_SHIFT)\n-#define I40E_FD_INSET_L4_SRC_SHIFT\t\t34\n-#define I40E_FD_INSET_L4_SRC_WORD_MASK\t\t(0x1ULL << \\\n-\t\t\t\t\t\t I40E_FD_INSET_L4_SRC_SHIFT)\n-#define I40E_FD_INSET_L4_DST_SHIFT\t\t33\n-#define I40E_FD_INSET_L4_DST_WORD_MASK\t\t(0x1ULL << \\\n-\t\t\t\t\t\t I40E_FD_INSET_L4_DST_SHIFT)\n-#define I40E_FD_INSET_VERIFY_TAG_SHIFT\t\t31\n-#define I40E_FD_INSET_VERIFY_TAG_WORD_MASK\t(0x3ULL << \\\n-\t\t\t\t\t\t I40E_FD_INSET_VERIFY_TAG_SHIFT)\n-\n-#define I40E_FD_INSET_FLEX_WORD50_SHIFT\t\t17\n-#define I40E_FD_INSET_FLEX_WORD50_MASK\t\t(0x1ULL << \\\n-\t\t\t\t\tI40E_FD_INSET_FLEX_WORD50_SHIFT)\n-#define I40E_FD_INSET_FLEX_WORD51_SHIFT\t\t16\n-#define I40E_FD_INSET_FLEX_WORD51_MASK\t\t(0x1ULL << \\\n-\t\t\t\t\tI40E_FD_INSET_FLEX_WORD51_SHIFT)\n-#define I40E_FD_INSET_FLEX_WORD52_SHIFT\t\t15\n-#define I40E_FD_INSET_FLEX_WORD52_MASK\t\t(0x1ULL << \\\n-\t\t\t\t\tI40E_FD_INSET_FLEX_WORD52_SHIFT)\n-#define I40E_FD_INSET_FLEX_WORD53_SHIFT\t\t14\n-#define I40E_FD_INSET_FLEX_WORD53_MASK\t\t(0x1ULL << \\\n-\t\t\t\t\tI40E_FD_INSET_FLEX_WORD53_SHIFT)\n-#define I40E_FD_INSET_FLEX_WORD54_SHIFT\t\t13\n-#define I40E_FD_INSET_FLEX_WORD54_MASK\t\t(0x1ULL << \\\n-\t\t\t\t\tI40E_FD_INSET_FLEX_WORD54_SHIFT)\n-#define I40E_FD_INSET_FLEX_WORD55_SHIFT\t\t12\n-#define I40E_FD_INSET_FLEX_WORD55_MASK\t\t(0x1ULL << \\\n-\t\t\t\t\tI40E_FD_INSET_FLEX_WORD55_SHIFT)\n-#define I40E_FD_INSET_FLEX_WORD56_SHIFT\t\t11\n-#define I40E_FD_INSET_FLEX_WORD56_MASK\t\t(0x1ULL << \\\n-\t\t\t\t\tI40E_FD_INSET_FLEX_WORD56_SHIFT)\n-#define I40E_FD_INSET_FLEX_WORD57_SHIFT\t\t10\n-#define I40E_FD_INSET_FLEX_WORD57_MASK\t\t(0x1ULL << \\\n-\t\t\t\t\tI40E_FD_INSET_FLEX_WORD57_SHIFT)\n-\n-/* Version format for Dynamic Device Personalization(DDP) */\n-struct i40e_ddp_version {\n-\tu8 major;\n-\tu8 minor;\n-\tu8 update;\n-\tu8 draft;\n-};\n-\n-#define I40E_DDP_NAME_SIZE\t32\n-\n-/* Package header */\n-struct i40e_package_header {\n-\tstruct i40e_ddp_version version;\n-\tu32 segment_count;\n-\tu32 segment_offset[1];\n-};\n-\n-/* Generic segment header */\n-struct i40e_generic_seg_header {\n-#define SEGMENT_TYPE_METADATA\t0x00000001\n-#define SEGMENT_TYPE_NOTES\t0x00000002\n-#define SEGMENT_TYPE_I40E\t0x00000011\n-#define SEGMENT_TYPE_X722\t0x00000012\n-\tu32 type;\n-\tstruct i40e_ddp_version version;\n-\tu32 size;\n-\tchar name[I40E_DDP_NAME_SIZE];\n-};\n-\n-struct i40e_metadata_segment {\n-\tstruct i40e_generic_seg_header header;\n-\tstruct i40e_ddp_version version;\n-\tu32 track_id;\n-\tchar name[I40E_DDP_NAME_SIZE];\n-};\n-\n-struct i40e_device_id_entry {\n-\tu32 vendor_dev_id;\n-\tu32 sub_vendor_dev_id;\n-};\n-\n-struct i40e_profile_segment {\n-\tstruct i40e_generic_seg_header header;\n-\tstruct i40e_ddp_version version;\n-\tchar name[I40E_DDP_NAME_SIZE];\n-\tu32 device_table_count;\n-\tstruct i40e_device_id_entry device_table[1];\n-};\n-\n-struct i40e_section_table {\n-\tu32 section_count;\n-\tu32 section_offset[1];\n-};\n-\n-struct i40e_profile_section_header {\n-\tu16 tbl_size;\n-\tu16 data_end;\n-\tstruct {\n-#define SECTION_TYPE_INFO\t0x00000010\n-#define SECTION_TYPE_MMIO\t0x00000800\n-#define SECTION_TYPE_AQ\t\t0x00000801\n-#define SECTION_TYPE_NOTE\t0x80000000\n-#define SECTION_TYPE_NAME\t0x80000001\n-\t\tu32 type;\n-\t\tu32 offset;\n-\t\tu32 size;\n-\t} section;\n-};\n-\n-struct i40e_profile_info {\n-\tu32 track_id;\n-\tstruct i40e_ddp_version version;\n-\tu8 op;\n-#define I40E_DDP_ADD_TRACKID\t\t0x01\n-#define I40E_DDP_REMOVE_TRACKID\t0x02\n-\tu8 reserved[7];\n-\tu8 name[I40E_DDP_NAME_SIZE];\n-};\n #endif /* _I40E_TYPE_H_ */\n", "prefixes": [ "net-next", "v2", "02/14" ] }