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GET /api/patches/970172/?format=api
{ "id": 970172, "url": "http://patchwork.ozlabs.org/api/patches/970172/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20180915003757.169108-7-jesse.brandeburg@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20180915003757.169108-7-jesse.brandeburg@intel.com>", "list_archive_url": null, "date": "2018-09-15T00:37:49", "name": "[net-next,v2,06/14] iavf: remove references to old names", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "220848c41899f2250245fb5b70ff680aab1dc76e", "submitter": { "id": 189, "url": "http://patchwork.ozlabs.org/api/people/189/?format=api", "name": "Jesse Brandeburg", "email": "jesse.brandeburg@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20180915003757.169108-7-jesse.brandeburg@intel.com/mbox/", "series": [ { "id": 65816, "url": "http://patchwork.ozlabs.org/api/series/65816/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=65816", "date": "2018-09-15T00:37:43", "name": "[net-next,v2,01/14] intel-ethernet: rename i40evf to iavf", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/65816/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/970172/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/970172/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.133; helo=hemlock.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 42Btlm6PXlz9sBn\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 15 Sep 2018 10:38:12 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 6E1B788DB0;\n\tSat, 15 Sep 2018 00:38:11 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 9ZxreLtiM22r; Sat, 15 Sep 2018 00:38:08 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 63C3D88DAD;\n\tSat, 15 Sep 2018 00:38:08 +0000 (UTC)", "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\tby ash.osuosl.org (Postfix) with ESMTP id E60C21C2E93\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tSat, 15 Sep 2018 00:38:06 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id D633488698\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tSat, 15 Sep 2018 00:38:06 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id t4J-cwCEK4SH for <intel-wired-lan@lists.osuosl.org>;\n\tSat, 15 Sep 2018 00:37:59 +0000 (UTC)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n\tby whitealder.osuosl.org (Postfix) with ESMTPS id 644BA8867A\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tSat, 15 Sep 2018 00:37:59 +0000 (UTC)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n\tby fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t14 Sep 2018 17:37:59 -0700", "from jfsjbrandeb002.jf.intel.com ([10.166.241.63])\n\tby fmsmga001.fm.intel.com with ESMTP; 14 Sep 2018 17:37:58 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.53,375,1531810800\"; d=\"scan'208\";a=\"90189559\"", "From": "Jesse Brandeburg <jesse.brandeburg@intel.com>", "To": "netdev@vger.kernel.org,\n\tintel-wired-lan@lists.osuosl.org", "Date": "Fri, 14 Sep 2018 17:37:49 -0700", "Message-Id": "<20180915003757.169108-7-jesse.brandeburg@intel.com>", "X-Mailer": "git-send-email 2.14.4", "In-Reply-To": "<20180915003757.169108-1-jesse.brandeburg@intel.com>", "References": "<20180915003757.169108-1-jesse.brandeburg@intel.com>", "Subject": "[Intel-wired-lan] [PATCH net-next v2 06/14] iavf: remove references\n\tto old names", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.24", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "Remove the register name references to I40E_VF* and change to\nIAVF_VF. Update the descriptor names and defines to the IAVF\nname.\n\nSigned-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>\n---\n drivers/net/ethernet/intel/iavf/i40e_adminq.c | 28 ++--\n drivers/net/ethernet/intel/iavf/i40e_common.c | 2 +-\n drivers/net/ethernet/intel/iavf/i40e_osdep.h | 2 +-\n drivers/net/ethernet/intel/iavf/i40e_register.h | 128 +++++++++---------\n drivers/net/ethernet/intel/iavf/i40e_type.h | 170 ++++++++++++------------\n drivers/net/ethernet/intel/iavf/iavf.h | 10 +-\n drivers/net/ethernet/intel/iavf/iavf_main.c | 92 ++++++-------\n drivers/net/ethernet/intel/iavf/iavf_txrx.c | 104 +++++++--------\n drivers/net/ethernet/intel/iavf/iavf_txrx.h | 2 +-\n 9 files changed, 267 insertions(+), 271 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/iavf/i40e_adminq.c b/drivers/net/ethernet/intel/iavf/i40e_adminq.c\nindex f0e6f9bbb819..50e0f1225298 100644\n--- a/drivers/net/ethernet/intel/iavf/i40e_adminq.c\n+++ b/drivers/net/ethernet/intel/iavf/i40e_adminq.c\n@@ -17,16 +17,16 @@ static void i40e_adminq_init_regs(struct i40e_hw *hw)\n {\n \t/* set head and tail registers in our local struct */\n \tif (i40e_is_vf(hw)) {\n-\t\thw->aq.asq.tail = I40E_VF_ATQT1;\n-\t\thw->aq.asq.head = I40E_VF_ATQH1;\n-\t\thw->aq.asq.len = I40E_VF_ATQLEN1;\n-\t\thw->aq.asq.bal = I40E_VF_ATQBAL1;\n-\t\thw->aq.asq.bah = I40E_VF_ATQBAH1;\n-\t\thw->aq.arq.tail = I40E_VF_ARQT1;\n-\t\thw->aq.arq.head = I40E_VF_ARQH1;\n-\t\thw->aq.arq.len = I40E_VF_ARQLEN1;\n-\t\thw->aq.arq.bal = I40E_VF_ARQBAL1;\n-\t\thw->aq.arq.bah = I40E_VF_ARQBAH1;\n+\t\thw->aq.asq.tail = IAVF_VF_ATQT1;\n+\t\thw->aq.asq.head = IAVF_VF_ATQH1;\n+\t\thw->aq.asq.len = IAVF_VF_ATQLEN1;\n+\t\thw->aq.asq.bal = IAVF_VF_ATQBAL1;\n+\t\thw->aq.asq.bah = IAVF_VF_ATQBAH1;\n+\t\thw->aq.arq.tail = IAVF_VF_ARQT1;\n+\t\thw->aq.arq.head = IAVF_VF_ARQH1;\n+\t\thw->aq.arq.len = IAVF_VF_ARQLEN1;\n+\t\thw->aq.arq.bal = IAVF_VF_ARQBAL1;\n+\t\thw->aq.arq.bah = IAVF_VF_ARQBAH1;\n \t}\n }\n \n@@ -264,7 +264,7 @@ static iavf_status i40e_config_asq_regs(struct i40e_hw *hw)\n \n \t/* set starting point */\n \twr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |\n-\t\t\t\t I40E_VF_ATQLEN1_ATQENABLE_MASK));\n+\t\t\t\t IAVF_VF_ATQLEN1_ATQENABLE_MASK));\n \twr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa));\n \twr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa));\n \n@@ -293,7 +293,7 @@ static iavf_status i40e_config_arq_regs(struct i40e_hw *hw)\n \n \t/* set starting point */\n \twr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |\n-\t\t\t\t I40E_VF_ARQLEN1_ARQENABLE_MASK));\n+\t\t\t\t IAVF_VF_ARQLEN1_ARQENABLE_MASK));\n \twr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa));\n \twr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa));\n \n@@ -800,7 +800,7 @@ iavf_status iavf_asq_send_command(struct i40e_hw *hw, struct i40e_aq_desc *desc,\n \t/* update the error if time out occurred */\n \tif ((!cmd_completed) &&\n \t (!details->async && !details->postpone)) {\n-\t\tif (rd32(hw, hw->aq.asq.len) & I40E_VF_ATQLEN1_ATQCRIT_MASK) {\n+\t\tif (rd32(hw, hw->aq.asq.len) & IAVF_VF_ATQLEN1_ATQCRIT_MASK) {\n \t\t\ti40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,\n \t\t\t\t \"AQTX: AQ Critical error.\\n\");\n \t\t\tstatus = I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR;\n@@ -868,7 +868,7 @@ iavf_status iavf_clean_arq_element(struct i40e_hw *hw,\n \t}\n \n \t/* set next_to_use to head */\n-\tntu = rd32(hw, hw->aq.arq.head) & I40E_VF_ARQH1_ARQH_MASK;\n+\tntu = rd32(hw, hw->aq.arq.head) & IAVF_VF_ARQH1_ARQH_MASK;\n \tif (ntu == ntc) {\n \t\t/* nothing to do - shouldn't need to update ring's values */\n \t\tret_code = I40E_ERR_ADMIN_QUEUE_NO_WORK;\ndiff --git a/drivers/net/ethernet/intel/iavf/i40e_common.c b/drivers/net/ethernet/intel/iavf/i40e_common.c\nindex 96133efddf72..733e5cfeaf71 100644\n--- a/drivers/net/ethernet/intel/iavf/i40e_common.c\n+++ b/drivers/net/ethernet/intel/iavf/i40e_common.c\n@@ -335,7 +335,7 @@ bool iavf_check_asq_alive(struct i40e_hw *hw)\n {\n \tif (hw->aq.asq.len)\n \t\treturn !!(rd32(hw, hw->aq.asq.len) &\n-\t\t\t I40E_VF_ATQLEN1_ATQENABLE_MASK);\n+\t\t\t IAVF_VF_ATQLEN1_ATQENABLE_MASK);\n \telse\n \t\treturn false;\n }\ndiff --git a/drivers/net/ethernet/intel/iavf/i40e_osdep.h b/drivers/net/ethernet/intel/iavf/i40e_osdep.h\nindex 788a599dc26b..0fceb284e54a 100644\n--- a/drivers/net/ethernet/intel/iavf/i40e_osdep.h\n+++ b/drivers/net/ethernet/intel/iavf/i40e_osdep.h\n@@ -24,7 +24,7 @@\n \n #define wr64(a, reg, value)\twriteq((value), ((a)->hw_addr + (reg)))\n #define rd64(a, reg)\t\treadq((a)->hw_addr + (reg))\n-#define i40e_flush(a)\t\treadl((a)->hw_addr + I40E_VFGEN_RSTAT)\n+#define iavf_flush(a)\t\treadl((a)->hw_addr + IAVF_VFGEN_RSTAT)\n \n /* memory allocation tracking */\n struct i40e_dma_mem {\ndiff --git a/drivers/net/ethernet/intel/iavf/i40e_register.h b/drivers/net/ethernet/intel/iavf/i40e_register.h\nindex 20b464ac1542..bf793332fc9d 100644\n--- a/drivers/net/ethernet/intel/iavf/i40e_register.h\n+++ b/drivers/net/ethernet/intel/iavf/i40e_register.h\n@@ -1,68 +1,68 @@\n /* SPDX-License-Identifier: GPL-2.0 */\n /* Copyright(c) 2013 - 2018 Intel Corporation. */\n \n-#ifndef _I40E_REGISTER_H_\n-#define _I40E_REGISTER_H_\n+#ifndef _IAVF_REGISTER_H_\n+#define _IAVF_REGISTER_H_\n \n-#define I40E_VF_ARQBAH1 0x00006000 /* Reset: EMPR */\n-#define I40E_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */\n-#define I40E_VF_ARQH1 0x00007400 /* Reset: EMPR */\n-#define I40E_VF_ARQH1_ARQH_SHIFT 0\n-#define I40E_VF_ARQH1_ARQH_MASK I40E_MASK(0x3FF, I40E_VF_ARQH1_ARQH_SHIFT)\n-#define I40E_VF_ARQLEN1 0x00008000 /* Reset: EMPR */\n-#define I40E_VF_ARQLEN1_ARQVFE_SHIFT 28\n-#define I40E_VF_ARQLEN1_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQVFE_SHIFT)\n-#define I40E_VF_ARQLEN1_ARQOVFL_SHIFT 29\n-#define I40E_VF_ARQLEN1_ARQOVFL_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQOVFL_SHIFT)\n-#define I40E_VF_ARQLEN1_ARQCRIT_SHIFT 30\n-#define I40E_VF_ARQLEN1_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQCRIT_SHIFT)\n-#define I40E_VF_ARQLEN1_ARQENABLE_SHIFT 31\n-#define I40E_VF_ARQLEN1_ARQENABLE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQENABLE_SHIFT)\n-#define I40E_VF_ARQT1 0x00007000 /* Reset: EMPR */\n-#define I40E_VF_ATQBAH1 0x00007800 /* Reset: EMPR */\n-#define I40E_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */\n-#define I40E_VF_ATQH1 0x00006400 /* Reset: EMPR */\n-#define I40E_VF_ATQLEN1 0x00006800 /* Reset: EMPR */\n-#define I40E_VF_ATQLEN1_ATQVFE_SHIFT 28\n-#define I40E_VF_ATQLEN1_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQVFE_SHIFT)\n-#define I40E_VF_ATQLEN1_ATQOVFL_SHIFT 29\n-#define I40E_VF_ATQLEN1_ATQOVFL_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQOVFL_SHIFT)\n-#define I40E_VF_ATQLEN1_ATQCRIT_SHIFT 30\n-#define I40E_VF_ATQLEN1_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQCRIT_SHIFT)\n-#define I40E_VF_ATQLEN1_ATQENABLE_SHIFT 31\n-#define I40E_VF_ATQLEN1_ATQENABLE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQENABLE_SHIFT)\n-#define I40E_VF_ATQT1 0x00008400 /* Reset: EMPR */\n-#define I40E_VFGEN_RSTAT 0x00008800 /* Reset: VFR */\n-#define I40E_VFGEN_RSTAT_VFR_STATE_SHIFT 0\n-#define I40E_VFGEN_RSTAT_VFR_STATE_MASK I40E_MASK(0x3, I40E_VFGEN_RSTAT_VFR_STATE_SHIFT)\n-#define I40E_VFINT_DYN_CTL01 0x00005C00 /* Reset: VFR */\n-#define I40E_VFINT_DYN_CTL01_INTENA_SHIFT 0\n-#define I40E_VFINT_DYN_CTL01_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_INTENA_SHIFT)\n-#define I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT 3\n-#define I40E_VFINT_DYN_CTL01_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT)\n-#define I40E_VFINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */\n-#define I40E_VFINT_DYN_CTLN1_INTENA_SHIFT 0\n-#define I40E_VFINT_DYN_CTLN1_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_INTENA_SHIFT)\n-#define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT 2\n-#define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT)\n-#define I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT 3\n-#define I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT)\n-#define I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT 5\n-#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT 24\n-#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT)\n-#define I40E_VFINT_ICR0_ENA1 0x00005000 /* Reset: CORER */\n-#define I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT 30\n-#define I40E_VFINT_ICR0_ENA1_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT)\n-#define I40E_VFINT_ICR0_ENA1_RSVD_SHIFT 31\n-#define I40E_VFINT_ICR01 0x00004800 /* Reset: CORER */\n-#define I40E_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */ /* Reset: VFR */\n-#define I40E_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: CORER */\n-#define I40E_QTX_TAIL1(_Q) (0x00000000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: PFR */\n-#define I40E_VFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */\n-#define I40E_VFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */\n-#define I40E_VFQF_HKEY_MAX_INDEX 12\n-#define I40E_VFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */\n-#define I40E_VFQF_HLUT_MAX_INDEX 15\n-#define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT 30\n-#define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT)\n-#endif /* _I40E_REGISTER_H_ */\n+#define IAVF_VF_ARQBAH1 0x00006000 /* Reset: EMPR */\n+#define IAVF_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */\n+#define IAVF_VF_ARQH1 0x00007400 /* Reset: EMPR */\n+#define IAVF_VF_ARQH1_ARQH_SHIFT 0\n+#define IAVF_VF_ARQH1_ARQH_MASK IAVF_MASK(0x3FF, IAVF_VF_ARQH1_ARQH_SHIFT)\n+#define IAVF_VF_ARQLEN1 0x00008000 /* Reset: EMPR */\n+#define IAVF_VF_ARQLEN1_ARQVFE_SHIFT 28\n+#define IAVF_VF_ARQLEN1_ARQVFE_MASK IAVF_MASK(0x1, IAVF_VF_ARQLEN1_ARQVFE_SHIFT)\n+#define IAVF_VF_ARQLEN1_ARQOVFL_SHIFT 29\n+#define IAVF_VF_ARQLEN1_ARQOVFL_MASK IAVF_MASK(0x1, IAVF_VF_ARQLEN1_ARQOVFL_SHIFT)\n+#define IAVF_VF_ARQLEN1_ARQCRIT_SHIFT 30\n+#define IAVF_VF_ARQLEN1_ARQCRIT_MASK IAVF_MASK(0x1, IAVF_VF_ARQLEN1_ARQCRIT_SHIFT)\n+#define IAVF_VF_ARQLEN1_ARQENABLE_SHIFT 31\n+#define IAVF_VF_ARQLEN1_ARQENABLE_MASK IAVF_MASK(0x1, IAVF_VF_ARQLEN1_ARQENABLE_SHIFT)\n+#define IAVF_VF_ARQT1 0x00007000 /* Reset: EMPR */\n+#define IAVF_VF_ATQBAH1 0x00007800 /* Reset: EMPR */\n+#define IAVF_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */\n+#define IAVF_VF_ATQH1 0x00006400 /* Reset: EMPR */\n+#define IAVF_VF_ATQLEN1 0x00006800 /* Reset: EMPR */\n+#define IAVF_VF_ATQLEN1_ATQVFE_SHIFT 28\n+#define IAVF_VF_ATQLEN1_ATQVFE_MASK IAVF_MASK(0x1, IAVF_VF_ATQLEN1_ATQVFE_SHIFT)\n+#define IAVF_VF_ATQLEN1_ATQOVFL_SHIFT 29\n+#define IAVF_VF_ATQLEN1_ATQOVFL_MASK IAVF_MASK(0x1, IAVF_VF_ATQLEN1_ATQOVFL_SHIFT)\n+#define IAVF_VF_ATQLEN1_ATQCRIT_SHIFT 30\n+#define IAVF_VF_ATQLEN1_ATQCRIT_MASK IAVF_MASK(0x1, IAVF_VF_ATQLEN1_ATQCRIT_SHIFT)\n+#define IAVF_VF_ATQLEN1_ATQENABLE_SHIFT 31\n+#define IAVF_VF_ATQLEN1_ATQENABLE_MASK IAVF_MASK(0x1, IAVF_VF_ATQLEN1_ATQENABLE_SHIFT)\n+#define IAVF_VF_ATQT1 0x00008400 /* Reset: EMPR */\n+#define IAVF_VFGEN_RSTAT 0x00008800 /* Reset: VFR */\n+#define IAVF_VFGEN_RSTAT_VFR_STATE_SHIFT 0\n+#define IAVF_VFGEN_RSTAT_VFR_STATE_MASK IAVF_MASK(0x3, IAVF_VFGEN_RSTAT_VFR_STATE_SHIFT)\n+#define IAVF_VFINT_DYN_CTL01 0x00005C00 /* Reset: VFR */\n+#define IAVF_VFINT_DYN_CTL01_INTENA_SHIFT 0\n+#define IAVF_VFINT_DYN_CTL01_INTENA_MASK IAVF_MASK(0x1, IAVF_VFINT_DYN_CTL01_INTENA_SHIFT)\n+#define IAVF_VFINT_DYN_CTL01_ITR_INDX_SHIFT 3\n+#define IAVF_VFINT_DYN_CTL01_ITR_INDX_MASK IAVF_MASK(0x3, IAVF_VFINT_DYN_CTL01_ITR_INDX_SHIFT)\n+#define IAVF_VFINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */\n+#define IAVF_VFINT_DYN_CTLN1_INTENA_SHIFT 0\n+#define IAVF_VFINT_DYN_CTLN1_INTENA_MASK IAVF_MASK(0x1, IAVF_VFINT_DYN_CTLN1_INTENA_SHIFT)\n+#define IAVF_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT 2\n+#define IAVF_VFINT_DYN_CTLN1_SWINT_TRIG_MASK IAVF_MASK(0x1, IAVF_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT)\n+#define IAVF_VFINT_DYN_CTLN1_ITR_INDX_SHIFT 3\n+#define IAVF_VFINT_DYN_CTLN1_ITR_INDX_MASK IAVF_MASK(0x3, IAVF_VFINT_DYN_CTLN1_ITR_INDX_SHIFT)\n+#define IAVF_VFINT_DYN_CTLN1_INTERVAL_SHIFT 5\n+#define IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT 24\n+#define IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK IAVF_MASK(0x1, IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT)\n+#define IAVF_VFINT_ICR0_ENA1 0x00005000 /* Reset: CORER */\n+#define IAVF_VFINT_ICR0_ENA1_ADMINQ_SHIFT 30\n+#define IAVF_VFINT_ICR0_ENA1_ADMINQ_MASK IAVF_MASK(0x1, IAVF_VFINT_ICR0_ENA1_ADMINQ_SHIFT)\n+#define IAVF_VFINT_ICR0_ENA1_RSVD_SHIFT 31\n+#define IAVF_VFINT_ICR01 0x00004800 /* Reset: CORER */\n+#define IAVF_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */ /* Reset: VFR */\n+#define IAVF_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: CORER */\n+#define IAVF_QTX_TAIL1(_Q) (0x00000000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: PFR */\n+#define IAVF_VFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */\n+#define IAVF_VFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */\n+#define IAVF_VFQF_HKEY_MAX_INDEX 12\n+#define IAVF_VFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */\n+#define IAVF_VFQF_HLUT_MAX_INDEX 15\n+#define IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT 30\n+#define IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK IAVF_MASK(0x1, IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT)\n+#endif /* _IAVF_REGISTER_H_ */\ndiff --git a/drivers/net/ethernet/intel/iavf/i40e_type.h b/drivers/net/ethernet/intel/iavf/i40e_type.h\nindex 8f1344094bc9..eea5b86a37b4 100644\n--- a/drivers/net/ethernet/intel/iavf/i40e_type.h\n+++ b/drivers/net/ethernet/intel/iavf/i40e_type.h\n@@ -13,7 +13,7 @@\n #define I40E_RXQ_CTX_DBUFF_SHIFT 7\n \n /* I40E_MASK is a macro used on 32 bit registers */\n-#define I40E_MASK(mask, shift) ((u32)(mask) << (shift))\n+#define IAVF_MASK(mask, shift) ((u32)(mask) << (shift))\n \n #define I40E_MAX_VSI_QP\t\t\t16\n #define I40E_MAX_VF_VSI\t\t\t3\n@@ -286,45 +286,45 @@ union i40e_32byte_rx_desc {\n \n enum i40e_rx_desc_status_bits {\n \t/* Note: These are predefined bit offsets */\n-\tI40E_RX_DESC_STATUS_DD_SHIFT\t\t= 0,\n-\tI40E_RX_DESC_STATUS_EOF_SHIFT\t\t= 1,\n-\tI40E_RX_DESC_STATUS_L2TAG1P_SHIFT\t= 2,\n-\tI40E_RX_DESC_STATUS_L3L4P_SHIFT\t\t= 3,\n-\tI40E_RX_DESC_STATUS_CRCP_SHIFT\t\t= 4,\n-\tI40E_RX_DESC_STATUS_TSYNINDX_SHIFT\t= 5, /* 2 BITS */\n-\tI40E_RX_DESC_STATUS_TSYNVALID_SHIFT\t= 7,\n+\tIAVF_RX_DESC_STATUS_DD_SHIFT\t\t= 0,\n+\tIAVF_RX_DESC_STATUS_EOF_SHIFT\t\t= 1,\n+\tIAVF_RX_DESC_STATUS_L2TAG1P_SHIFT\t= 2,\n+\tIAVF_RX_DESC_STATUS_L3L4P_SHIFT\t\t= 3,\n+\tIAVF_RX_DESC_STATUS_CRCP_SHIFT\t\t= 4,\n+\tIAVF_RX_DESC_STATUS_TSYNINDX_SHIFT\t= 5, /* 2 BITS */\n+\tIAVF_RX_DESC_STATUS_TSYNVALID_SHIFT\t= 7,\n \t/* Note: Bit 8 is reserved in X710 and XL710 */\n-\tI40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT\t= 8,\n-\tI40E_RX_DESC_STATUS_UMBCAST_SHIFT\t= 9, /* 2 BITS */\n-\tI40E_RX_DESC_STATUS_FLM_SHIFT\t\t= 11,\n-\tI40E_RX_DESC_STATUS_FLTSTAT_SHIFT\t= 12, /* 2 BITS */\n-\tI40E_RX_DESC_STATUS_LPBK_SHIFT\t\t= 14,\n-\tI40E_RX_DESC_STATUS_IPV6EXADD_SHIFT\t= 15,\n-\tI40E_RX_DESC_STATUS_RESERVED_SHIFT\t= 16, /* 2 BITS */\n+\tIAVF_RX_DESC_STATUS_EXT_UDP_0_SHIFT\t= 8,\n+\tIAVF_RX_DESC_STATUS_UMBCAST_SHIFT\t= 9, /* 2 BITS */\n+\tIAVF_RX_DESC_STATUS_FLM_SHIFT\t\t= 11,\n+\tIAVF_RX_DESC_STATUS_FLTSTAT_SHIFT\t= 12, /* 2 BITS */\n+\tIAVF_RX_DESC_STATUS_LPBK_SHIFT\t\t= 14,\n+\tIAVF_RX_DESC_STATUS_IPV6EXADD_SHIFT\t= 15,\n+\tIAVF_RX_DESC_STATUS_RESERVED_SHIFT\t= 16, /* 2 BITS */\n \t/* Note: For non-tunnel packets INT_UDP_0 is the right status for\n \t * UDP header\n \t */\n-\tI40E_RX_DESC_STATUS_INT_UDP_0_SHIFT\t= 18,\n-\tI40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */\n+\tIAVF_RX_DESC_STATUS_INT_UDP_0_SHIFT\t= 18,\n+\tIAVF_RX_DESC_STATUS_LAST /* this entry must be last!!! */\n };\n \n #define I40E_RXD_QW1_STATUS_SHIFT\t0\n-#define I40E_RXD_QW1_STATUS_MASK\t((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \\\n+#define I40E_RXD_QW1_STATUS_MASK\t((BIT(IAVF_RX_DESC_STATUS_LAST) - 1) \\\n \t\t\t\t\t << I40E_RXD_QW1_STATUS_SHIFT)\n \n-#define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT\n+#define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT IAVF_RX_DESC_STATUS_TSYNINDX_SHIFT\n #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK\t(0x3UL << \\\n \t\t\t\t\t I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)\n \n-#define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT\n+#define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT IAVF_RX_DESC_STATUS_TSYNVALID_SHIFT\n #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \\\n \t\t\t\t BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)\n \n enum i40e_rx_desc_fltstat_values {\n-\tI40E_RX_DESC_FLTSTAT_NO_DATA\t= 0,\n-\tI40E_RX_DESC_FLTSTAT_RSV_FD_ID\t= 1, /* 16byte desc? FD_ID : RSV */\n-\tI40E_RX_DESC_FLTSTAT_RSV\t= 2,\n-\tI40E_RX_DESC_FLTSTAT_RSS_HASH\t= 3,\n+\tIAVF_RX_DESC_FLTSTAT_NO_DATA\t= 0,\n+\tIAVF_RX_DESC_FLTSTAT_RSV_FD_ID\t= 1, /* 16byte desc? FD_ID : RSV */\n+\tIAVF_RX_DESC_FLTSTAT_RSV\t= 2,\n+\tIAVF_RX_DESC_FLTSTAT_RSS_HASH\t= 3,\n };\n \n #define I40E_RXD_QW1_ERROR_SHIFT\t19\n@@ -332,23 +332,23 @@ enum i40e_rx_desc_fltstat_values {\n \n enum i40e_rx_desc_error_bits {\n \t/* Note: These are predefined bit offsets */\n-\tI40E_RX_DESC_ERROR_RXE_SHIFT\t\t= 0,\n-\tI40E_RX_DESC_ERROR_RECIPE_SHIFT\t\t= 1,\n-\tI40E_RX_DESC_ERROR_HBO_SHIFT\t\t= 2,\n-\tI40E_RX_DESC_ERROR_L3L4E_SHIFT\t\t= 3, /* 3 BITS */\n-\tI40E_RX_DESC_ERROR_IPE_SHIFT\t\t= 3,\n-\tI40E_RX_DESC_ERROR_L4E_SHIFT\t\t= 4,\n-\tI40E_RX_DESC_ERROR_EIPE_SHIFT\t\t= 5,\n-\tI40E_RX_DESC_ERROR_OVERSIZE_SHIFT\t= 6,\n-\tI40E_RX_DESC_ERROR_PPRS_SHIFT\t\t= 7\n+\tIAVF_RX_DESC_ERROR_RXE_SHIFT\t\t= 0,\n+\tIAVF_RX_DESC_ERROR_RECIPE_SHIFT\t\t= 1,\n+\tIAVF_RX_DESC_ERROR_HBO_SHIFT\t\t= 2,\n+\tIAVF_RX_DESC_ERROR_L3L4E_SHIFT\t\t= 3, /* 3 BITS */\n+\tIAVF_RX_DESC_ERROR_IPE_SHIFT\t\t= 3,\n+\tIAVF_RX_DESC_ERROR_L4E_SHIFT\t\t= 4,\n+\tIAVF_RX_DESC_ERROR_EIPE_SHIFT\t\t= 5,\n+\tIAVF_RX_DESC_ERROR_OVERSIZE_SHIFT\t= 6,\n+\tIAVF_RX_DESC_ERROR_PPRS_SHIFT\t\t= 7\n };\n \n enum i40e_rx_desc_error_l3l4e_fcoe_masks {\n-\tI40E_RX_DESC_ERROR_L3L4E_NONE\t\t= 0,\n-\tI40E_RX_DESC_ERROR_L3L4E_PROT\t\t= 1,\n-\tI40E_RX_DESC_ERROR_L3L4E_FC\t\t= 2,\n-\tI40E_RX_DESC_ERROR_L3L4E_DMAC_ERR\t= 3,\n-\tI40E_RX_DESC_ERROR_L3L4E_DMAC_WARN\t= 4\n+\tIAVF_RX_DESC_ERROR_L3L4E_NONE\t\t= 0,\n+\tIAVF_RX_DESC_ERROR_L3L4E_PROT\t\t= 1,\n+\tIAVF_RX_DESC_ERROR_L3L4E_FC\t\t= 2,\n+\tIAVF_RX_DESC_ERROR_L3L4E_DMAC_ERR\t= 3,\n+\tIAVF_RX_DESC_ERROR_L3L4E_DMAC_WARN\t= 4\n };\n \n #define I40E_RXD_QW1_PTYPE_SHIFT\t30\n@@ -456,26 +456,26 @@ enum i40e_rx_ptype_payload_layer {\n \n enum i40e_rx_desc_ext_status_bits {\n \t/* Note: These are predefined bit offsets */\n-\tI40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT\t= 0,\n-\tI40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT\t= 1,\n-\tI40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT\t= 2, /* 2 BITS */\n-\tI40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT\t= 4, /* 2 BITS */\n-\tI40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT\t= 9,\n-\tI40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT\t= 10,\n-\tI40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT\t= 11,\n+\tIAVF_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT\t= 0,\n+\tIAVF_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT\t= 1,\n+\tIAVF_RX_DESC_EXT_STATUS_FLEXBL_SHIFT\t= 2, /* 2 BITS */\n+\tIAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT\t= 4, /* 2 BITS */\n+\tIAVF_RX_DESC_EXT_STATUS_FDLONGB_SHIFT\t= 9,\n+\tIAVF_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT\t= 10,\n+\tIAVF_RX_DESC_EXT_STATUS_PELONGB_SHIFT\t= 11,\n };\n \n enum i40e_rx_desc_pe_status_bits {\n \t/* Note: These are predefined bit offsets */\n-\tI40E_RX_DESC_PE_STATUS_QPID_SHIFT\t= 0, /* 18 BITS */\n-\tI40E_RX_DESC_PE_STATUS_L4PORT_SHIFT\t= 0, /* 16 BITS */\n-\tI40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT\t= 16, /* 8 BITS */\n-\tI40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT\t= 24,\n-\tI40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT\t= 25,\n-\tI40E_RX_DESC_PE_STATUS_PORTV_SHIFT\t= 26,\n-\tI40E_RX_DESC_PE_STATUS_URG_SHIFT\t= 27,\n-\tI40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT\t= 28,\n-\tI40E_RX_DESC_PE_STATUS_IPOPT_SHIFT\t= 29\n+\tIAVF_RX_DESC_PE_STATUS_QPID_SHIFT\t= 0, /* 18 BITS */\n+\tIAVF_RX_DESC_PE_STATUS_L4PORT_SHIFT\t= 0, /* 16 BITS */\n+\tIAVF_RX_DESC_PE_STATUS_IPINDEX_SHIFT\t= 16, /* 8 BITS */\n+\tIAVF_RX_DESC_PE_STATUS_QPIDHIT_SHIFT\t= 24,\n+\tIAVF_RX_DESC_PE_STATUS_APBVTHIT_SHIFT\t= 25,\n+\tIAVF_RX_DESC_PE_STATUS_PORTV_SHIFT\t= 26,\n+\tIAVF_RX_DESC_PE_STATUS_URG_SHIFT\t= 27,\n+\tIAVF_RX_DESC_PE_STATUS_IPFRAG_SHIFT\t= 28,\n+\tIAVF_RX_DESC_PE_STATUS_IPOPT_SHIFT\t= 29\n };\n \n #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT\t\t38\n@@ -519,40 +519,40 @@ struct i40e_tx_desc {\n #define I40E_TXD_QW1_DTYPE_MASK\t\t(0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)\n \n enum i40e_tx_desc_dtype_value {\n-\tI40E_TX_DESC_DTYPE_DATA\t\t= 0x0,\n-\tI40E_TX_DESC_DTYPE_NOP\t\t= 0x1, /* same as Context desc */\n-\tI40E_TX_DESC_DTYPE_CONTEXT\t= 0x1,\n-\tI40E_TX_DESC_DTYPE_FCOE_CTX\t= 0x2,\n-\tI40E_TX_DESC_DTYPE_FILTER_PROG\t= 0x8,\n-\tI40E_TX_DESC_DTYPE_DDP_CTX\t= 0x9,\n-\tI40E_TX_DESC_DTYPE_FLEX_DATA\t= 0xB,\n-\tI40E_TX_DESC_DTYPE_FLEX_CTX_1\t= 0xC,\n-\tI40E_TX_DESC_DTYPE_FLEX_CTX_2\t= 0xD,\n-\tI40E_TX_DESC_DTYPE_DESC_DONE\t= 0xF\n+\tIAVF_TX_DESC_DTYPE_DATA\t\t= 0x0,\n+\tIAVF_TX_DESC_DTYPE_NOP\t\t= 0x1, /* same as Context desc */\n+\tIAVF_TX_DESC_DTYPE_CONTEXT\t= 0x1,\n+\tIAVF_TX_DESC_DTYPE_FCOE_CTX\t= 0x2,\n+\tIAVF_TX_DESC_DTYPE_FILTER_PROG\t= 0x8,\n+\tIAVF_TX_DESC_DTYPE_DDP_CTX\t= 0x9,\n+\tIAVF_TX_DESC_DTYPE_FLEX_DATA\t= 0xB,\n+\tIAVF_TX_DESC_DTYPE_FLEX_CTX_1\t= 0xC,\n+\tIAVF_TX_DESC_DTYPE_FLEX_CTX_2\t= 0xD,\n+\tIAVF_TX_DESC_DTYPE_DESC_DONE\t= 0xF\n };\n \n #define I40E_TXD_QW1_CMD_SHIFT\t4\n #define I40E_TXD_QW1_CMD_MASK\t(0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)\n \n enum i40e_tx_desc_cmd_bits {\n-\tI40E_TX_DESC_CMD_EOP\t\t\t= 0x0001,\n-\tI40E_TX_DESC_CMD_RS\t\t\t= 0x0002,\n-\tI40E_TX_DESC_CMD_ICRC\t\t\t= 0x0004,\n-\tI40E_TX_DESC_CMD_IL2TAG1\t\t= 0x0008,\n-\tI40E_TX_DESC_CMD_DUMMY\t\t\t= 0x0010,\n-\tI40E_TX_DESC_CMD_IIPT_NONIP\t\t= 0x0000, /* 2 BITS */\n-\tI40E_TX_DESC_CMD_IIPT_IPV6\t\t= 0x0020, /* 2 BITS */\n-\tI40E_TX_DESC_CMD_IIPT_IPV4\t\t= 0x0040, /* 2 BITS */\n-\tI40E_TX_DESC_CMD_IIPT_IPV4_CSUM\t\t= 0x0060, /* 2 BITS */\n-\tI40E_TX_DESC_CMD_FCOET\t\t\t= 0x0080,\n-\tI40E_TX_DESC_CMD_L4T_EOFT_UNK\t\t= 0x0000, /* 2 BITS */\n-\tI40E_TX_DESC_CMD_L4T_EOFT_TCP\t\t= 0x0100, /* 2 BITS */\n-\tI40E_TX_DESC_CMD_L4T_EOFT_SCTP\t\t= 0x0200, /* 2 BITS */\n-\tI40E_TX_DESC_CMD_L4T_EOFT_UDP\t\t= 0x0300, /* 2 BITS */\n-\tI40E_TX_DESC_CMD_L4T_EOFT_EOF_N\t\t= 0x0000, /* 2 BITS */\n-\tI40E_TX_DESC_CMD_L4T_EOFT_EOF_T\t\t= 0x0100, /* 2 BITS */\n-\tI40E_TX_DESC_CMD_L4T_EOFT_EOF_NI\t= 0x0200, /* 2 BITS */\n-\tI40E_TX_DESC_CMD_L4T_EOFT_EOF_A\t\t= 0x0300, /* 2 BITS */\n+\tIAVF_TX_DESC_CMD_EOP\t\t\t= 0x0001,\n+\tIAVF_TX_DESC_CMD_RS\t\t\t= 0x0002,\n+\tIAVF_TX_DESC_CMD_ICRC\t\t\t= 0x0004,\n+\tIAVF_TX_DESC_CMD_IL2TAG1\t\t= 0x0008,\n+\tIAVF_TX_DESC_CMD_DUMMY\t\t\t= 0x0010,\n+\tIAVF_TX_DESC_CMD_IIPT_NONIP\t\t= 0x0000, /* 2 BITS */\n+\tIAVF_TX_DESC_CMD_IIPT_IPV6\t\t= 0x0020, /* 2 BITS */\n+\tIAVF_TX_DESC_CMD_IIPT_IPV4\t\t= 0x0040, /* 2 BITS */\n+\tIAVF_TX_DESC_CMD_IIPT_IPV4_CSUM\t\t= 0x0060, /* 2 BITS */\n+\tIAVF_TX_DESC_CMD_FCOET\t\t\t= 0x0080,\n+\tIAVF_TX_DESC_CMD_L4T_EOFT_UNK\t\t= 0x0000, /* 2 BITS */\n+\tIAVF_TX_DESC_CMD_L4T_EOFT_TCP\t\t= 0x0100, /* 2 BITS */\n+\tIAVF_TX_DESC_CMD_L4T_EOFT_SCTP\t\t= 0x0200, /* 2 BITS */\n+\tIAVF_TX_DESC_CMD_L4T_EOFT_UDP\t\t= 0x0300, /* 2 BITS */\n+\tIAVF_TX_DESC_CMD_L4T_EOFT_EOF_N\t\t= 0x0000, /* 2 BITS */\n+\tIAVF_TX_DESC_CMD_L4T_EOFT_EOF_T\t\t= 0x0100, /* 2 BITS */\n+\tIAVF_TX_DESC_CMD_L4T_EOFT_EOF_NI\t= 0x0200, /* 2 BITS */\n+\tIAVF_TX_DESC_CMD_L4T_EOFT_EOF_A\t\t= 0x0300, /* 2 BITS */\n };\n \n #define I40E_TXD_QW1_OFFSET_SHIFT\t16\n@@ -561,9 +561,9 @@ enum i40e_tx_desc_cmd_bits {\n \n enum i40e_tx_desc_length_fields {\n \t/* Note: These are predefined bit offsets */\n-\tI40E_TX_DESC_LENGTH_MACLEN_SHIFT\t= 0, /* 7 BITS */\n-\tI40E_TX_DESC_LENGTH_IPLEN_SHIFT\t\t= 7, /* 7 BITS */\n-\tI40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT\t= 14 /* 4 BITS */\n+\tIAVF_TX_DESC_LENGTH_MACLEN_SHIFT\t= 0, /* 7 BITS */\n+\tIAVF_TX_DESC_LENGTH_IPLEN_SHIFT\t\t= 7, /* 7 BITS */\n+\tIAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT\t= 14 /* 4 BITS */\n };\n \n #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT\t34\ndiff --git a/drivers/net/ethernet/intel/iavf/iavf.h b/drivers/net/ethernet/intel/iavf/iavf.h\nindex c7ce2db958b0..48ff5e924cfe 100644\n--- a/drivers/net/ethernet/intel/iavf/iavf.h\n+++ b/drivers/net/ethernet/intel/iavf/iavf.h\n@@ -77,14 +77,14 @@ struct i40e_vsi {\n \n #define MAXIMUM_ETHERNET_VLAN_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)\n \n-#define I40E_RX_DESC(R, i) (&(((union i40e_32byte_rx_desc *)((R)->desc))[i]))\n-#define I40E_TX_DESC(R, i) (&(((struct i40e_tx_desc *)((R)->desc))[i]))\n-#define I40E_TX_CTXTDESC(R, i) \\\n+#define IAVF_RX_DESC(R, i) (&(((union i40e_32byte_rx_desc *)((R)->desc))[i]))\n+#define IAVF_TX_DESC(R, i) (&(((struct i40e_tx_desc *)((R)->desc))[i]))\n+#define IAVF_TX_CTXTDESC(R, i) \\\n \t(&(((struct i40e_tx_context_desc *)((R)->desc))[i]))\n #define IAVF_MAX_REQ_QUEUES 4\n \n-#define IAVF_HKEY_ARRAY_SIZE ((I40E_VFQF_HKEY_MAX_INDEX + 1) * 4)\n-#define IAVF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT_MAX_INDEX + 1) * 4)\n+#define IAVF_HKEY_ARRAY_SIZE ((IAVF_VFQF_HKEY_MAX_INDEX + 1) * 4)\n+#define IAVF_HLUT_ARRAY_SIZE ((IAVF_VFQF_HLUT_MAX_INDEX + 1) * 4)\n #define IAVF_MBPS_DIVISOR\t125000 /* divisor to convert to Mbps */\n \n /* MAX_MSIX_Q_VECTORS of these are allocated,\ndiff --git a/drivers/net/ethernet/intel/iavf/iavf_main.c b/drivers/net/ethernet/intel/iavf/iavf_main.c\nindex 7d815ace2d98..01fd440b4bbe 100644\n--- a/drivers/net/ethernet/intel/iavf/iavf_main.c\n+++ b/drivers/net/ethernet/intel/iavf/iavf_main.c\n@@ -196,10 +196,9 @@ static void iavf_misc_irq_disable(struct iavf_adapter *adapter)\n \tif (!adapter->msix_entries)\n \t\treturn;\n \n-\twr32(hw, I40E_VFINT_DYN_CTL01, 0);\n+\twr32(hw, IAVF_VFINT_DYN_CTL01, 0);\n \n-\t/* read flush */\n-\trd32(hw, I40E_VFGEN_RSTAT);\n+\tiavf_flush(hw);\n \n \tsynchronize_irq(adapter->msix_entries[0].vector);\n }\n@@ -212,12 +211,11 @@ static void iavf_misc_irq_enable(struct iavf_adapter *adapter)\n {\n \tstruct i40e_hw *hw = &adapter->hw;\n \n-\twr32(hw, I40E_VFINT_DYN_CTL01, I40E_VFINT_DYN_CTL01_INTENA_MASK |\n-\t\t\t\t I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);\n-\twr32(hw, I40E_VFINT_ICR0_ENA1, I40E_VFINT_ICR0_ENA1_ADMINQ_MASK);\n+\twr32(hw, IAVF_VFINT_DYN_CTL01, IAVF_VFINT_DYN_CTL01_INTENA_MASK |\n+\t\t\t\t IAVF_VFINT_DYN_CTL01_ITR_INDX_MASK);\n+\twr32(hw, IAVF_VFINT_ICR0_ENA1, IAVF_VFINT_ICR0_ENA1_ADMINQ_MASK);\n \n-\t/* read flush */\n-\trd32(hw, I40E_VFGEN_RSTAT);\n+\tiavf_flush(hw);\n }\n \n /**\n@@ -233,11 +231,10 @@ static void iavf_irq_disable(struct iavf_adapter *adapter)\n \t\treturn;\n \n \tfor (i = 1; i < adapter->num_msix_vectors; i++) {\n-\t\twr32(hw, I40E_VFINT_DYN_CTLN1(i - 1), 0);\n+\t\twr32(hw, IAVF_VFINT_DYN_CTLN1(i - 1), 0);\n \t\tsynchronize_irq(adapter->msix_entries[i].vector);\n \t}\n-\t/* read flush */\n-\trd32(hw, I40E_VFGEN_RSTAT);\n+\tiavf_flush(hw);\n }\n \n /**\n@@ -252,9 +249,9 @@ void iavf_irq_enable_queues(struct iavf_adapter *adapter, u32 mask)\n \n \tfor (i = 1; i < adapter->num_msix_vectors; i++) {\n \t\tif (mask & BIT(i - 1)) {\n-\t\t\twr32(hw, I40E_VFINT_DYN_CTLN1(i - 1),\n-\t\t\t I40E_VFINT_DYN_CTLN1_INTENA_MASK |\n-\t\t\t I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK);\n+\t\t\twr32(hw, IAVF_VFINT_DYN_CTLN1(i - 1),\n+\t\t\t IAVF_VFINT_DYN_CTLN1_INTENA_MASK |\n+\t\t\t IAVF_VFINT_DYN_CTLN1_ITR_INDX_MASK);\n \t\t}\n \t}\n }\n@@ -272,7 +269,7 @@ void iavf_irq_enable(struct iavf_adapter *adapter, bool flush)\n \tiavf_irq_enable_queues(adapter, ~0);\n \n \tif (flush)\n-\t\trd32(hw, I40E_VFGEN_RSTAT);\n+\t\tiavf_flush(hw);\n }\n \n /**\n@@ -287,8 +284,8 @@ static irqreturn_t iavf_msix_aq(int irq, void *data)\n \tstruct i40e_hw *hw = &adapter->hw;\n \n \t/* handle non-queue interrupts, these reads clear the registers */\n-\trd32(hw, I40E_VFINT_ICR01);\n-\trd32(hw, I40E_VFINT_ICR0_ENA1);\n+\trd32(hw, IAVF_VFINT_ICR01);\n+\trd32(hw, IAVF_VFINT_ICR0_ENA1);\n \n \t/* schedule work on the private workqueue */\n \tschedule_work(&adapter->adminq_task);\n@@ -334,7 +331,7 @@ iavf_map_vector_to_rxq(struct iavf_adapter *adapter, int v_idx, int r_idx)\n \tq_vector->rx.next_update = jiffies + 1;\n \tq_vector->rx.target_itr = ITR_TO_REG(rx_ring->itr_setting);\n \tq_vector->ring_mask |= BIT(r_idx);\n-\twr32(hw, I40E_VFINT_ITRN1(I40E_RX_ITR, q_vector->reg_idx),\n+\twr32(hw, IAVF_VFINT_ITRN1(I40E_RX_ITR, q_vector->reg_idx),\n \t q_vector->rx.current_itr);\n \tq_vector->rx.current_itr = q_vector->rx.target_itr;\n }\n@@ -360,7 +357,7 @@ iavf_map_vector_to_txq(struct iavf_adapter *adapter, int v_idx, int t_idx)\n \tq_vector->tx.next_update = jiffies + 1;\n \tq_vector->tx.target_itr = ITR_TO_REG(tx_ring->itr_setting);\n \tq_vector->num_ringpairs++;\n-\twr32(hw, I40E_VFINT_ITRN1(I40E_TX_ITR, q_vector->reg_idx),\n+\twr32(hw, IAVF_VFINT_ITRN1(I40E_TX_ITR, q_vector->reg_idx),\n \t q_vector->tx.target_itr);\n \tq_vector->tx.current_itr = q_vector->tx.target_itr;\n }\n@@ -601,7 +598,7 @@ static void iavf_configure_tx(struct iavf_adapter *adapter)\n \tint i;\n \n \tfor (i = 0; i < adapter->num_active_queues; i++)\n-\t\tadapter->tx_rings[i].tail = hw->hw_addr + I40E_QTX_TAIL1(i);\n+\t\tadapter->tx_rings[i].tail = hw->hw_addr + IAVF_QTX_TAIL1(i);\n }\n \n /**\n@@ -638,7 +635,7 @@ static void iavf_configure_rx(struct iavf_adapter *adapter)\n #endif\n \n \tfor (i = 0; i < adapter->num_active_queues; i++) {\n-\t\tadapter->rx_rings[i].tail = hw->hw_addr + I40E_QRX_TAIL1(i);\n+\t\tadapter->rx_rings[i].tail = hw->hw_addr + IAVF_QRX_TAIL1(i);\n \t\tadapter->rx_rings[i].rx_buf_len = rx_buf_len;\n \n \t\tif (adapter->flags & IAVF_FLAG_LEGACY_RX)\n@@ -1301,13 +1298,13 @@ static int iavf_config_rss_reg(struct iavf_adapter *adapter)\n \n \tdw = (u32 *)adapter->rss_key;\n \tfor (i = 0; i <= adapter->rss_key_size / 4; i++)\n-\t\twr32(hw, I40E_VFQF_HKEY(i), dw[i]);\n+\t\twr32(hw, IAVF_VFQF_HKEY(i), dw[i]);\n \n \tdw = (u32 *)adapter->rss_lut;\n \tfor (i = 0; i <= adapter->rss_lut_size / 4; i++)\n-\t\twr32(hw, I40E_VFQF_HLUT(i), dw[i]);\n+\t\twr32(hw, IAVF_VFQF_HLUT(i), dw[i]);\n \n-\ti40e_flush(hw);\n+\tiavf_flush(hw);\n \n \treturn 0;\n }\n@@ -1363,12 +1360,11 @@ static int iavf_init_rss(struct iavf_adapter *adapter)\n \t\telse\n \t\t\tadapter->hena = I40E_DEFAULT_RSS_HENA;\n \n-\t\twr32(hw, I40E_VFQF_HENA(0), (u32)adapter->hena);\n-\t\twr32(hw, I40E_VFQF_HENA(1), (u32)(adapter->hena >> 32));\n+\t\twr32(hw, IAVF_VFQF_HENA(0), (u32)adapter->hena);\n+\t\twr32(hw, IAVF_VFQF_HENA(1), (u32)(adapter->hena >> 32));\n \t}\n \n \tiavf_fill_rss_lut(adapter);\n-\n \tnetdev_rss_key_fill((void *)adapter->rss_key, adapter->rss_key_size);\n \tret = iavf_config_rss(adapter);\n \n@@ -1588,8 +1584,8 @@ static void iavf_watchdog_task(struct work_struct *work)\n \t\tgoto restart_watchdog;\n \n \tif (adapter->flags & IAVF_FLAG_PF_COMMS_FAILED) {\n-\t\treg_val = rd32(hw, I40E_VFGEN_RSTAT) &\n-\t\t\t I40E_VFGEN_RSTAT_VFR_STATE_MASK;\n+\t\treg_val = rd32(hw, IAVF_VFGEN_RSTAT) &\n+\t\t\t IAVF_VFGEN_RSTAT_VFR_STATE_MASK;\n \t\tif ((reg_val == VIRTCHNL_VFR_VFACTIVE) ||\n \t\t (reg_val == VIRTCHNL_VFR_COMPLETED)) {\n \t\t\t/* A chance for redemption! */\n@@ -1616,7 +1612,7 @@ static void iavf_watchdog_task(struct work_struct *work)\n \t\tgoto watchdog_done;\n \n \t/* check for reset */\n-\treg_val = rd32(hw, I40E_VF_ARQLEN1) & I40E_VF_ARQLEN1_ARQENABLE_MASK;\n+\treg_val = rd32(hw, IAVF_VF_ARQLEN1) & IAVF_VF_ARQLEN1_ARQENABLE_MASK;\n \tif (!(adapter->flags & IAVF_FLAG_RESET_PENDING) && !reg_val) {\n \t\tadapter->state = __IAVF_RESETTING;\n \t\tadapter->flags |= IAVF_FLAG_RESET_PENDING;\n@@ -1891,8 +1887,8 @@ static void iavf_reset_task(struct work_struct *work)\n \n \t/* poll until we see the reset actually happen */\n \tfor (i = 0; i < IAVF_RESET_WAIT_COUNT; i++) {\n-\t\treg_val = rd32(hw, I40E_VF_ARQLEN1) &\n-\t\t\t I40E_VF_ARQLEN1_ARQENABLE_MASK;\n+\t\treg_val = rd32(hw, IAVF_VF_ARQLEN1) &\n+\t\t\t IAVF_VF_ARQLEN1_ARQENABLE_MASK;\n \t\tif (!reg_val)\n \t\t\tbreak;\n \t\tusleep_range(5000, 10000);\n@@ -1907,8 +1903,8 @@ static void iavf_reset_task(struct work_struct *work)\n \t\t/* sleep first to make sure a minimum wait time is met */\n \t\tmsleep(IAVF_RESET_WAIT_MS);\n \n-\t\treg_val = rd32(hw, I40E_VFGEN_RSTAT) &\n-\t\t\t I40E_VFGEN_RSTAT_VFR_STATE_MASK;\n+\t\treg_val = rd32(hw, IAVF_VFGEN_RSTAT) &\n+\t\t\t IAVF_VFGEN_RSTAT_VFR_STATE_MASK;\n \t\tif (reg_val == VIRTCHNL_VFR_VFACTIVE)\n \t\t\tbreak;\n \t}\n@@ -2087,34 +2083,34 @@ static void iavf_adminq_task(struct work_struct *work)\n \tif (val == 0xdeadbeef) /* indicates device in reset */\n \t\tgoto freedom;\n \toldval = val;\n-\tif (val & I40E_VF_ARQLEN1_ARQVFE_MASK) {\n+\tif (val & IAVF_VF_ARQLEN1_ARQVFE_MASK) {\n \t\tdev_info(&adapter->pdev->dev, \"ARQ VF Error detected\\n\");\n-\t\tval &= ~I40E_VF_ARQLEN1_ARQVFE_MASK;\n+\t\tval &= ~IAVF_VF_ARQLEN1_ARQVFE_MASK;\n \t}\n-\tif (val & I40E_VF_ARQLEN1_ARQOVFL_MASK) {\n+\tif (val & IAVF_VF_ARQLEN1_ARQOVFL_MASK) {\n \t\tdev_info(&adapter->pdev->dev, \"ARQ Overflow Error detected\\n\");\n-\t\tval &= ~I40E_VF_ARQLEN1_ARQOVFL_MASK;\n+\t\tval &= ~IAVF_VF_ARQLEN1_ARQOVFL_MASK;\n \t}\n-\tif (val & I40E_VF_ARQLEN1_ARQCRIT_MASK) {\n+\tif (val & IAVF_VF_ARQLEN1_ARQCRIT_MASK) {\n \t\tdev_info(&adapter->pdev->dev, \"ARQ Critical Error detected\\n\");\n-\t\tval &= ~I40E_VF_ARQLEN1_ARQCRIT_MASK;\n+\t\tval &= ~IAVF_VF_ARQLEN1_ARQCRIT_MASK;\n \t}\n \tif (oldval != val)\n \t\twr32(hw, hw->aq.arq.len, val);\n \n \tval = rd32(hw, hw->aq.asq.len);\n \toldval = val;\n-\tif (val & I40E_VF_ATQLEN1_ATQVFE_MASK) {\n+\tif (val & IAVF_VF_ATQLEN1_ATQVFE_MASK) {\n \t\tdev_info(&adapter->pdev->dev, \"ASQ VF Error detected\\n\");\n-\t\tval &= ~I40E_VF_ATQLEN1_ATQVFE_MASK;\n+\t\tval &= ~IAVF_VF_ATQLEN1_ATQVFE_MASK;\n \t}\n-\tif (val & I40E_VF_ATQLEN1_ATQOVFL_MASK) {\n+\tif (val & IAVF_VF_ATQLEN1_ATQOVFL_MASK) {\n \t\tdev_info(&adapter->pdev->dev, \"ASQ Overflow Error detected\\n\");\n-\t\tval &= ~I40E_VF_ATQLEN1_ATQOVFL_MASK;\n+\t\tval &= ~IAVF_VF_ATQLEN1_ATQOVFL_MASK;\n \t}\n-\tif (val & I40E_VF_ATQLEN1_ATQCRIT_MASK) {\n+\tif (val & IAVF_VF_ATQLEN1_ATQCRIT_MASK) {\n \t\tdev_info(&adapter->pdev->dev, \"ASQ Critical Error detected\\n\");\n-\t\tval &= ~I40E_VF_ATQLEN1_ATQCRIT_MASK;\n+\t\tval &= ~IAVF_VF_ATQLEN1_ATQCRIT_MASK;\n \t}\n \tif (oldval != val)\n \t\twr32(hw, hw->aq.asq.len, val);\n@@ -3251,8 +3247,8 @@ static int iavf_check_reset_complete(struct i40e_hw *hw)\n \tint i;\n \n \tfor (i = 0; i < 100; i++) {\n-\t\trstat = rd32(hw, I40E_VFGEN_RSTAT) &\n-\t\t\t I40E_VFGEN_RSTAT_VFR_STATE_MASK;\n+\t\trstat = rd32(hw, IAVF_VFGEN_RSTAT) &\n+\t\t\t IAVF_VFGEN_RSTAT_VFR_STATE_MASK;\n \t\tif ((rstat == VIRTCHNL_VFR_VFACTIVE) ||\n \t\t (rstat == VIRTCHNL_VFR_COMPLETED))\n \t\t\treturn 0;\ndiff --git a/drivers/net/ethernet/intel/iavf/iavf_txrx.c b/drivers/net/ethernet/intel/iavf/iavf_txrx.c\nindex d288694a6c83..01ec3944c3c9 100644\n--- a/drivers/net/ethernet/intel/iavf/iavf_txrx.c\n+++ b/drivers/net/ethernet/intel/iavf/iavf_txrx.c\n@@ -11,14 +11,14 @@\n static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,\n \t\t\t\tu32 td_tag)\n {\n-\treturn cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |\n+\treturn cpu_to_le64(IAVF_TX_DESC_DTYPE_DATA |\n \t\t\t ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |\n \t\t\t ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |\n \t\t\t ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |\n \t\t\t ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));\n }\n \n-#define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)\n+#define I40E_TXD_CMD (IAVF_TX_DESC_CMD_EOP | IAVF_TX_DESC_CMD_RS)\n \n /**\n * i40e_unmap_and_free_tx_resource - Release a Tx buffer\n@@ -198,7 +198,7 @@ static bool i40e_clean_tx_irq(struct i40e_vsi *vsi,\n \tunsigned int budget = vsi->work_limit;\n \n \ttx_buf = &tx_ring->tx_bi[i];\n-\ttx_desc = I40E_TX_DESC(tx_ring, i);\n+\ttx_desc = IAVF_TX_DESC(tx_ring, i);\n \ti -= tx_ring->count;\n \n \tdo {\n@@ -214,7 +214,7 @@ static bool i40e_clean_tx_irq(struct i40e_vsi *vsi,\n \t\ti40e_trace(clean_tx_irq, tx_ring, tx_desc, tx_buf);\n \t\t/* if the descriptor isn't done, no work yet to do */\n \t\tif (!(eop_desc->cmd_type_offset_bsz &\n-\t\t cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))\n+\t\t cpu_to_le64(IAVF_TX_DESC_DTYPE_DESC_DONE)))\n \t\t\tbreak;\n \n \t\t/* clear next_to_watch to prevent false hangs */\n@@ -248,7 +248,7 @@ static bool i40e_clean_tx_irq(struct i40e_vsi *vsi,\n \t\t\tif (unlikely(!i)) {\n \t\t\t\ti -= tx_ring->count;\n \t\t\t\ttx_buf = tx_ring->tx_bi;\n-\t\t\t\ttx_desc = I40E_TX_DESC(tx_ring, 0);\n+\t\t\t\ttx_desc = IAVF_TX_DESC(tx_ring, 0);\n \t\t\t}\n \n \t\t\t/* unmap any remaining paged data */\n@@ -268,7 +268,7 @@ static bool i40e_clean_tx_irq(struct i40e_vsi *vsi,\n \t\tif (unlikely(!i)) {\n \t\t\ti -= tx_ring->count;\n \t\t\ttx_buf = tx_ring->tx_bi;\n-\t\t\ttx_desc = I40E_TX_DESC(tx_ring, 0);\n+\t\t\ttx_desc = IAVF_TX_DESC(tx_ring, 0);\n \t\t}\n \n \t\tprefetch(tx_desc);\n@@ -342,11 +342,11 @@ static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi,\n \tif (q_vector->arm_wb_state)\n \t\treturn;\n \n-\tval = I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK |\n-\t I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK; /* set noitr */\n+\tval = IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK |\n+\t IAVF_VFINT_DYN_CTLN1_ITR_INDX_MASK; /* set noitr */\n \n \twr32(&vsi->back->hw,\n-\t I40E_VFINT_DYN_CTLN1(q_vector->reg_idx), val);\n+\t IAVF_VFINT_DYN_CTLN1(q_vector->reg_idx), val);\n \tq_vector->arm_wb_state = true;\n }\n \n@@ -358,14 +358,14 @@ static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi,\n **/\n void iavf_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)\n {\n-\tu32 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |\n-\t\t I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */\n-\t\t I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |\n-\t\t I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK\n+\tu32 val = IAVF_VFINT_DYN_CTLN1_INTENA_MASK |\n+\t\t IAVF_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */\n+\t\t IAVF_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |\n+\t\t IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK\n \t\t /* allow 00 to be written to the index */;\n \n \twr32(&vsi->back->hw,\n-\t I40E_VFINT_DYN_CTLN1(q_vector->reg_idx),\n+\t IAVF_VFINT_DYN_CTLN1(q_vector->reg_idx),\n \t val);\n }\n \n@@ -887,7 +887,7 @@ bool iavf_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count)\n \tif (!rx_ring->netdev || !cleaned_count)\n \t\treturn false;\n \n-\trx_desc = I40E_RX_DESC(rx_ring, ntu);\n+\trx_desc = IAVF_RX_DESC(rx_ring, ntu);\n \tbi = &rx_ring->rx_bi[ntu];\n \n \tdo {\n@@ -909,7 +909,7 @@ bool iavf_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count)\n \t\tbi++;\n \t\tntu++;\n \t\tif (unlikely(ntu == rx_ring->count)) {\n-\t\t\trx_desc = I40E_RX_DESC(rx_ring, 0);\n+\t\t\trx_desc = IAVF_RX_DESC(rx_ring, 0);\n \t\t\tbi = rx_ring->rx_bi;\n \t\t\tntu = 0;\n \t\t}\n@@ -968,7 +968,7 @@ static inline void i40e_rx_checksum(struct i40e_vsi *vsi,\n \t\treturn;\n \n \t/* did the hardware decode the packet and checksum? */\n-\tif (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))\n+\tif (!(rx_status & BIT(IAVF_RX_DESC_STATUS_L3L4P_SHIFT)))\n \t\treturn;\n \n \t/* both known and outer_ip must be set for the below code to work */\n@@ -981,25 +981,25 @@ static inline void i40e_rx_checksum(struct i40e_vsi *vsi,\n \t (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6);\n \n \tif (ipv4 &&\n-\t (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |\n-\t\t\t BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))\n+\t (rx_error & (BIT(IAVF_RX_DESC_ERROR_IPE_SHIFT) |\n+\t\t\t BIT(IAVF_RX_DESC_ERROR_EIPE_SHIFT))))\n \t\tgoto checksum_fail;\n \n \t/* likely incorrect csum if alternate IP extension headers found */\n \tif (ipv6 &&\n-\t rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))\n+\t rx_status & BIT(IAVF_RX_DESC_STATUS_IPV6EXADD_SHIFT))\n \t\t/* don't increment checksum err here, non-fatal err */\n \t\treturn;\n \n \t/* there was some L4 error, count error and punt packet to the stack */\n-\tif (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))\n+\tif (rx_error & BIT(IAVF_RX_DESC_ERROR_L4E_SHIFT))\n \t\tgoto checksum_fail;\n \n \t/* handle packets that were not able to be checksummed due\n \t * to arrival speed, in this case the stack can compute\n \t * the csum.\n \t */\n-\tif (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))\n+\tif (rx_error & BIT(IAVF_RX_DESC_ERROR_PPRS_SHIFT))\n \t\treturn;\n \n \t/* Only report checksum unnecessary for TCP, UDP, or SCTP */\n@@ -1056,8 +1056,8 @@ static inline void i40e_rx_hash(struct i40e_ring *ring,\n {\n \tu32 hash;\n \tconst __le64 rss_mask =\n-\t\tcpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<\n-\t\t\t I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);\n+\t\tcpu_to_le64((u64)IAVF_RX_DESC_FLTSTAT_RSS_HASH <<\n+\t\t\t IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT);\n \n \tif (ring->netdev->features & NETIF_F_RXHASH)\n \t\treturn;\n@@ -1437,10 +1437,10 @@ static bool i40e_is_non_eop(struct i40e_ring *rx_ring,\n \tntc = (ntc < rx_ring->count) ? ntc : 0;\n \trx_ring->next_to_clean = ntc;\n \n-\tprefetch(I40E_RX_DESC(rx_ring, ntc));\n+\tprefetch(IAVF_RX_DESC(rx_ring, ntc));\n \n \t/* if we are the last buffer then there is nothing else to do */\n-#define I40E_RXD_EOF BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)\n+#define I40E_RXD_EOF BIT(IAVF_RX_DESC_STATUS_EOF_SHIFT)\n \tif (likely(i40e_test_staterr(rx_desc, I40E_RXD_EOF)))\n \t\treturn false;\n \n@@ -1483,7 +1483,7 @@ static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget)\n \t\t\tcleaned_count = 0;\n \t\t}\n \n-\t\trx_desc = I40E_RX_DESC(rx_ring, rx_ring->next_to_clean);\n+\t\trx_desc = IAVF_RX_DESC(rx_ring, rx_ring->next_to_clean);\n \n \t\t/* status_error_len will always be zero for unused descriptors\n \t\t * because it's cleared in cleanup, and overlaps with hdr_addr\n@@ -1529,7 +1529,7 @@ static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget)\n \n \t\t/* ERR_MASK will only have valid bits if EOP set, and\n \t\t * what we are doing here is actually checking\n-\t\t * I40E_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in\n+\t\t * IAVF_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in\n \t\t * the error field\n \t\t */\n \t\tif (unlikely(i40e_test_staterr(rx_desc, BIT(I40E_RXD_QW1_ERROR_SHIFT)))) {\n@@ -1554,7 +1554,7 @@ static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget)\n \t\tiavf_process_skb_fields(rx_ring, rx_desc, skb, rx_ptype);\n \n \n-\t\tvlan_tag = (qword & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) ?\n+\t\tvlan_tag = (qword & BIT(IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT)) ?\n \t\t\t le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1) : 0;\n \n \t\ti40e_trace(clean_rx_irq_rx, rx_ring, rx_desc, skb);\n@@ -1599,15 +1599,15 @@ static inline u32 i40e_buildreg_itr(const int type, u16 itr)\n \t */\n \titr &= I40E_ITR_MASK;\n \n-\tval = I40E_VFINT_DYN_CTLN1_INTENA_MASK |\n-\t (type << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |\n-\t (itr << (I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT - 1));\n+\tval = IAVF_VFINT_DYN_CTLN1_INTENA_MASK |\n+\t (type << IAVF_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |\n+\t (itr << (IAVF_VFINT_DYN_CTLN1_INTERVAL_SHIFT - 1));\n \n \treturn val;\n }\n \n /* a small macro to shorten up some long lines */\n-#define INTREG I40E_VFINT_DYN_CTLN1\n+#define INTREG IAVF_VFINT_DYN_CTLN1\n \n /* The act of updating the ITR will cause it to immediately trigger. In order\n * to prevent this from throwing off adaptive update statistics we defer the\n@@ -1968,7 +1968,7 @@ static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,\n \tl4.hdr = skb_transport_header(skb);\n \n \t/* compute outer L2 header size */\n-\toffset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;\n+\toffset = ((ip.hdr - skb->data) / 2) << IAVF_TX_DESC_LENGTH_MACLEN_SHIFT;\n \n \tif (skb->encapsulation) {\n \t\tu32 tunnel = 0;\n@@ -2051,10 +2051,10 @@ static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,\n \t\t * need the hardware to recompute it is in the case of TSO.\n \t\t */\n \t\tcmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ?\n-\t\t I40E_TX_DESC_CMD_IIPT_IPV4_CSUM :\n-\t\t I40E_TX_DESC_CMD_IIPT_IPV4;\n+\t\t IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM :\n+\t\t IAVF_TX_DESC_CMD_IIPT_IPV4;\n \t} else if (*tx_flags & I40E_TX_FLAGS_IPV6) {\n-\t\tcmd |= I40E_TX_DESC_CMD_IIPT_IPV6;\n+\t\tcmd |= IAVF_TX_DESC_CMD_IIPT_IPV6;\n \n \t\texthdr = ip.hdr + sizeof(*ip.v6);\n \t\tl4_proto = ip.v6->nexthdr;\n@@ -2064,26 +2064,26 @@ static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,\n \t}\n \n \t/* compute inner L3 header size */\n-\toffset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;\n+\toffset |= ((l4.hdr - ip.hdr) / 4) << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;\n \n \t/* Enable L4 checksum offloads */\n \tswitch (l4_proto) {\n \tcase IPPROTO_TCP:\n \t\t/* enable checksum offloads */\n-\t\tcmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;\n-\t\toffset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;\n+\t\tcmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;\n+\t\toffset |= l4.tcp->doff << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;\n \t\tbreak;\n \tcase IPPROTO_SCTP:\n \t\t/* enable SCTP checksum offload */\n-\t\tcmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;\n+\t\tcmd |= IAVF_TX_DESC_CMD_L4T_EOFT_SCTP;\n \t\toffset |= (sizeof(struct sctphdr) >> 2) <<\n-\t\t\t I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;\n+\t\t\t IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;\n \t\tbreak;\n \tcase IPPROTO_UDP:\n \t\t/* enable UDP checksum offload */\n-\t\tcmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;\n+\t\tcmd |= IAVF_TX_DESC_CMD_L4T_EOFT_UDP;\n \t\toffset |= (sizeof(struct udphdr) >> 2) <<\n-\t\t\t I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;\n+\t\t\t IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;\n \t\tbreak;\n \tdefault:\n \t\tif (*tx_flags & I40E_TX_FLAGS_TSO)\n@@ -2112,12 +2112,12 @@ static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,\n \tstruct i40e_tx_context_desc *context_desc;\n \tint i = tx_ring->next_to_use;\n \n-\tif ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&\n+\tif ((cd_type_cmd_tso_mss == IAVF_TX_DESC_DTYPE_CONTEXT) &&\n \t !cd_tunneling && !cd_l2tag2)\n \t\treturn;\n \n \t/* grab the next descriptor */\n-\tcontext_desc = I40E_TX_CTXTDESC(tx_ring, i);\n+\tcontext_desc = IAVF_TX_CTXTDESC(tx_ring, i);\n \n \ti++;\n \ttx_ring->next_to_use = (i < tx_ring->count) ? i : 0;\n@@ -2260,7 +2260,7 @@ static inline void iavf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,\n \tdma_addr_t dma;\n \n \tif (tx_flags & I40E_TX_FLAGS_HW_VLAN) {\n-\t\ttd_cmd |= I40E_TX_DESC_CMD_IL2TAG1;\n+\t\ttd_cmd |= IAVF_TX_DESC_CMD_IL2TAG1;\n \t\ttd_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>\n \t\t\t I40E_TX_FLAGS_VLAN_SHIFT;\n \t}\n@@ -2269,7 +2269,7 @@ static inline void iavf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,\n \n \tdma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);\n \n-\ttx_desc = I40E_TX_DESC(tx_ring, i);\n+\ttx_desc = IAVF_TX_DESC(tx_ring, i);\n \ttx_bi = first;\n \n \tfor (frag = &skb_shinfo(skb)->frags[0];; frag++) {\n@@ -2295,7 +2295,7 @@ static inline void iavf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,\n \t\t\ti++;\n \n \t\t\tif (i == tx_ring->count) {\n-\t\t\t\ttx_desc = I40E_TX_DESC(tx_ring, 0);\n+\t\t\t\ttx_desc = IAVF_TX_DESC(tx_ring, 0);\n \t\t\t\ti = 0;\n \t\t\t}\n \n@@ -2316,7 +2316,7 @@ static inline void iavf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,\n \t\ti++;\n \n \t\tif (i == tx_ring->count) {\n-\t\t\ttx_desc = I40E_TX_DESC(tx_ring, 0);\n+\t\t\ttx_desc = IAVF_TX_DESC(tx_ring, 0);\n \t\t\ti = 0;\n \t\t}\n \n@@ -2394,7 +2394,7 @@ static inline void iavf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,\n static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,\n \t\t\t\t\tstruct i40e_ring *tx_ring)\n {\n-\tu64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;\n+\tu64 cd_type_cmd_tso_mss = IAVF_TX_DESC_DTYPE_CONTEXT;\n \tu32 cd_tunneling = 0, cd_l2tag2 = 0;\n \tstruct i40e_tx_buffer *first;\n \tu32 td_offset = 0;\n@@ -2465,7 +2465,7 @@ static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,\n \tskb_tx_timestamp(skb);\n \n \t/* always enable CRC insertion offload */\n-\ttd_cmd |= I40E_TX_DESC_CMD_ICRC;\n+\ttd_cmd |= IAVF_TX_DESC_CMD_ICRC;\n \n \ti40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,\n \t\t\t cd_tunneling, cd_l2tag2);\ndiff --git a/drivers/net/ethernet/intel/iavf/iavf_txrx.h b/drivers/net/ethernet/intel/iavf/iavf_txrx.h\nindex 5dbb1cd52feb..db2ec715f3b5 100644\n--- a/drivers/net/ethernet/intel/iavf/iavf_txrx.h\n+++ b/drivers/net/ethernet/intel/iavf/iavf_txrx.h\n@@ -186,7 +186,7 @@ static inline bool i40e_test_staterr(union i40e_rx_desc *rx_desc,\n \t\t(i)++;\t\t\t\t\\\n \t\tif ((i) == (r)->count)\t\t\\\n \t\t\ti = 0;\t\t\t\\\n-\t\t(n) = I40E_RX_DESC((r), (i));\t\\\n+\t\t(n) = IAVF_RX_DESC((r), (i));\t\\\n \t} while (0)\n \n #define I40E_RX_NEXT_DESC_PREFETCH(r, i, n)\t\t\\\n", "prefixes": [ "net-next", "v2", "06/14" ] }