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GET /api/patches/963012/?format=api
{ "id": 963012, "url": "http://patchwork.ozlabs.org/api/patches/963012/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20180828155949.26316-1-sasha.neftin@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20180828155949.26316-1-sasha.neftin@intel.com>", "list_archive_url": null, "date": "2018-08-28T15:59:49", "name": "[v7,02/11] igc: Add support for PF", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "fc0517a9a2250c4dda3784dc120f3c3720430b0b", "submitter": { "id": 69860, "url": "http://patchwork.ozlabs.org/api/people/69860/?format=api", "name": "Sasha Neftin", "email": "sasha.neftin@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20180828155949.26316-1-sasha.neftin@intel.com/mbox/", "series": [ { "id": 62908, "url": "http://patchwork.ozlabs.org/api/series/62908/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=62908", "date": "2018-08-28T15:59:52", "name": "[v7,01/11] igc: Add skeletal frame for Intel(R) 2.5G Ethernet Controller support.", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/62908/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/963012/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/963012/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.138; helo=whitealder.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 420D3n2dLlz9s1x\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 29 Aug 2018 02:00:05 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 978B385AFB;\n\tTue, 28 Aug 2018 16:00:03 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id XwW4xmFOmFJ4; Tue, 28 Aug 2018 15:59:59 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 7F678846B0;\n\tTue, 28 Aug 2018 15:59:59 +0000 (UTC)", "from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\tby ash.osuosl.org (Postfix) with ESMTP id 591CF1C2272\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tTue, 28 Aug 2018 15:59:58 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 56299847E9\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tTue, 28 Aug 2018 15:59:58 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id lkYG_XNZ97fn for <intel-wired-lan@lists.osuosl.org>;\n\tTue, 28 Aug 2018 15:59:56 +0000 (UTC)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n\tby fraxinus.osuosl.org (Postfix) with ESMTPS id 847B6847DE\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tTue, 28 Aug 2018 15:59:56 +0000 (UTC)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n\tby fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t28 Aug 2018 08:59:56 -0700", "from ccdlinuxdev08.iil.intel.com ([143.185.161.150])\n\tby fmsmga005.fm.intel.com with ESMTP; 28 Aug 2018 08:59:49 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.53,300,1531810800\"; d=\"scan'208\";a=\"257924625\"", "From": "Sasha Neftin <sasha.neftin@intel.com>", "To": "sasha.neftin@intel.com,\n\tintel-wired-lan@lists.osuosl.org", "Date": "Tue, 28 Aug 2018 18:59:49 +0300", "Message-Id": "<20180828155949.26316-1-sasha.neftin@intel.com>", "X-Mailer": "git-send-email 2.11.0", "Subject": "[Intel-wired-lan] [PATCH v7 02/11] igc: Add support for PF", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.24", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "This patch adds the basic defines and structures needed by the PF for\noperation. With this it is possible to bring up the interface,\nbut without being able to configure any of the filters on\nthe interface itself.\nAdd skeleton for a function pointers.\n\nSasha Neftin (v2):\nadd description\nfix code indentation\n\nSasha Neftin (v3):\nsquash patches, clean code and remove unused values\nremove duplication\n\nSasha Neftin (v4):\naddress comments\nremove unused PCIE definition\nremove unused MAX_MTA_REG definition\nremove unused NVM registers\nremove unused PCIE registers\nremove unused DMA registers\nremove unused Receive registers\nremove unused Transmit registers\nfix typos\nreplace e1000_ prefix with igc_ prefix\nremove unused PCIE defines\nremove unused EEE register, will be add per needs\nremove unused SERDES definitions\n\nSasha Neftin (v5):\nresolve automatic test system error\nadd __iomem to *hw_addr definition\nremove obsolete flash_address definition\n\nSasha Neftin (v6):\nfix code indentation\nremove unused defines from igc_defines.h\nminor cosmetic changes\n\nSasha Neftin (v7):\nno changes\n\nSigned-off-by: Sasha Neftin <sasha.neftin@intel.com>\n---\n drivers/net/ethernet/intel/igc/Makefile | 2 +-\n drivers/net/ethernet/intel/igc/igc.h | 13 ++\n drivers/net/ethernet/intel/igc/igc_defines.h | 33 +++++\n drivers/net/ethernet/intel/igc/igc_hw.h | 112 ++++++++++++++++\n drivers/net/ethernet/intel/igc/igc_i225.h | 10 ++\n drivers/net/ethernet/intel/igc/igc_mac.c | 51 +++++++\n drivers/net/ethernet/intel/igc/igc_mac.h | 13 ++\n drivers/net/ethernet/intel/igc/igc_main.c | 101 ++++++++++++++\n drivers/net/ethernet/intel/igc/igc_regs.h | 192 +++++++++++++++++++++++++++\n 9 files changed, 526 insertions(+), 1 deletion(-)\n create mode 100644 drivers/net/ethernet/intel/igc/igc_defines.h\n create mode 100644 drivers/net/ethernet/intel/igc/igc_i225.h\n create mode 100644 drivers/net/ethernet/intel/igc/igc_mac.c\n create mode 100644 drivers/net/ethernet/intel/igc/igc_mac.h\n create mode 100644 drivers/net/ethernet/intel/igc/igc_regs.h", "diff": "diff --git a/drivers/net/ethernet/intel/igc/Makefile b/drivers/net/ethernet/intel/igc/Makefile\nindex 3d13b015d401..06e0b9e23a8c 100644\n--- a/drivers/net/ethernet/intel/igc/Makefile\n+++ b/drivers/net/ethernet/intel/igc/Makefile\n@@ -7,4 +7,4 @@\n \n obj-$(CONFIG_IGC) += igc.o\n \n-igc-objs := igc_main.o\n+igc-objs := igc_main.o igc_mac.o\ndiff --git a/drivers/net/ethernet/intel/igc/igc.h b/drivers/net/ethernet/intel/igc/igc.h\nindex afe595cfcf63..481b2ee694fa 100644\n--- a/drivers/net/ethernet/intel/igc/igc.h\n+++ b/drivers/net/ethernet/intel/igc/igc.h\n@@ -22,8 +22,21 @@\n #include <linux/net_tstamp.h>\n #include <linux/ptp_clock_kernel.h>\n \n+#include \"igc_hw.h\"\n+\n /* main */\n extern char igc_driver_name[];\n extern char igc_driver_version[];\n \n+/* Board specific private data structure */\n+struct igc_adapter {\n+\tu8 __iomem *io_addr;\n+\n+\t/* OS defined structs */\n+\tstruct pci_dev *pdev;\n+\n+\t/* structs defined in igc_hw.h */\n+\tstruct igc_hw hw;\n+};\n+\n #endif /* _IGC_H_ */\ndiff --git a/drivers/net/ethernet/intel/igc/igc_defines.h b/drivers/net/ethernet/intel/igc/igc_defines.h\nnew file mode 100644\nindex 000000000000..05bdba94b045\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/igc/igc_defines.h\n@@ -0,0 +1,33 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/* Copyright (c) 2018 Intel Corporation */\n+\n+#ifndef _IGC_DEFINES_H_\n+#define _IGC_DEFINES_H_\n+\n+/* PCI Function Mask */\n+#define IGC_STATUS_FUNC_MASK\t\t\t0x0000000C\n+\n+/* PCI Bus Info */\n+#define PCIE_DEVICE_CONTROL2\t\t0x28\n+#define PCIE_DEVICE_CONTROL2_16ms\t0x0005\n+\n+/* Error Codes */\n+#define IGC_SUCCESS\t\t\t0\n+#define IGC_ERR_NVM\t\t\t1\n+#define IGC_ERR_PHY\t\t\t2\n+#define IGC_ERR_CONFIG\t\t\t3\n+#define IGC_ERR_PARAM\t\t\t4\n+#define IGC_ERR_MAC_INIT\t\t5\n+#define IGC_ERR_RESET\t\t\t9\n+\n+/* Device Status */\n+#define IGC_STATUS_FD\t\t0x00000001 /* Full duplex.0=half,1=full */\n+#define IGC_STATUS_LU\t\t0x00000002 /* Link up.0=no,1=link */\n+#define IGC_STATUS_FUNC_MASK\t0x0000000C /* PCI Function Mask */\n+#define IGC_STATUS_FUNC_SHIFT\t2\n+#define IGC_STATUS_FUNC_1\t0x00000004 /* Function 1 */\n+#define IGC_STATUS_TXOFF\t0x00000010 /* transmission paused */\n+#define IGC_STATUS_SPEED_100\t0x00000040 /* Speed 100Mb/s */\n+#define IGC_STATUS_SPEED_1000\t0x00000080 /* Speed 1000Mb/s */\n+\n+#endif /* _IGC_DEFINES_H_ */\ndiff --git a/drivers/net/ethernet/intel/igc/igc_hw.h b/drivers/net/ethernet/intel/igc/igc_hw.h\nindex aa68b4516700..f115ef08f8ac 100644\n--- a/drivers/net/ethernet/intel/igc/igc_hw.h\n+++ b/drivers/net/ethernet/intel/igc/igc_hw.h\n@@ -4,7 +4,119 @@\n #ifndef _IGC_HW_H_\n #define _IGC_HW_H_\n \n+#include <linux/types.h>\n+#include <linux/if_ether.h>\n+#include \"igc_regs.h\"\n+#include \"igc_defines.h\"\n+#include \"igc_mac.h\"\n+#include \"igc_i225.h\"\n+\n #define IGC_DEV_ID_I225_LM\t\t\t0x15F2\n #define IGC_DEV_ID_I225_V\t\t\t0x15F3\n \n+/* forward declaration */\n+struct igc_hw;\n+\n+/* Function pointers for the MAC. */\n+struct igc_mac_operations {\n+};\n+\n+enum igc_mac_type {\n+\tigc_undefined = 0,\n+\tigc_i225,\n+\tigc_num_macs /* List is 1-based, so subtract 1 for true count. */\n+};\n+\n+enum igc_phy_type {\n+\tigc_phy_unknown = 0,\n+\tigc_phy_none,\n+\tigc_phy_i225,\n+};\n+\n+enum igc_bus_type {\n+\tigc_bus_type_unknown = 0,\n+\tigc_bus_type_pci_express,\n+\tigc_bus_type_reserved\n+};\n+\n+enum igc_bus_speed {\n+\tigc_bus_speed_unknown = 0,\n+\tigc_bus_speed_2500,\n+\tigc_bus_speed_5000,\n+\tigc_bus_speed_reserved\n+};\n+\n+enum igc_bus_width {\n+\tigc_bus_width_unknown = 0,\n+\tigc_bus_width_pcie_x1 = 1,\n+\tigc_bus_width_pcie_x2 = 2,\n+\tigc_bus_width_pcie_x4 = 4,\n+\tigc_bus_width_pcie_x8 = 8,\n+\tigc_bus_width_reserved\n+};\n+\n+struct igc_mac_info {\n+\tstruct igc_mac_operations ops;\n+\n+\tu8 addr[ETH_ALEN];\n+\tu8 perm_addr[ETH_ALEN];\n+\n+\tenum igc_mac_type type;\n+\n+\tu32 collision_delta;\n+\tu32 ledctl_default;\n+\tu32 ledctl_mode1;\n+\tu32 ledctl_mode2;\n+\tu32 mc_filter_type;\n+\tu32 tx_packet_delta;\n+\tu32 txcw;\n+\n+\tu16 mta_reg_count;\n+\tu16 uta_reg_count;\n+\n+\tu16 rar_entry_count;\n+\n+\tu8 forced_speed_duplex;\n+\n+\tbool adaptive_ifs;\n+\tbool has_fwsm;\n+\tbool arc_subsystem_valid;\n+\n+\tbool autoneg;\n+\tbool autoneg_failed;\n+};\n+\n+struct igc_bus_info {\n+\tenum igc_bus_type type;\n+\tenum igc_bus_speed speed;\n+\tenum igc_bus_width width;\n+\n+\tu16 func;\n+\tu16 pci_cmd_word;\n+};\n+\n+struct igc_hw {\n+\tvoid *back;\n+\n+\tu8 __iomem *hw_addr;\n+\tunsigned long io_base;\n+\n+\tstruct igc_mac_info mac;\n+\n+\tstruct igc_bus_info bus;\n+\n+\tu16 device_id;\n+\tu16 subsystem_vendor_id;\n+\tu16 subsystem_device_id;\n+\tu16 vendor_id;\n+\n+\tu8 revision_id;\n+};\n+\n+/* These functions must be implemented by drivers */\n+s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);\n+s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);\n+void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);\n+void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);\n+\n #endif /* _IGC_HW_H_ */\ndiff --git a/drivers/net/ethernet/intel/igc/igc_i225.h b/drivers/net/ethernet/intel/igc/igc_i225.h\nnew file mode 100644\nindex 000000000000..461cd8c7e352\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/igc/igc_i225.h\n@@ -0,0 +1,10 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/* Copyright (c) 2018 Intel Corporation */\n+\n+#ifndef _IGC_I225_H_\n+#define _IGC_I225_H_\n+\n+s32 igc_acquire_swfw_sync_i225(struct igc_hw *hw, u16 mask);\n+void igc_release_swfw_sync_i225(struct igc_hw *hw, u16 mask);\n+\n+#endif\ndiff --git a/drivers/net/ethernet/intel/igc/igc_mac.c b/drivers/net/ethernet/intel/igc/igc_mac.c\nnew file mode 100644\nindex 000000000000..0c81ea3bc706\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/igc/igc_mac.c\n@@ -0,0 +1,51 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/* Copyright (c) 2018 Intel Corporation */\n+\n+#include <linux/pci.h>\n+#include \"igc_hw.h\"\n+\n+/**\n+ * igc_get_bus_info_pcie - Get PCIe bus information\n+ * @hw: pointer to the HW structure\n+ *\n+ * Determines and stores the system bus information for a particular\n+ * network interface. The following bus information is determined and stored:\n+ * bus speed, bus width, type (PCIe), and PCIe function.\n+ **/\n+s32 igc_get_bus_info_pcie(struct igc_hw *hw)\n+{\n+\tstruct igc_bus_info *bus = &hw->bus;\n+\tu16 pcie_link_status;\n+\ts32 ret_val;\n+\tu32 reg = 0;\n+\n+\tbus->type = igc_bus_type_pci_express;\n+\n+\tret_val = igc_read_pcie_cap_reg(hw, PCI_EXP_LNKSTA,\n+\t\t\t\t\t&pcie_link_status);\n+\tif (ret_val) {\n+\t\tbus->width = igc_bus_width_unknown;\n+\t\tbus->speed = igc_bus_speed_unknown;\n+\t} else {\n+\t\tswitch (pcie_link_status & PCI_EXP_LNKSTA_CLS) {\n+\t\tcase PCI_EXP_LNKSTA_CLS_2_5GB:\n+\t\t\tbus->speed = igc_bus_speed_2500;\n+\t\t\tbreak;\n+\t\tcase PCI_EXP_LNKSTA_CLS_5_0GB:\n+\t\t\tbus->speed = igc_bus_speed_5000;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tbus->speed = igc_bus_speed_unknown;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tbus->width = (enum igc_bus_width)((pcie_link_status &\n+\t\t\t\t\t\t PCI_EXP_LNKSTA_NLW) >>\n+\t\t\t\t\t\t PCI_EXP_LNKSTA_NLW_SHIFT);\n+\t}\n+\n+\treg = rd32(IGC_STATUS);\n+\tbus->func = (reg & IGC_STATUS_FUNC_MASK) >> IGC_STATUS_FUNC_SHIFT;\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/net/ethernet/intel/igc/igc_mac.h b/drivers/net/ethernet/intel/igc/igc_mac.h\nnew file mode 100644\nindex 000000000000..f5de0213c2a5\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/igc/igc_mac.h\n@@ -0,0 +1,13 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/* Copyright (c) 2018 Intel Corporation */\n+\n+#ifndef _IGC_MAC_H_\n+#define _IGC_MAC_H_\n+\n+#ifndef IGC_REMOVED\n+#define IGC_REMOVED(a) (0)\n+#endif /* IGC_REMOVED */\n+\n+s32 igc_get_bus_info_pcie(struct igc_hw *hw);\n+\n+#endif\ndiff --git a/drivers/net/ethernet/intel/igc/igc_main.c b/drivers/net/ethernet/intel/igc/igc_main.c\nindex c926dab0057d..6413ad5ff13a 100644\n--- a/drivers/net/ethernet/intel/igc/igc_main.c\n+++ b/drivers/net/ethernet/intel/igc/igc_main.c\n@@ -25,6 +25,69 @@ static const struct pci_device_id igc_pci_tbl[] = {\n \n MODULE_DEVICE_TABLE(pci, igc_pci_tbl);\n \n+/* forward declaration */\n+static int igc_sw_init(struct igc_adapter *);\n+\n+/* PCIe configuration access */\n+void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value)\n+{\n+\tstruct igc_adapter *adapter = hw->back;\n+\n+\tpci_read_config_word(adapter->pdev, reg, value);\n+}\n+\n+void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value)\n+{\n+\tstruct igc_adapter *adapter = hw->back;\n+\n+\tpci_write_config_word(adapter->pdev, reg, *value);\n+}\n+\n+s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value)\n+{\n+\tstruct igc_adapter *adapter = hw->back;\n+\tu16 cap_offset;\n+\n+\tcap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);\n+\tif (!cap_offset)\n+\t\treturn -IGC_ERR_CONFIG;\n+\n+\tpci_read_config_word(adapter->pdev, cap_offset + reg, value);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value)\n+{\n+\tstruct igc_adapter *adapter = hw->back;\n+\tu16 cap_offset;\n+\n+\tcap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);\n+\tif (!cap_offset)\n+\t\treturn -IGC_ERR_CONFIG;\n+\n+\tpci_write_config_word(adapter->pdev, cap_offset + reg, *value);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+u32 igc_rd32(struct igc_hw *hw, u32 reg)\n+{\n+\tu8 __iomem *hw_addr = READ_ONCE(hw->hw_addr);\n+\tu32 value = 0;\n+\n+\tif (IGC_REMOVED(hw_addr))\n+\t\treturn ~value;\n+\n+\tvalue = readl(&hw_addr[reg]);\n+\n+\t/* reads should not return all F's */\n+\tif (!(~value) && (!reg || !(~readl(hw_addr))))\n+\t\thw->hw_addr = NULL;\n+\n+\treturn value;\n+}\n+\n /**\n * igc_probe - Device Initialization Routine\n * @pdev: PCI device information struct\n@@ -39,6 +102,8 @@ MODULE_DEVICE_TABLE(pci, igc_pci_tbl);\n static int igc_probe(struct pci_dev *pdev,\n \t\t const struct pci_device_id *ent)\n {\n+\tstruct igc_adapter *adapter;\n+\tstruct igc_hw *hw;\n \tint err, pci_using_dac;\n \n \terr = pci_enable_device_mem(pdev);\n@@ -73,8 +138,17 @@ static int igc_probe(struct pci_dev *pdev,\n \n \tpci_set_master(pdev);\n \tpci_save_state(pdev);\n+\n+\t/* setup the private structure */\n+\terr = igc_sw_init(adapter);\n+\tif (err)\n+\t\tgoto err_sw_init;\n+\n+\tigc_get_bus_info_pcie(hw);\n+\n \treturn 0;\n \n+err_sw_init:\n err_pci_reg:\n err_dma:\n \tpci_disable_device(pdev);\n@@ -106,6 +180,33 @@ static struct pci_driver igc_driver = {\n };\n \n /**\n+ * igc_sw_init - Initialize general software structures (struct igc_adapter)\n+ * @adapter: board private structure to initialize\n+ *\n+ * igc_sw_init initializes the Adapter private data structure.\n+ * Fields are initialized based on PCI device information and\n+ * OS network device settings (MTU size).\n+ **/\n+static int igc_sw_init(struct igc_adapter *adapter)\n+{\n+\tstruct pci_dev *pdev = adapter->pdev;\n+\tstruct igc_hw *hw = &adapter->hw;\n+\n+\t/* PCI config space info */\n+\n+\thw->vendor_id = pdev->vendor;\n+\thw->device_id = pdev->device;\n+\thw->subsystem_vendor_id = pdev->subsystem_vendor;\n+\thw->subsystem_device_id = pdev->subsystem_device;\n+\n+\tpci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);\n+\n+\tpci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);\n+\n+\treturn 0;\n+}\n+\n+/**\n * igc_init_module - Driver Registration Routine\n *\n * igc_init_module is the first routine called when the driver is\ndiff --git a/drivers/net/ethernet/intel/igc/igc_regs.h b/drivers/net/ethernet/intel/igc/igc_regs.h\nnew file mode 100644\nindex 000000000000..d390b5336cc7\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/igc/igc_regs.h\n@@ -0,0 +1,192 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/* Copyright (c) 2018 Intel Corporation */\n+\n+#ifndef _IGC_REGS_H_\n+#define _IGC_REGS_H_\n+\n+/* General Register Descriptions */\n+#define IGC_CTRL\t\t0x00000 /* Device Control - RW */\n+#define IGC_STATUS\t\t0x00008 /* Device Status - RO */\n+#define IGC_CTRL_EXT\t\t0x00018 /* Extended Device Control - RW */\n+#define IGC_MDIC\t\t0x00020 /* MDI Control - RW */\n+#define IGC_MDICNFG\t\t0x00E04 /* MDC/MDIO Configuration - RW */\n+#define IGC_CONNSW\t\t0x00034 /* Copper/Fiber switch control - RW */\n+\n+/* Internal Packet Buffer Size Registers */\n+#define IGC_RXPBS\t\t0x02404 /* Rx Packet Buffer Size - RW */\n+#define IGC_TXPBS\t\t0x03404 /* Tx Packet Buffer Size - RW */\n+\n+/* NVM Register Descriptions */\n+#define IGC_EERD\t\t0x12014 /* EEprom mode read - RW */\n+#define IGC_EEWR\t\t0x12018 /* EEprom mode write - RW */\n+\n+/* Flow Control Register Descriptions */\n+#define IGC_FCAL\t\t0x00028 /* FC Address Low - RW */\n+#define IGC_FCAH\t\t0x0002C /* FC Address High - RW */\n+#define IGC_FCT\t\t\t0x00030 /* FC Type - RW */\n+#define IGC_FCTTV\t\t0x00170 /* FC Transmit Timer - RW */\n+#define IGC_FCRTL\t\t0x02160 /* FC Receive Threshold Low - RW */\n+#define IGC_FCRTH\t\t0x02168 /* FC Receive Threshold High - RW */\n+#define IGC_FCRTV\t\t0x02460 /* FC Refresh Timer Value - RW */\n+#define IGC_FCSTS\t\t0x02464 /* FC Status - RO */\n+\n+/* PCIe Register Description */\n+#define IGC_GCR\t\t\t0x05B00 /* PCIe control- RW */\n+\n+/* Semaphore registers */\n+#define IGC_SW_FW_SYNC\t\t0x05B5C /* SW-FW Synchronization - RW */\n+#define IGC_SWSM\t\t0x05B50 /* SW Semaphore */\n+#define IGC_FWSM\t\t0x05B54 /* FW Semaphore */\n+\n+/* Interrupt Register Description */\n+#define IGC_EICS\t\t0x01520 /* Ext. Interrupt Cause Set - W0 */\n+#define IGC_EIMS\t\t0x01524 /* Ext. Interrupt Mask Set/Read - RW */\n+#define IGC_EIMC\t\t0x01528 /* Ext. Interrupt Mask Clear - WO */\n+#define IGC_EIAC\t\t0x0152C /* Ext. Interrupt Auto Clear - RW */\n+#define IGC_EIAM\t\t0x01530 /* Ext. Interrupt Auto Mask - RW */\n+#define IGC_ICR\t\t\t0x01500 /* Intr Cause Read - RC/W1C */\n+#define IGC_ICS\t\t\t0x01504 /* Intr Cause Set - WO */\n+#define IGC_IMS\t\t\t0x01508 /* Intr Mask Set/Read - RW */\n+#define IGC_IMC\t\t\t0x0150C /* Intr Mask Clear - WO */\n+#define IGC_IAM\t\t\t0x01510 /* Intr Ack Auto Mask- RW */\n+/* Intr Throttle - RW */\n+#define IGC_EITR(_n)\t\t(0x01680 + (0x4 * (_n)))\n+/* Interrupt Vector Allocation - RW */\n+#define IGC_IVAR0\t\t0x01700\n+#define IGC_IVAR_MISC\t\t0x01740 /* IVAR for \"other\" causes - RW */\n+#define IGC_GPIE\t\t0x01514 /* General Purpose Intr Enable - RW */\n+\n+/* MSI-X Table Register Descriptions */\n+#define IGC_PBACL\t\t0x05B68 /* MSIx PBA Clear - R/W 1 to clear */\n+\n+/* Receive Register Descriptions */\n+#define IGC_RCTL\t\t0x00100 /* Rx Control - RW */\n+#define IGC_SRRCTL(_n)\t\t(0x0C00C + ((_n) * 0x40))\n+#define IGC_PSRTYPE(_i)\t\t(0x05480 + ((_i) * 4))\n+#define IGC_RDBAL(_n)\t\t(0x0C000 + ((_n) * 0x40))\n+#define IGC_RDBAH(_n)\t\t(0x0C004 + ((_n) * 0x40))\n+#define IGC_RDLEN(_n)\t\t(0x0C008 + ((_n) * 0x40))\n+#define IGC_RDH(_n)\t\t(0x0C010 + ((_n) * 0x40))\n+#define IGC_RDT(_n)\t\t(0x0C018 + ((_n) * 0x40))\n+#define IGC_RXDCTL(_n)\t\t(0x0C028 + ((_n) * 0x40))\n+#define IGC_RQDPC(_n)\t\t(0x0C030 + ((_n) * 0x40))\n+#define IGC_RXCSUM\t\t0x05000 /* Rx Checksum Control - RW */\n+#define IGC_RLPML\t\t0x05004 /* Rx Long Packet Max Length */\n+#define IGC_RFCTL\t\t0x05008 /* Receive Filter Control*/\n+#define IGC_RAL(_n)\t\t(0x05400 + ((_n) * 0x08))\n+#define IGC_RAH(_n)\t\t(0x05404 + ((_n) * 0x08))\n+\n+/* Transmit Register Descriptions */\n+#define IGC_TCTL\t\t0x00400 /* Tx Control - RW */\n+#define IGC_TIPG\t\t0x00410 /* Tx Inter-packet gap - RW */\n+#define IGC_TDBAL(_n)\t\t(0x0E000 + ((_n) * 0x40))\n+#define IGC_TDBAH(_n)\t\t(0x0E004 + ((_n) * 0x40))\n+#define IGC_TDLEN(_n)\t\t(0x0E008 + ((_n) * 0x40))\n+#define IGC_TDH(_n)\t\t(0x0E010 + ((_n) * 0x40))\n+#define IGC_TDT(_n)\t\t(0x0E018 + ((_n) * 0x40))\n+#define IGC_TXDCTL(_n)\t\t(0x0E028 + ((_n) * 0x40))\n+\n+/* MMD Register Descriptions */\n+#define IGC_MMDAC\t\t13 /* MMD Access Control */\n+#define IGC_MMDAAD\t\t14 /* MMD Access Address/Data */\n+\n+/* Good transmitted packets counter registers */\n+#define IGC_PQGPTC(_n)\t\t(0x010014 + (0x100 * (_n)))\n+\n+/* Statistics Register Descriptions */\n+#define IGC_CRCERRS\t0x04000 /* CRC Error Count - R/clr */\n+#define IGC_ALGNERRC\t0x04004 /* Alignment Error Count - R/clr */\n+#define IGC_SYMERRS\t0x04008 /* Symbol Error Count - R/clr */\n+#define IGC_RXERRC\t0x0400C /* Receive Error Count - R/clr */\n+#define IGC_MPC\t\t0x04010 /* Missed Packet Count - R/clr */\n+#define IGC_SCC\t\t0x04014 /* Single Collision Count - R/clr */\n+#define IGC_ECOL\t0x04018 /* Excessive Collision Count - R/clr */\n+#define IGC_MCC\t\t0x0401C /* Multiple Collision Count - R/clr */\n+#define IGC_LATECOL\t0x04020 /* Late Collision Count - R/clr */\n+#define IGC_COLC\t0x04028 /* Collision Count - R/clr */\n+#define IGC_DC\t\t0x04030 /* Defer Count - R/clr */\n+#define IGC_TNCRS\t0x04034 /* Tx-No CRS - R/clr */\n+#define IGC_SEC\t\t0x04038 /* Sequence Error Count - R/clr */\n+#define IGC_CEXTERR\t0x0403C /* Carrier Extension Error Count - R/clr */\n+#define IGC_RLEC\t0x04040 /* Receive Length Error Count - R/clr */\n+#define IGC_XONRXC\t0x04048 /* XON Rx Count - R/clr */\n+#define IGC_XONTXC\t0x0404C /* XON Tx Count - R/clr */\n+#define IGC_XOFFRXC\t0x04050 /* XOFF Rx Count - R/clr */\n+#define IGC_XOFFTXC\t0x04054 /* XOFF Tx Count - R/clr */\n+#define IGC_FCRUC\t0x04058 /* Flow Control Rx Unsupported Count- R/clr */\n+#define IGC_PRC64\t0x0405C /* Packets Rx (64 bytes) - R/clr */\n+#define IGC_PRC127\t0x04060 /* Packets Rx (65-127 bytes) - R/clr */\n+#define IGC_PRC255\t0x04064 /* Packets Rx (128-255 bytes) - R/clr */\n+#define IGC_PRC511\t0x04068 /* Packets Rx (255-511 bytes) - R/clr */\n+#define IGC_PRC1023\t0x0406C /* Packets Rx (512-1023 bytes) - R/clr */\n+#define IGC_PRC1522\t0x04070 /* Packets Rx (1024-1522 bytes) - R/clr */\n+#define IGC_GPRC\t0x04074 /* Good Packets Rx Count - R/clr */\n+#define IGC_BPRC\t0x04078 /* Broadcast Packets Rx Count - R/clr */\n+#define IGC_MPRC\t0x0407C /* Multicast Packets Rx Count - R/clr */\n+#define IGC_GPTC\t0x04080 /* Good Packets Tx Count - R/clr */\n+#define IGC_GORCL\t0x04088 /* Good Octets Rx Count Low - R/clr */\n+#define IGC_GORCH\t0x0408C /* Good Octets Rx Count High - R/clr */\n+#define IGC_GOTCL\t0x04090 /* Good Octets Tx Count Low - R/clr */\n+#define IGC_GOTCH\t0x04094 /* Good Octets Tx Count High - R/clr */\n+#define IGC_RNBC\t0x040A0 /* Rx No Buffers Count - R/clr */\n+#define IGC_RUC\t\t0x040A4 /* Rx Undersize Count - R/clr */\n+#define IGC_RFC\t\t0x040A8 /* Rx Fragment Count - R/clr */\n+#define IGC_ROC\t\t0x040AC /* Rx Oversize Count - R/clr */\n+#define IGC_RJC\t\t0x040B0 /* Rx Jabber Count - R/clr */\n+#define IGC_MGTPRC\t0x040B4 /* Management Packets Rx Count - R/clr */\n+#define IGC_MGTPDC\t0x040B8 /* Management Packets Dropped Count - R/clr */\n+#define IGC_MGTPTC\t0x040BC /* Management Packets Tx Count - R/clr */\n+#define IGC_TORL\t0x040C0 /* Total Octets Rx Low - R/clr */\n+#define IGC_TORH\t0x040C4 /* Total Octets Rx High - R/clr */\n+#define IGC_TOTL\t0x040C8 /* Total Octets Tx Low - R/clr */\n+#define IGC_TOTH\t0x040CC /* Total Octets Tx High - R/clr */\n+#define IGC_TPR\t\t0x040D0 /* Total Packets Rx - R/clr */\n+#define IGC_TPT\t\t0x040D4 /* Total Packets Tx - R/clr */\n+#define IGC_PTC64\t0x040D8 /* Packets Tx (64 bytes) - R/clr */\n+#define IGC_PTC127\t0x040DC /* Packets Tx (65-127 bytes) - R/clr */\n+#define IGC_PTC255\t0x040E0 /* Packets Tx (128-255 bytes) - R/clr */\n+#define IGC_PTC511\t0x040E4 /* Packets Tx (256-511 bytes) - R/clr */\n+#define IGC_PTC1023\t0x040E8 /* Packets Tx (512-1023 bytes) - R/clr */\n+#define IGC_PTC1522\t0x040EC /* Packets Tx (1024-1522 Bytes) - R/clr */\n+#define IGC_MPTC\t0x040F0 /* Multicast Packets Tx Count - R/clr */\n+#define IGC_BPTC\t0x040F4 /* Broadcast Packets Tx Count - R/clr */\n+#define IGC_TSCTC\t0x040F8 /* TCP Segmentation Context Tx - R/clr */\n+#define IGC_TSCTFC\t0x040FC /* TCP Segmentation Context Tx Fail - R/clr */\n+#define IGC_IAC\t\t0x04100 /* Interrupt Assertion Count */\n+#define IGC_ICTXPTC\t0x0410C /* Interrupt Cause Tx Pkt Timer Expire Count */\n+#define IGC_ICTXATC\t0x04110 /* Interrupt Cause Tx Abs Timer Expire Count */\n+#define IGC_ICTXQEC\t0x04118 /* Interrupt Cause Tx Queue Empty Count */\n+#define IGC_ICTXQMTC\t0x0411C /* Interrupt Cause Tx Queue Min Thresh Count */\n+#define IGC_RPTHC\t0x04104 /* Rx Packets To Host */\n+#define IGC_HGPTC\t0x04118 /* Host Good Packets Tx Count */\n+#define IGC_RXDMTC\t0x04120 /* Rx Descriptor Minimum Threshold Count */\n+#define IGC_HGORCL\t0x04128 /* Host Good Octets Received Count Low */\n+#define IGC_HGORCH\t0x0412C /* Host Good Octets Received Count High */\n+#define IGC_HGOTCL\t0x04130 /* Host Good Octets Transmit Count Low */\n+#define IGC_HGOTCH\t0x04134 /* Host Good Octets Transmit Count High */\n+#define IGC_LENERRS\t0x04138 /* Length Errors Count */\n+#define IGC_SCVPC\t0x04228 /* SerDes/SGMII Code Violation Pkt Count */\n+#define IGC_HRMPC\t0x0A018 /* Header Redirection Missed Packet Count */\n+\n+/* forward declaration */\n+struct igc_hw;\n+u32 igc_rd32(struct igc_hw *hw, u32 reg);\n+\n+/* write operations, indexed using DWORDS */\n+#define wr32(reg, val) \\\n+do { \\\n+\tu8 __iomem *hw_addr = READ_ONCE((hw)->hw_addr); \\\n+\tif (!IGC_REMOVED(hw_addr)) \\\n+\t\twritel((val), &hw_addr[(reg)]); \\\n+} while (0)\n+\n+#define rd32(reg) (igc_rd32(hw, reg))\n+\n+#define wrfl() ((void)rd32(IGC_STATUS))\n+\n+#define array_wr32(reg, offset, value) \\\n+\twr32((reg) + ((offset) << 2), (value))\n+\n+#define array_rd32(reg, offset) (igc_rd32(hw, (reg) + ((offset) << 2)))\n+\n+#endif\n", "prefixes": [ "v7", "02/11" ] }