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GET /api/patches/956011/?format=api
{ "id": 956011, "url": "http://patchwork.ozlabs.org/api/patches/956011/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20180810060711.6547-38-jagan@amarulasolutions.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20180810060711.6547-38-jagan@amarulasolutions.com>", "list_archive_url": null, "date": "2018-08-10T06:06:55", "name": "[U-Boot,v2,37/53] clk: sunxi: Implement SPI clocks", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "8e577131ee7ab82fa5d40c12d3c92a1356ed413d", "submitter": { "id": 69820, "url": "http://patchwork.ozlabs.org/api/people/69820/?format=api", "name": "Jagan Teki", "email": "jagan@amarulasolutions.com" }, "delegate": { "id": 17739, "url": "http://patchwork.ozlabs.org/api/users/17739/?format=api", "username": "jagan", "first_name": "Jagannadha Sutradharudu", "last_name": "Teki", "email": "jagannadh.teki@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20180810060711.6547-38-jagan@amarulasolutions.com/mbox/", "series": [ { "id": 60190, "url": "http://patchwork.ozlabs.org/api/series/60190/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=60190", "date": "2018-08-10T06:06:18", "name": "clk: Add Allwinner CLK, RESET support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/60190/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/956011/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/956011/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=amarulasolutions.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=amarulasolutions.com\n\theader.i=@amarulasolutions.com header.b=\"pk/IacpP\"; \n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 41mwck2F7gz9s4Z\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 10 Aug 2018 16:45:58 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 13097C21E89; Fri, 10 Aug 2018 06:29:35 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id A8851C21E76;\n\tFri, 10 Aug 2018 06:19:00 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s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=W/8clBWkABhqmne61nvD7p1/HUjSzGdi57woQwPfvoY=;\n\tb=Ek9eF6/ScoVGDChH09Zaoqqt94FfoBErYCXOFnrqtm7RVbpvjZ6LGO/doxnb8MG678\n\tfE9Ofh/ciRghCiMPydg1yX4AmnDFxw1OqfaYp8UTEAoMwv2+6SaII+925TYAYMvfk3uy\n\tHRWQUFX686R+XRP7hJfLvDmfn7Dmv/HH9VEWMIwkUxhGFxZlGZ+nKreMQefvSNH3E/rQ\n\tbuTkCl34EI/vdOCcQw9e5JFhMDDTkz69/GsRD0ndWRfHOFoTDUuNHzjN8JwQNkgJ/Gof\n\tmsjqI8jCoZjnBmyFFbqGYkbhMU75OFJU5pWQlcDeV5E4mxxfyTdgcC7k2u6Bub3vbogV\n\tMqGA==", "X-Gm-Message-State": "AOUpUlGZsiHIaeLVX0VwLL/vGyQERT7UesJXDVWxZuim10etcM4ZPwx/\n\t5KcQfBSXCzAeLtB3dcLxT02STg==", "X-Google-Smtp-Source": "AA+uWPyOT5y0ie3HV3racOwqTzmG5YAuWocfsAc3lZpG4MaIhOsu4ZT3l85X/X4HHQb3DKBo5+2Wkg==", "X-Received": "by 2002:a62:4ece:: with SMTP id\n\tc197-v6mr5630478pfb.240.1533881399245; \n\tThu, 09 Aug 2018 23:09:59 -0700 (PDT)", "From": "Jagan Teki <jagan@amarulasolutions.com>", "To": "Maxime Ripard <maxime.ripard@bootlin.com>,\n\tAndre Przywara <andre.przywara@arm.com>, Chen-Yu Tsai <wens@csie.org>,\n\tIcenowy Zheng <icenowy@aosc.io>", "Date": "Fri, 10 Aug 2018 11:36:55 +0530", "Message-Id": "<20180810060711.6547-38-jagan@amarulasolutions.com>", "X-Mailer": "git-send-email 2.18.0.321.gffc6fa0e3", "In-Reply-To": "<20180810060711.6547-1-jagan@amarulasolutions.com>", "References": "<20180810060711.6547-1-jagan@amarulasolutions.com>", "MIME-Version": "1.0", "Cc": "Tom Rini <trini@konsulko.com>, u-boot@lists.denx.de", "Subject": "[U-Boot] [PATCH v2 37/53] clk: sunxi: Implement SPI clocks", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Implement SPI AHB and MOD clocks for all Allwinner SoC\nclock drivers via clock map descriptor table.\n\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\n---\n drivers/clk/sunxi/clk_a10.c | 9 +++++++++\n drivers/clk/sunxi/clk_a10s.c | 7 +++++++\n drivers/clk/sunxi/clk_a31.c | 9 +++++++++\n drivers/clk/sunxi/clk_a64.c | 5 +++++\n drivers/clk/sunxi/clk_h3.c | 5 +++++\n drivers/clk/sunxi/clk_v3s.c | 3 +++\n 6 files changed, 38 insertions(+)", "diff": "diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c\nindex 55176bc174..ee499c402a 100644\n--- a/drivers/clk/sunxi/clk_a10.c\n+++ b/drivers/clk/sunxi/clk_a10.c\n@@ -22,12 +22,21 @@ static struct ccu_clk_map a10_clks[] = {\n \t[CLK_AHB_MMC1]\t\t= { 0x060, BIT(9), NULL },\n \t[CLK_AHB_MMC2]\t\t= { 0x060, BIT(10), NULL },\n \t[CLK_AHB_MMC3]\t\t= { 0x060, BIT(11), NULL },\n+\t[CLK_AHB_SPI0]\t\t= { 0x060, BIT(20), NULL },\n+\t[CLK_AHB_SPI1]\t\t= { 0x060, BIT(21), NULL },\n+\t[CLK_AHB_SPI2]\t\t= { 0x060, BIT(22), NULL },\n+\t[CLK_AHB_SPI3]\t\t= { 0x060, BIT(23), NULL },\n \n \t[CLK_MMC0]\t\t= { 0x088, BIT(31), &mmc_clk_set_rate },\n \t[CLK_MMC1]\t\t= { 0x08c, BIT(31), &mmc_clk_set_rate },\n \t[CLK_MMC2]\t\t= { 0x090, BIT(31), &mmc_clk_set_rate },\n \t[CLK_MMC3]\t\t= { 0x094, BIT(31), &mmc_clk_set_rate },\n \n+\t[CLK_SPI0]\t\t= { 0x0a0, BIT(31), NULL },\n+\t[CLK_SPI1]\t\t= { 0x0a4, BIT(31), NULL },\n+\t[CLK_SPI2]\t\t= { 0x0a8, BIT(31), NULL },\n+\t[CLK_SPI3]\t\t= { 0x0d4, BIT(31), NULL },\n+\n \t[CLK_USB_OHCI0]\t\t= { 0x0cc, BIT(6), NULL },\n \t[CLK_USB_OHCI1]\t\t= { 0x0cc, BIT(7), NULL },\n \t[CLK_USB_PHY]\t\t= { 0x0cc, BIT(8), NULL },\ndiff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c\nindex fbac0ad751..bca248f59f 100644\n--- a/drivers/clk/sunxi/clk_a10s.c\n+++ b/drivers/clk/sunxi/clk_a10s.c\n@@ -19,6 +19,9 @@ static struct ccu_clk_map a10s_clks[] = {\n \t[CLK_AHB_MMC0]\t\t= { 0x060, BIT(8), NULL },\n \t[CLK_AHB_MMC1]\t\t= { 0x060, BIT(9), NULL },\n \t[CLK_AHB_MMC2]\t\t= { 0x060, BIT(10), NULL },\n+\t[CLK_AHB_SPI0]\t\t= { 0x060, BIT(20), NULL },\n+\t[CLK_AHB_SPI1]\t\t= { 0x060, BIT(21), NULL },\n+\t[CLK_AHB_SPI2]\t\t= { 0x060, BIT(22), NULL },\n \n #ifdef CONFIG_MMC\n \t[CLK_MMC0]\t\t= { 0x088, BIT(31), &mmc_clk_set_rate },\n@@ -26,6 +29,10 @@ static struct ccu_clk_map a10s_clks[] = {\n \t[CLK_MMC2]\t\t= { 0x090, BIT(31), &mmc_clk_set_rate },\n #endif\n \n+\t[CLK_SPI0]\t\t= { 0x0a0, BIT(31), NULL },\n+\t[CLK_SPI1]\t\t= { 0x0a4, BIT(31), NULL },\n+\t[CLK_SPI2]\t\t= { 0x0a8, BIT(31), NULL },\n+\n \t[CLK_USB_OHCI]\t\t= { 0x0cc, BIT(6), NULL },\n \t[CLK_USB_PHY0]\t\t= { 0x0cc, BIT(8), NULL },\n \t[CLK_USB_PHY1]\t\t= { 0x0cc, BIT(9), NULL },\ndiff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c\nindex 15076d0e72..1fa77e1272 100644\n--- a/drivers/clk/sunxi/clk_a31.c\n+++ b/drivers/clk/sunxi/clk_a31.c\n@@ -17,6 +17,10 @@ static struct ccu_clk_map a31_clks[] = {\n \t[CLK_AHB1_MMC1]\t\t= { 0x060, BIT(9), NULL },\n \t[CLK_AHB1_MMC2]\t\t= { 0x060, BIT(10), NULL },\n \t[CLK_AHB1_MMC3]\t\t= { 0x060, BIT(12), NULL },\n+\t[CLK_AHB1_SPI0]\t\t= { 0x060, BIT(20), NULL },\n+\t[CLK_AHB1_SPI1]\t\t= { 0x060, BIT(21), NULL },\n+\t[CLK_AHB1_SPI2]\t\t= { 0x060, BIT(22), NULL },\n+\t[CLK_AHB1_SPI3]\t\t= { 0x060, BIT(23), NULL },\n \t[CLK_AHB1_OTG]\t\t= { 0x060, BIT(24), NULL },\n \t[CLK_AHB1_EHCI0]\t= { 0x060, BIT(26), NULL },\n \t[CLK_AHB1_EHCI1]\t= { 0x060, BIT(27), NULL },\n@@ -29,6 +33,11 @@ static struct ccu_clk_map a31_clks[] = {\n \t[CLK_MMC2]\t\t= { 0x090, BIT(31), &mmc_clk_set_rate },\n \t[CLK_MMC3]\t\t= { 0x094, BIT(31), &mmc_clk_set_rate },\n \n+\t[CLK_SPI0]\t\t= { 0x0a0, BIT(31), NULL },\n+\t[CLK_SPI1]\t\t= { 0x0a4, BIT(31), NULL },\n+\t[CLK_SPI2]\t\t= { 0x0a8, BIT(31), NULL },\n+\t[CLK_SPI3]\t\t= { 0x0ac, BIT(31), NULL },\n+\n \t[CLK_USB_PHY0]\t\t= { 0x0cc, BIT(8), NULL },\n \t[CLK_USB_PHY1]\t\t= { 0x0cc, BIT(9), NULL },\n \t[CLK_USB_PHY2]\t\t= { 0x0cc, BIT(10), NULL },\ndiff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c\nindex 9ef9b606d2..aa2e69d0a3 100644\n--- a/drivers/clk/sunxi/clk_a64.c\n+++ b/drivers/clk/sunxi/clk_a64.c\n@@ -16,6 +16,8 @@ static struct ccu_clk_map a64_clks[] = {\n \t[CLK_BUS_MMC0]\t\t= { 0x060, BIT(8), NULL },\n \t[CLK_BUS_MMC1]\t\t= { 0x060, BIT(9), NULL },\n \t[CLK_BUS_MMC2]\t\t= { 0x060, BIT(10), NULL },\n+\t[CLK_BUS_SPI0]\t\t= { 0x060, BIT(20), NULL },\n+\t[CLK_BUS_SPI1]\t\t= { 0x060, BIT(21), NULL },\n \t[CLK_BUS_OTG]\t\t= { 0x060, BIT(23), NULL },\n \t[CLK_BUS_EHCI0]\t\t= { 0x060, BIT(24), NULL },\n \t[CLK_BUS_EHCI1]\t\t= { 0x060, BIT(25), NULL },\n@@ -26,6 +28,9 @@ static struct ccu_clk_map a64_clks[] = {\n \t[CLK_MMC1]\t\t= { 0x08c, BIT(31), &mmc_clk_set_rate },\n \t[CLK_MMC2]\t\t= { 0x090, BIT(31), &mmc_clk_set_rate },\n \n+\t[CLK_SPI0]\t\t= { 0x0a0, BIT(31), NULL },\n+\t[CLK_SPI1]\t\t= { 0x0a4, BIT(31), NULL },\n+\n \t[CLK_USB_PHY0]\t\t= { 0x0cc, BIT(8), NULL },\n \t[CLK_USB_PHY1]\t\t= { 0x0cc, BIT(9), NULL },\n \t[CLK_USB_HSIC]\t\t= { 0x0cc, BIT(10), NULL },\ndiff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c\nindex ad15aaae67..386289b654 100644\n--- a/drivers/clk/sunxi/clk_h3.c\n+++ b/drivers/clk/sunxi/clk_h3.c\n@@ -16,6 +16,8 @@ static struct ccu_clk_map h3_clks[] = {\n \t[CLK_BUS_MMC0]\t\t= { 0x060, BIT(8), NULL },\n \t[CLK_BUS_MMC1]\t\t= { 0x060, BIT(9), NULL },\n \t[CLK_BUS_MMC2]\t\t= { 0x060, BIT(10), NULL },\n+\t[CLK_BUS_SPI0]\t\t= { 0x060, BIT(20), NULL },\n+\t[CLK_BUS_SPI1]\t\t= { 0x060, BIT(21), NULL },\n \t[CLK_BUS_OTG]\t\t= { 0x060, BIT(23), NULL },\n \t[CLK_BUS_EHCI0]\t\t= { 0x060, BIT(24), NULL },\n \t[CLK_BUS_EHCI1]\t\t= { 0x060, BIT(25), NULL },\n@@ -30,6 +32,9 @@ static struct ccu_clk_map h3_clks[] = {\n \t[CLK_MMC1]\t\t= { 0x08c, BIT(31), &mmc_clk_set_rate },\n \t[CLK_MMC2]\t\t= { 0x090, BIT(31), &mmc_clk_set_rate },\n \n+\t[CLK_SPI0]\t\t= { 0x0a0, BIT(31), NULL },\n+\t[CLK_SPI1]\t\t= { 0x0a4, BIT(31), NULL },\n+\n \t[CLK_USB_PHY0]\t\t= { 0x0cc, BIT(8), NULL },\n \t[CLK_USB_PHY1]\t\t= { 0x0cc, BIT(9), NULL },\n \t[CLK_USB_PHY2]\t\t= { 0x0cc, BIT(10), NULL },\ndiff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c\nindex 6eeec201a2..1cca57e065 100644\n--- a/drivers/clk/sunxi/clk_v3s.c\n+++ b/drivers/clk/sunxi/clk_v3s.c\n@@ -16,12 +16,15 @@ static struct ccu_clk_map v3s_clks[] = {\n \t[CLK_BUS_MMC0]\t\t= { 0x060, BIT(8), NULL },\n \t[CLK_BUS_MMC1]\t\t= { 0x060, BIT(9), NULL },\n \t[CLK_BUS_MMC2]\t\t= { 0x060, BIT(10), NULL },\n+\t[CLK_BUS_SPI0]\t\t= { 0x060, BIT(20), NULL },\n \t[CLK_BUS_OTG]\t\t= { 0x060, BIT(24), NULL },\n \n \t[CLK_MMC0]\t\t= { 0x088, BIT(31), &mmc_clk_set_rate },\n \t[CLK_MMC1]\t\t= { 0x08c, BIT(31), &mmc_clk_set_rate },\n \t[CLK_MMC2]\t\t= { 0x090, BIT(31), &mmc_clk_set_rate },\n \n+\t[CLK_SPI0]\t\t= { 0x0a0, BIT(31), NULL },\n+\n \t[CLK_USB_PHY0] = { 0x0cc, BIT(8), NULL },\n };\n \n", "prefixes": [ "U-Boot", "v2", "37/53" ] }