Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/956005/?format=api
{ "id": 956005, "url": "http://patchwork.ozlabs.org/api/patches/956005/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20180810060711.6547-48-jagan@amarulasolutions.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20180810060711.6547-48-jagan@amarulasolutions.com>", "list_archive_url": null, "date": "2018-08-10T06:07:05", "name": "[U-Boot,v2,47/53] net: sun8i_emac: Add CLK and RESET support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "e016c8e33f25f41690e1570d9271baab8ecaaa74", "submitter": { "id": 69820, "url": "http://patchwork.ozlabs.org/api/people/69820/?format=api", "name": "Jagan Teki", "email": "jagan@amarulasolutions.com" }, "delegate": { "id": 17739, "url": "http://patchwork.ozlabs.org/api/users/17739/?format=api", "username": "jagan", "first_name": "Jagannadha Sutradharudu", "last_name": "Teki", "email": "jagannadh.teki@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20180810060711.6547-48-jagan@amarulasolutions.com/mbox/", "series": [ { "id": 60190, "url": "http://patchwork.ozlabs.org/api/series/60190/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=60190", "date": "2018-08-10T06:06:18", "name": "clk: Add Allwinner CLK, RESET support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/60190/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/956005/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/956005/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=amarulasolutions.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=amarulasolutions.com\n\theader.i=@amarulasolutions.com header.b=\"NFhacBSV\"; \n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 41mwWt6ccFz9s4Z\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 10 Aug 2018 16:41:46 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 8F44CC21E26; Fri, 10 Aug 2018 06:21:41 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 32DC0C21E12;\n\tFri, 10 Aug 2018 06:11:59 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid EAD2EC21E12; Fri, 10 Aug 2018 06:10:52 +0000 (UTC)", "from mail-pg1-f195.google.com (mail-pg1-f195.google.com\n\t[209.85.215.195])\n\tby lists.denx.de (Postfix) with ESMTPS id D984BC21EB1\n\tfor <u-boot@lists.denx.de>; Fri, 10 Aug 2018 06:10:40 +0000 (UTC)", "by mail-pg1-f195.google.com with SMTP id y5-v6so3903027pgv.1\n\tfor <u-boot@lists.denx.de>; Thu, 09 Aug 2018 23:10:40 -0700 (PDT)", "from localhost.localdomain ([183.82.228.250])\n\tby smtp.gmail.com with ESMTPSA id\n\tr23-v6sm16880975pfj.5.2018.08.09.23.10.35\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tThu, 09 Aug 2018 23:10:39 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no\n\tversion=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=amarulasolutions.com; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=DLZx4iGCNcW3Z3z4nZOIMqyis58Sk7qxVT/tdhjTpJw=;\n\tb=NFhacBSVlIfCfCSiFhM+bEvF0WgdWduksL0QFXc5QdGDqKhMvlWpUq49+rCPHChUF6\n\tcbah/B74QwFXbhQLH7H18NkYF5Whtt2ugOeFaid3y+SbIVj5AoRcUOBFL1xlmV3suzN1\n\tUrV06ztmIrl8FRXeuy7JI4L50sRcZgZ6G0vgU=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=DLZx4iGCNcW3Z3z4nZOIMqyis58Sk7qxVT/tdhjTpJw=;\n\tb=P2OVft5l3AFdhoJB0M3wtXx7+ChkIOqyfYPOh7PHbGfpfswnW0c8oXz13R8d4KpzCw\n\tT+JI27jM30JB70cbKvp6cGXTUeIvJ1c3xj7JmhzATNeU2Cf33iND0bcQQZlMVuSzzXDk\n\t2Cv/V91RD58DcxT8apiGCh8zNmlSLrvj1/23mT7bWZRSgtjg3TR1OSk6Eo10ITnFcHsE\n\tsSoYr4uieB6SYxqa/7b12qbrduR4+XPnAPRQOgeoIxwSstGYL0IqJ2dFZr1eOFrrIeG8\n\tPbkslmp3LcIjsOcgVijcEQRocvYugJ9iLfR2AZaxK97i/CdazxDDeZVHRJx8l3DFtJHq\n\t9rcw==", "X-Gm-Message-State": "AOUpUlENDXHpdqb1OR2RGwHkm7GaAzpHN3yOYFvNNVbhcKSQ5+6BEu2X\n\tLKdTZiInkFaZngqObj3trhCRA8h2DQg=", "X-Google-Smtp-Source": "AA+uWPyYQa60+I2ke63l9SCJHV5PPM7BJbehoswB8IzMXJz5Rs56A9+zdPnyldR01nrypsyudW6sLg==", "X-Received": "by 2002:a63:2013:: with SMTP id\n\tg19-v6mr5071230pgg.68.1533881439479; \n\tThu, 09 Aug 2018 23:10:39 -0700 (PDT)", "From": "Jagan Teki <jagan@amarulasolutions.com>", "To": "Maxime Ripard <maxime.ripard@bootlin.com>,\n\tAndre Przywara <andre.przywara@arm.com>, Chen-Yu Tsai <wens@csie.org>,\n\tIcenowy Zheng <icenowy@aosc.io>", "Date": "Fri, 10 Aug 2018 11:37:05 +0530", "Message-Id": "<20180810060711.6547-48-jagan@amarulasolutions.com>", "X-Mailer": "git-send-email 2.18.0.321.gffc6fa0e3", "In-Reply-To": "<20180810060711.6547-1-jagan@amarulasolutions.com>", "References": "<20180810060711.6547-1-jagan@amarulasolutions.com>", "MIME-Version": "1.0", "Cc": "Tom Rini <trini@konsulko.com>, u-boot@lists.denx.de,\n\tJoe Hershberger <joe.hershberger@ni.com>", "Subject": "[U-Boot] [PATCH v2 47/53] net: sun8i_emac: Add CLK and RESET support", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Add CLK and RESET support for sun8i_emac driver to\nenable TX clock and reset pins via CLK and RESET\nframework.\n\nCc: Joe Hershberger <joe.hershberger@ni.com>\nCc: Lothar Felten <lothar.felten@gmail.com>\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\n---\n drivers/net/sun8i_emac.c | 56 ++++++++++++++++++++++++++++------------\n 1 file changed, 40 insertions(+), 16 deletions(-)", "diff": "diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c\nindex 5ee4c2f993..ad2d390f4e 100644\n--- a/drivers/net/sun8i_emac.c\n+++ b/drivers/net/sun8i_emac.c\n@@ -10,6 +10,7 @@\n *\n */\n \n+#include <clk.h>\n #include <asm/io.h>\n #include <asm/arch/clock.h>\n #include <asm/arch/gpio.h>\n@@ -20,6 +21,7 @@\n #include <malloc.h>\n #include <miiphy.h>\n #include <net.h>\n+#include <reset.h>\n #include <dt-bindings/pinctrl/sun4i-a10.h>\n #ifdef CONFIG_DM_GPIO\n #include <asm-generic/gpio.h>\n@@ -131,6 +133,8 @@ struct emac_eth_dev {\n \tphys_addr_t sysctl_reg;\n \tstruct phy_device *phydev;\n \tstruct mii_dev *bus;\n+\tstruct clk tx_clk;\n+\tstruct reset_ctl tx_rst;\n #ifdef CONFIG_DM_GPIO\n \tstruct gpio_desc reset_gpio;\n #endif\n@@ -632,9 +636,24 @@ static int sun8i_eth_write_hwaddr(struct udevice *dev)\n \treturn _sun8i_write_hwaddr(priv, pdata->enetaddr);\n }\n \n-static void sun8i_emac_board_setup(struct emac_eth_dev *priv)\n+static int sun8i_emac_board_setup(struct emac_eth_dev *priv)\n {\n \tstruct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;\n+\tint ret;\n+\n+\tret = clk_enable(&priv->tx_clk);\n+\tif (ret) {\n+\t\tdev_err(dev, \"failed to enable TX clock\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tif (reset_valid(&priv->tx_rst)) {\n+\t\tret = reset_deassert(&priv->tx_rst);\n+\t\tif (ret) {\n+\t\t\tdev_err(dev, \"failed to deassert TX reset\\n\");\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n \n \tif (priv->variant == H3_EMAC) {\n \t\t/* Only H3/H5 have clock controls for internal EPHY */\n@@ -649,19 +668,7 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv)\n \t\t}\n \t}\n \n-\tif (priv->variant == R40_GMAC) {\n-\t\t/* Set clock gating for emac */\n-\t\tsetbits_le32(&ccm->ahb_reset1_cfg, BIT(AHB_RESET_OFFSET_GMAC));\n-\n-\t\t/* De-assert EMAC */\n-\t\tsetbits_le32(&ccm->ahb_gate1, BIT(AHB_GATE_OFFSET_GMAC));\n-\t} else {\n-\t\t/* Set clock gating for emac */\n-\t\tsetbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));\n-\n-\t\t/* De-assert EMAC */\n-\t\tsetbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC));\n-\t}\n+\treturn 0;\n }\n \n #if defined(CONFIG_DM_GPIO)\n@@ -787,10 +794,14 @@ static int sun8i_emac_eth_probe(struct udevice *dev)\n {\n \tstruct eth_pdata *pdata = dev_get_platdata(dev);\n \tstruct emac_eth_dev *priv = dev_get_priv(dev);\n+\tint ret;\n \n \tpriv->mac_reg = (void *)pdata->iobase;\n \n-\tsun8i_emac_board_setup(priv);\n+\tret = sun8i_emac_board_setup(priv);\n+\tif (ret)\n+\t\treturn ret;\n+\n \tsun8i_emac_set_syscon(priv);\n \n \tsun8i_mdio_init(dev->name, dev);\n@@ -819,8 +830,8 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)\n \tint offset = 0;\n #ifdef CONFIG_DM_GPIO\n \tint reset_flags = GPIOD_IS_OUT;\n-\tint ret = 0;\n #endif\n+\tint ret;\n \n \tpdata->iobase = devfdt_get_addr(dev);\n \tif (pdata->iobase == FDT_ADDR_T_NONE) {\n@@ -835,6 +846,19 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)\n \t\treturn -EINVAL;\n \t}\n \n+\tret = clk_get_by_name(dev, \"stmmaceth\", &priv->tx_clk);\n+\tif (ret) {\n+\t\tdev_err(dev, \"failed to get TX clock\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tret = reset_get_by_name_optional(dev, \"stmmaceth\",\n+\t\t\t\t\t &priv->tx_rst, true);\n+\tif (ret) {\n+\t\tdev_err(dev, \"failed to get TX reset\\n\");\n+\t\treturn ret;\n+\t}\n+\n \toffset = fdtdec_lookup_phandle(gd->fdt_blob, node, \"syscon\");\n \tif (offset < 0) {\n \t\tdebug(\"%s: cannot find syscon node\\n\", __func__);\n", "prefixes": [ "U-Boot", "v2", "47/53" ] }