Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/955998/?format=api
{ "id": 955998, "url": "http://patchwork.ozlabs.org/api/patches/955998/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20180810060711.6547-17-jagan@amarulasolutions.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20180810060711.6547-17-jagan@amarulasolutions.com>", "list_archive_url": null, "date": "2018-08-10T06:06:34", "name": "[U-Boot,v2,16/53] phy: sun4i-usb: Use CLK and RESET support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "8e6d74764dfdf35b672f639565b593ffc9896e8d", "submitter": { "id": 69820, "url": "http://patchwork.ozlabs.org/api/people/69820/?format=api", "name": "Jagan Teki", "email": "jagan@amarulasolutions.com" }, "delegate": { "id": 17739, "url": "http://patchwork.ozlabs.org/api/users/17739/?format=api", "username": "jagan", "first_name": "Jagannadha Sutradharudu", "last_name": "Teki", "email": "jagannadh.teki@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20180810060711.6547-17-jagan@amarulasolutions.com/mbox/", "series": [ { "id": 60190, "url": "http://patchwork.ozlabs.org/api/series/60190/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=60190", "date": "2018-08-10T06:06:18", "name": "clk: Add Allwinner CLK, RESET support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/60190/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/955998/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/955998/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=amarulasolutions.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=amarulasolutions.com\n\theader.i=@amarulasolutions.com header.b=\"MDLUa3C4\"; \n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 41mwSm15s4z9s7Q\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 10 Aug 2018 16:39:04 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid D0D4CC21E42; Fri, 10 Aug 2018 06:22:22 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id E10CBC21E88;\n\tFri, 10 Aug 2018 06:12:19 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 6A74CC21C57; Fri, 10 Aug 2018 06:08:43 +0000 (UTC)", "from mail-pf1-f196.google.com (mail-pf1-f196.google.com\n\t[209.85.210.196])\n\tby lists.denx.de (Postfix) with ESMTPS id DD951C21E12\n\tfor <u-boot@lists.denx.de>; Fri, 10 Aug 2018 06:08:38 +0000 (UTC)", "by mail-pf1-f196.google.com with SMTP id a26-v6so4018389pfo.4\n\tfor <u-boot@lists.denx.de>; Thu, 09 Aug 2018 23:08:38 -0700 (PDT)", "from localhost.localdomain ([183.82.228.250])\n\tby smtp.gmail.com with ESMTPSA id\n\tr23-v6sm16880975pfj.5.2018.08.09.23.08.33\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tThu, 09 Aug 2018 23:08:36 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no\n\tversion=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=amarulasolutions.com; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=vE9WmEIiyHbsdC5w72COwECnW7iiMB1eNDJEk+MLI6M=;\n\tb=MDLUa3C4m12bEvOES2wuYz6h/ElyWwTRWHoIkHL+8+Sk/VMwGtqidOTgwR3lKLyhRD\n\t4R/lwlZ15nZAHckvW2YgZWmOW00P4GJcy1MemG87pWcuPET2z/z51eoPx/XzmrkvF80K\n\tctbOCotDa7G0LLVbeHJGoo6C1BYpvxdwz+FLI=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=vE9WmEIiyHbsdC5w72COwECnW7iiMB1eNDJEk+MLI6M=;\n\tb=jYoJUXcaM6oCHC4hHYITF0gBka7+Fme3uY/p23CjV97Zd4H0Ctf0u2+nI39L42DD88\n\tMIqA3Sibv54Tr2leMGRtw3TJDFyQosc2HKH/fD450vD7tyf0ZMr2LZnu7zHsyRDW90Xh\n\twLsdAUuycaS+WsCAuisBZ4LAUnrDt9bVw7osBYxQ+c6vp9Ucmdk26Mgmg+3EJSwnvjuF\n\tLyYGRPsK8G9i15nAovdUL8pBsoRNVlBnHpEFXerHSUfI9D9F/Lem5eAINP79i4DUkvu4\n\tZJ6wJXPT6bz/AjOKP82DL6joovPdWSAqz4rnZUfMo4doAbqzqyl6DDvqH+q44Dv00UZ5\n\t7xfw==", "X-Gm-Message-State": "AOUpUlF7m8vA/mv4c7V10XAcy0k7zVcMTS24YmuyilJ4NYVUQalM/qag\n\t9bu3bjUWBurAOaMEZqgIU1CPyw==", "X-Google-Smtp-Source": "AA+uWPwEXh8egTMmpcqsjHCgRAlFRqpZXvb0JWysQnfYJRJYiBeUx5G9Y7o8EgNkXSn+FwzxnDOzvw==", "X-Received": "by 2002:a63:5a5e:: with SMTP id\n\tk30-v6mr5103059pgm.123.1533881317449; \n\tThu, 09 Aug 2018 23:08:37 -0700 (PDT)", "From": "Jagan Teki <jagan@amarulasolutions.com>", "To": "Maxime Ripard <maxime.ripard@bootlin.com>,\n\tAndre Przywara <andre.przywara@arm.com>, Chen-Yu Tsai <wens@csie.org>,\n\tIcenowy Zheng <icenowy@aosc.io>", "Date": "Fri, 10 Aug 2018 11:36:34 +0530", "Message-Id": "<20180810060711.6547-17-jagan@amarulasolutions.com>", "X-Mailer": "git-send-email 2.18.0.321.gffc6fa0e3", "In-Reply-To": "<20180810060711.6547-1-jagan@amarulasolutions.com>", "References": "<20180810060711.6547-1-jagan@amarulasolutions.com>", "MIME-Version": "1.0", "Cc": "Tom Rini <trini@konsulko.com>, u-boot@lists.denx.de", "Subject": "[U-Boot] [PATCH v2 16/53] phy: sun4i-usb: Use CLK and RESET support", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Now clock and reset drivers are available for respective\nSoC's so use clk and reset ops on phy driver.\n\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\n---\n drivers/phy/allwinner/phy-sun4i-usb.c | 77 ++++++++++++++++++++-------\n 1 file changed, 57 insertions(+), 20 deletions(-)", "diff": "diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c\nindex a7d7e3f044..f206fa3f5d 100644\n--- a/drivers/phy/allwinner/phy-sun4i-usb.c\n+++ b/drivers/phy/allwinner/phy-sun4i-usb.c\n@@ -11,10 +11,12 @@\n */\n \n #include <common.h>\n+#include <clk.h>\n #include <dm.h>\n #include <dm/device.h>\n #include <generic-phy.h>\n #include <phy-sun4i-usb.h>\n+#include <reset.h>\n #include <asm/gpio.h>\n #include <asm/io.h>\n #include <asm/arch/clock.h>\n@@ -80,6 +82,7 @@ struct sun4i_usb_phy_cfg {\n \tenum sun4i_usb_phy_type type;\n \tu32 disc_thresh;\n \tu8 phyctl_offset;\n+\tbool dedicated_clocks;\n \tbool enable_pmu_unk1;\n \tbool phy0_dual_route;\n };\n@@ -88,30 +91,21 @@ struct sun4i_usb_phy_info {\n \tconst char *gpio_vbus;\n \tconst char *gpio_vbus_det;\n \tconst char *gpio_id_det;\n-\tint rst_mask;\n } phy_info[] = {\n \t{\n \t\t.gpio_vbus = CONFIG_USB0_VBUS_PIN,\n \t\t.gpio_vbus_det = CONFIG_USB0_VBUS_DET,\n \t\t.gpio_id_det = CONFIG_USB0_ID_DET,\n-\t\t.rst_mask = (CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK),\n \t},\n \t{\n \t\t.gpio_vbus = CONFIG_USB1_VBUS_PIN,\n \t\t.gpio_vbus_det = NULL,\n \t\t.gpio_id_det = NULL,\n-\t\t.rst_mask = (CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK),\n \t},\n \t{\n \t\t.gpio_vbus = CONFIG_USB2_VBUS_PIN,\n \t\t.gpio_vbus_det = NULL,\n \t\t.gpio_id_det = NULL,\n-#ifdef CONFIG_MACH_SUN8I_A83T\n-\t\t.rst_mask = (CCM_USB_CTRL_HSIC_RST | CCM_USB_CTRL_HSIC_CLK |\n-\t\t\t CCM_USB_CTRL_12M_CLK),\n-#else\n-\t\t.rst_mask = (CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK),\n-#endif\n \t},\n \t{\n \t\t.gpio_vbus = CONFIG_USB3_VBUS_PIN,\n@@ -126,13 +120,13 @@ struct sun4i_usb_phy_plat {\n \tint gpio_vbus;\n \tint gpio_vbus_det;\n \tint gpio_id_det;\n-\tint rst_mask;\n+\tstruct clk clocks;\n+\tstruct reset_ctl resets;\n \tint id;\n };\n \n struct sun4i_usb_phy_data {\n \tvoid __iomem *base;\n-\tstruct sunxi_ccm_reg *ccm;\n \tconst struct sun4i_usb_phy_cfg *cfg;\n \tstruct sun4i_usb_phy_plat *usb_phy;\n };\n@@ -266,8 +260,19 @@ static int sun4i_usb_phy_init(struct phy *phy)\n \tstruct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);\n \tstruct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];\n \tu32 val;\n+\tint ret;\n \n-\tsetbits_le32(&data->ccm->usb_clk_cfg, usb_phy->rst_mask);\n+\tret = clk_enable(&usb_phy->clocks);\n+\tif (ret) {\n+\t\tdev_err(dev, \"failed to enable usb_%ldphy clock\\n\", phy->id);\n+\t\treturn ret;\n+\t}\n+\n+\tret = reset_deassert(&usb_phy->resets);\n+\tif (ret) {\n+\t\tdev_err(dev, \"failed to deassert usb_%ldreset reset\\n\", phy->id);\n+\t\treturn ret;\n+\t}\n \n \tif (data->cfg->type == sun8i_a83t_phy) {\n \t\tif (phy->id == 0) {\n@@ -308,6 +313,7 @@ static int sun4i_usb_phy_exit(struct phy *phy)\n {\n \tstruct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);\n \tstruct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];\n+\tint ret;\n \n \tif (phy->id == 0) {\n \t\tif (data->cfg->type == sun8i_a83t_phy) {\n@@ -320,7 +326,17 @@ static int sun4i_usb_phy_exit(struct phy *phy)\n \n \tsun4i_usb_phy_passby(phy, false);\n \n-\tclrbits_le32(&data->ccm->usb_clk_cfg, usb_phy->rst_mask);\n+\tret = clk_disable(&usb_phy->clocks);\n+\tif (ret) {\n+\t\tdev_err(dev, \"failed to disable usb_%ldphy clock\\n\", phy->id);\n+\t\treturn ret;\n+\t}\n+\n+\tret = reset_assert(&usb_phy->resets);\n+\tif (ret) {\n+\t\tdev_err(dev, \"failed to assert usb_%ldreset reset\\n\", phy->id);\n+\t\treturn ret;\n+\t}\n \n \treturn 0;\n }\n@@ -407,10 +423,6 @@ static int sun4i_usb_phy_probe(struct udevice *dev)\n \tif (IS_ERR(data->base))\n \t\treturn PTR_ERR(data->base);\n \n-\tdata->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;\n-\tif (IS_ERR(data->ccm))\n-\t\treturn PTR_ERR(data->ccm);\n-\n \tdata->usb_phy = plat;\n \tfor (i = 0; i < data->cfg->num_phys; i++) {\n \t\tstruct sun4i_usb_phy_plat *phy = &plat[i];\n@@ -448,6 +460,24 @@ static int sun4i_usb_phy_probe(struct udevice *dev)\n \t\t\tsunxi_gpio_set_pull(phy->gpio_id_det, SUNXI_GPIO_PULL_UP);\n \t\t}\n \n+\t\tif (data->cfg->dedicated_clocks)\n+\t\t\tsnprintf(name, sizeof(name), \"usb%d_phy\", i);\n+\t\telse\n+\t\t\tstrlcpy(name, \"usb_phy\", sizeof(name));\n+\n+\t\tret = clk_get_by_name(dev, name, &phy->clocks);\n+\t\tif (ret) {\n+\t\t\tdev_err(dev, \"failed to get usb%d_phy clock phandle\\n\", i);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\tsnprintf(name, sizeof(name), \"usb%d_reset\", i);\n+\t\tret = reset_get_by_name(dev, name, &phy->resets);\n+\t\tif (ret) {\n+\t\t\tdev_err(dev, \"failed to get usb%d_reset reset phandle\\n\", i);\n+\t\t\treturn ret;\n+\t\t}\n+\n \t\tif (i || data->cfg->phy0_dual_route) {\n \t\t\tsnprintf(name, sizeof(name), \"pmu%d\", i);\n \t\t\tphy->pmu = (void __iomem *)devfdt_get_addr_name(dev, name);\n@@ -456,9 +486,6 @@ static int sun4i_usb_phy_probe(struct udevice *dev)\n \t\t}\n \n \t\tphy->id = i;\n-\t\tphy->rst_mask = info->rst_mask;\n-\t\tif ((data->cfg->type == sun8i_h3_phy) && (phy->id == 3))\n-\t\t\tphy->rst_mask = (BIT(3) | BIT(11));\n \t};\n \n \tdebug(\"Allwinner Sun4I USB PHY driver loaded\\n\");\n@@ -470,6 +497,7 @@ static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {\n \t.type = sun4i_a10_phy,\n \t.disc_thresh = 3,\n \t.phyctl_offset = REG_PHYCTL_A10,\n+\t.dedicated_clocks = false,\n \t.enable_pmu_unk1 = false,\n };\n \n@@ -478,6 +506,7 @@ static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {\n \t.type = sun4i_a10_phy,\n \t.disc_thresh = 2,\n \t.phyctl_offset = REG_PHYCTL_A10,\n+\t.dedicated_clocks = false,\n \t.enable_pmu_unk1 = false,\n };\n \n@@ -486,6 +515,7 @@ static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {\n \t.type = sun6i_a31_phy,\n \t.disc_thresh = 3,\n \t.phyctl_offset = REG_PHYCTL_A10,\n+\t.dedicated_clocks = true,\n \t.enable_pmu_unk1 = false,\n };\n \n@@ -494,6 +524,7 @@ static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {\n \t.type = sun4i_a10_phy,\n \t.disc_thresh = 2,\n \t.phyctl_offset = REG_PHYCTL_A10,\n+\t.dedicated_clocks = false,\n \t.enable_pmu_unk1 = false,\n };\n \n@@ -502,6 +533,7 @@ static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {\n \t.type = sun4i_a10_phy,\n \t.disc_thresh = 3,\n \t.phyctl_offset = REG_PHYCTL_A10,\n+\t.dedicated_clocks = true,\n \t.enable_pmu_unk1 = false,\n };\n \n@@ -510,6 +542,7 @@ static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {\n \t.type = sun8i_a33_phy,\n \t.disc_thresh = 3,\n \t.phyctl_offset = REG_PHYCTL_A33,\n+\t.dedicated_clocks = true,\n \t.enable_pmu_unk1 = false,\n };\n \n@@ -517,6 +550,7 @@ static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {\n \t.num_phys = 3,\n \t.type = sun8i_a83t_phy,\n \t.phyctl_offset = REG_PHYCTL_A33,\n+\t.dedicated_clocks = true,\n };\n \n static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {\n@@ -524,6 +558,7 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {\n \t.type = sun8i_h3_phy,\n \t.disc_thresh = 3,\n \t.phyctl_offset = REG_PHYCTL_A33,\n+\t.dedicated_clocks = true,\n \t.enable_pmu_unk1 = true,\n \t.phy0_dual_route = true,\n };\n@@ -533,6 +568,7 @@ static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {\n \t.type = sun8i_v3s_phy,\n \t.disc_thresh = 3,\n \t.phyctl_offset = REG_PHYCTL_A33,\n+\t.dedicated_clocks = true,\n \t.enable_pmu_unk1 = true,\n \t.phy0_dual_route = true,\n };\n@@ -542,6 +578,7 @@ static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {\n \t.type = sun50i_a64_phy,\n \t.disc_thresh = 3,\n \t.phyctl_offset = REG_PHYCTL_A33,\n+\t.dedicated_clocks = true,\n \t.enable_pmu_unk1 = true,\n \t.phy0_dual_route = true,\n };\n", "prefixes": [ "U-Boot", "v2", "16/53" ] }