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GET /api/patches/955993/?format=api
{ "id": 955993, "url": "http://patchwork.ozlabs.org/api/patches/955993/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20180810060711.6547-21-jagan@amarulasolutions.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20180810060711.6547-21-jagan@amarulasolutions.com>", "list_archive_url": null, "date": "2018-08-10T06:06:38", "name": "[U-Boot,v2,20/53] clk: sunxi: Implement direct MMC clocks", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "3dbefb4010c56b75bcea622590a70f9f513b7f28", "submitter": { "id": 69820, "url": "http://patchwork.ozlabs.org/api/people/69820/?format=api", "name": "Jagan Teki", "email": "jagan@amarulasolutions.com" }, "delegate": { "id": 17739, "url": "http://patchwork.ozlabs.org/api/users/17739/?format=api", "username": "jagan", "first_name": "Jagannadha Sutradharudu", "last_name": "Teki", "email": "jagannadh.teki@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20180810060711.6547-21-jagan@amarulasolutions.com/mbox/", "series": [ { "id": 60190, "url": "http://patchwork.ozlabs.org/api/series/60190/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=60190", "date": "2018-08-10T06:06:18", "name": "clk: Add Allwinner CLK, RESET support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/60190/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/955993/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/955993/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=amarulasolutions.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=amarulasolutions.com\n\theader.i=@amarulasolutions.com header.b=\"CcqM5cpU\"; \n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 41mwR25v0Fz9s7Q\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 10 Aug 2018 16:37:34 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 745E2C21DD9; Fri, 10 Aug 2018 06:20:37 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 55F07C21EBF;\n\tFri, 10 Aug 2018 06:10:45 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s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=kckSnLt/DulTI9dx/LawiM76vXZHL4U3acQ+ZtO0KEU=;\n\tb=iMeh2+NTyWfUeMJHxav8Ie8e5LS6MqXA+iiv0SxqmIeEeSEEhNmP0CJm5ehXN1XGQT\n\tmWcWMW/cR75xmOYXlVGah6hvmqfQ7z424zl9yVrNv6wsg70+/wvTwOWgMhW7RRzY6Qus\n\tn+PfIeg9sDbS8HaxL3JP6/fMHgk+X1udcVVarlV0MGhCFxeGKhuZNAO36hRalFPwrcjT\n\tjIiH/o3d4Zxo5l06N3lgVTaQ0JztsUWMew4xpGa33qvvSKNSJI2/sygpciw44zCH9uvo\n\tm63S+kifq2r+FVX70OjVEgFP1FyocS8C65bD5DEX/ZYrMZPQDMgHxwezSHxDSiyE5zXc\n\tV++Q==", "X-Gm-Message-State": "AOUpUlEtOxSZDPtfTQvBG8mP1nqZoFepN37R4M6Gim4MWzP5+nlLH7oZ\n\tnIDVzHmZXsEQAMptcX7+KE5gYQ==", "X-Google-Smtp-Source": "AA+uWPzU04lWUopKCL+rbVWg6d9RzsgEwmarBO3ZXShIJTk80MPppMnZ8fq0BzWJGJnzh0TkC0l5KA==", "X-Received": "by 2002:a63:b504:: with SMTP id\n\ty4-v6mr5097884pge.247.1533881333619; \n\tThu, 09 Aug 2018 23:08:53 -0700 (PDT)", "From": "Jagan Teki <jagan@amarulasolutions.com>", "To": "Maxime Ripard <maxime.ripard@bootlin.com>,\n\tAndre Przywara <andre.przywara@arm.com>, Chen-Yu Tsai <wens@csie.org>,\n\tIcenowy Zheng <icenowy@aosc.io>", "Date": "Fri, 10 Aug 2018 11:36:38 +0530", "Message-Id": "<20180810060711.6547-21-jagan@amarulasolutions.com>", "X-Mailer": "git-send-email 2.18.0.321.gffc6fa0e3", "In-Reply-To": "<20180810060711.6547-1-jagan@amarulasolutions.com>", "References": "<20180810060711.6547-1-jagan@amarulasolutions.com>", "MIME-Version": "1.0", "Cc": "Tom Rini <trini@konsulko.com>, u-boot@lists.denx.de", "Subject": "[U-Boot] [PATCH v2 20/53] clk: sunxi: Implement direct MMC clocks", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Implement direct MMC clocks for all Allwinner SoC\nclock drivers via clock map descriptor table.\n\nThis includes adding ccu_clk_set_rate function pointer,\nwhich indeed support CLK set_rate API, so update clock\nhandling in sunxi_mmc driver to support both no-dm and dm code.\n\nCc: Jaehoon Chung <jh80.chung@samsung.com>\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\n---\n arch/arm/include/asm/arch-sunxi/ccu.h | 10 +++++\n drivers/clk/sunxi/clk_a10.c | 5 +++\n drivers/clk/sunxi/clk_a10s.c | 6 +++\n drivers/clk/sunxi/clk_a23.c | 6 +++\n drivers/clk/sunxi/clk_a31.c | 5 +++\n drivers/clk/sunxi/clk_a64.c | 4 ++\n drivers/clk/sunxi/clk_a83t.c | 4 ++\n drivers/clk/sunxi/clk_h3.c | 4 ++\n drivers/clk/sunxi/clk_r40.c | 4 ++\n drivers/clk/sunxi/clk_sunxi.c | 19 +++++++++\n drivers/clk/sunxi/clk_v3s.c | 4 ++\n drivers/mmc/sunxi_mmc.c | 58 +++++++++++++++++----------\n 12 files changed, 107 insertions(+), 22 deletions(-)", "diff": "diff --git a/arch/arm/include/asm/arch-sunxi/ccu.h b/arch/arm/include/asm/arch-sunxi/ccu.h\nindex bacd052ef3..4e30ab330c 100644\n--- a/arch/arm/include/asm/arch-sunxi/ccu.h\n+++ b/arch/arm/include/asm/arch-sunxi/ccu.h\n@@ -60,6 +60,16 @@ struct sunxi_clk_priv {\n \n extern struct clk_ops sunxi_clk_ops;\n \n+/**\n+ * mmc_clk_set_rate - mmc clock set rate\n+ *\n+ * @base:\tclock register base address\n+ * @bit:\tclock bit value\n+ * @rate:\tclock input rate in Hz\n+ * @return 0, or -ve error code.\n+ */\n+int mmc_clk_set_rate(void *base, u32 bit, ulong rate);\n+\n /**\n * sunxi_reset_bind() - reset binding\n *\ndiff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c\nindex fb11231dd1..55176bc174 100644\n--- a/drivers/clk/sunxi/clk_a10.c\n+++ b/drivers/clk/sunxi/clk_a10.c\n@@ -23,6 +23,11 @@ static struct ccu_clk_map a10_clks[] = {\n \t[CLK_AHB_MMC2]\t\t= { 0x060, BIT(10), NULL },\n \t[CLK_AHB_MMC3]\t\t= { 0x060, BIT(11), NULL },\n \n+\t[CLK_MMC0]\t\t= { 0x088, BIT(31), &mmc_clk_set_rate },\n+\t[CLK_MMC1]\t\t= { 0x08c, BIT(31), &mmc_clk_set_rate },\n+\t[CLK_MMC2]\t\t= { 0x090, BIT(31), &mmc_clk_set_rate },\n+\t[CLK_MMC3]\t\t= { 0x094, BIT(31), &mmc_clk_set_rate },\n+\n \t[CLK_USB_OHCI0]\t\t= { 0x0cc, BIT(6), NULL },\n \t[CLK_USB_OHCI1]\t\t= { 0x0cc, BIT(7), NULL },\n \t[CLK_USB_PHY]\t\t= { 0x0cc, BIT(8), NULL },\ndiff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c\nindex bc4ae7352b..fbac0ad751 100644\n--- a/drivers/clk/sunxi/clk_a10s.c\n+++ b/drivers/clk/sunxi/clk_a10s.c\n@@ -20,6 +20,12 @@ static struct ccu_clk_map a10s_clks[] = {\n \t[CLK_AHB_MMC1]\t\t= { 0x060, BIT(9), NULL },\n \t[CLK_AHB_MMC2]\t\t= { 0x060, BIT(10), NULL },\n \n+#ifdef CONFIG_MMC\n+\t[CLK_MMC0]\t\t= { 0x088, BIT(31), &mmc_clk_set_rate },\n+\t[CLK_MMC1]\t\t= { 0x08c, BIT(31), &mmc_clk_set_rate },\n+\t[CLK_MMC2]\t\t= { 0x090, BIT(31), &mmc_clk_set_rate },\n+#endif\n+\n \t[CLK_USB_OHCI]\t\t= { 0x0cc, BIT(6), NULL },\n \t[CLK_USB_PHY0]\t\t= { 0x0cc, BIT(8), NULL },\n \t[CLK_USB_PHY1]\t\t= { 0x0cc, BIT(9), NULL },\ndiff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c\nindex 62770a58fe..0b5406c5b3 100644\n--- a/drivers/clk/sunxi/clk_a23.c\n+++ b/drivers/clk/sunxi/clk_a23.c\n@@ -20,6 +20,12 @@ static struct ccu_clk_map a23_clks[] = {\n \t[CLK_BUS_EHCI]\t\t= { 0x060, BIT(26), NULL },\n \t[CLK_BUS_OHCI]\t\t= { 0x060, BIT(29), NULL },\n \n+#ifdef CONFIG_MMC\n+\t[CLK_MMC0]\t\t= { 0x088, BIT(31), &mmc_clk_set_rate },\n+\t[CLK_MMC1]\t\t= { 0x08c, BIT(31), &mmc_clk_set_rate },\n+\t[CLK_MMC2]\t\t= { 0x090, BIT(31), &mmc_clk_set_rate },\n+#endif\n+\n \t[CLK_USB_PHY0]\t\t= { 0x0cc, BIT(8), NULL },\n \t[CLK_USB_PHY1]\t\t= { 0x0cc, BIT(9), NULL },\n \t[CLK_USB_HSIC]\t\t= { 0x0cc, BIT(10), NULL },\ndiff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c\nindex f314feff69..3c807bde77 100644\n--- a/drivers/clk/sunxi/clk_a31.c\n+++ b/drivers/clk/sunxi/clk_a31.c\n@@ -24,6 +24,11 @@ static struct ccu_clk_map a31_clks[] = {\n \t[CLK_AHB1_OHCI1]\t= { 0x060, BIT(30), NULL },\n \t[CLK_AHB1_OHCI2]\t= { 0x060, BIT(31), NULL },\n \n+\t[CLK_MMC0]\t\t= { 0x088, BIT(31), &mmc_clk_set_rate },\n+\t[CLK_MMC1]\t\t= { 0x08c, BIT(31), &mmc_clk_set_rate },\n+\t[CLK_MMC2]\t\t= { 0x090, BIT(31), &mmc_clk_set_rate },\n+\t[CLK_MMC3]\t\t= { 0x094, BIT(31), &mmc_clk_set_rate },\n+\n \t[CLK_USB_PHY0]\t\t= { 0x0cc, BIT(8), NULL },\n \t[CLK_USB_PHY1]\t\t= { 0x0cc, BIT(9), NULL },\n \t[CLK_USB_PHY2]\t\t= { 0x0cc, BIT(10), NULL },\ndiff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c\nindex 71f3510c74..62cd6d6464 100644\n--- a/drivers/clk/sunxi/clk_a64.c\n+++ b/drivers/clk/sunxi/clk_a64.c\n@@ -22,6 +22,10 @@ static struct ccu_clk_map a64_clks[] = {\n \t[CLK_BUS_OHCI0]\t\t= { 0x060, BIT(28), NULL },\n \t[CLK_BUS_OHCI1]\t\t= { 0x060, BIT(29), NULL },\n \n+\t[CLK_MMC0]\t\t= { 0x088, BIT(31), &mmc_clk_set_rate },\n+\t[CLK_MMC1]\t\t= { 0x08c, BIT(31), &mmc_clk_set_rate },\n+\t[CLK_MMC2]\t\t= { 0x090, BIT(31), &mmc_clk_set_rate },\n+\n \t[CLK_USB_PHY0]\t\t= { 0x0cc, BIT(8), NULL },\n \t[CLK_USB_PHY1]\t\t= { 0x0cc, BIT(9), NULL },\n \t[CLK_USB_HSIC]\t\t= { 0x0cc, BIT(10), NULL },\ndiff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c\nindex cc18975a06..a2e0ac7a26 100644\n--- a/drivers/clk/sunxi/clk_a83t.c\n+++ b/drivers/clk/sunxi/clk_a83t.c\n@@ -21,6 +21,10 @@ static struct ccu_clk_map a83t_clks[] = {\n \t[CLK_BUS_EHCI1]\t\t= { 0x060, BIT(27), NULL },\n \t[CLK_BUS_OHCI0]\t\t= { 0x060, BIT(29), NULL },\n \n+\t[CLK_MMC0]\t\t= { 0x088, BIT(31), &mmc_clk_set_rate },\n+\t[CLK_MMC1]\t\t= { 0x08c, BIT(31), &mmc_clk_set_rate },\n+\t[CLK_MMC2]\t\t= { 0x090, BIT(31), &mmc_clk_set_rate },\n+\n \t[CLK_USB_PHY0]\t\t= { 0x0cc, BIT(8), NULL },\n \t[CLK_USB_PHY1]\t\t= { 0x0cc, BIT(9), NULL },\n \t[CLK_USB_HSIC]\t\t= { 0x0cc, BIT(10), NULL },\ndiff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c\nindex 85dd06ee2d..f467187c01 100644\n--- a/drivers/clk/sunxi/clk_h3.c\n+++ b/drivers/clk/sunxi/clk_h3.c\n@@ -26,6 +26,10 @@ static struct ccu_clk_map h3_clks[] = {\n \t[CLK_BUS_OHCI2]\t\t= { 0x060, BIT(30), NULL },\n \t[CLK_BUS_OHCI3]\t\t= { 0x060, BIT(31), NULL },\n \n+\t[CLK_MMC0]\t\t= { 0x088, BIT(31), &mmc_clk_set_rate },\n+\t[CLK_MMC1]\t\t= { 0x08c, BIT(31), &mmc_clk_set_rate },\n+\t[CLK_MMC2]\t\t= { 0x090, BIT(31), &mmc_clk_set_rate },\n+\n \t[CLK_USB_PHY0]\t\t= { 0x0cc, BIT(8), NULL },\n \t[CLK_USB_PHY1]\t\t= { 0x0cc, BIT(9), NULL },\n \t[CLK_USB_PHY2]\t\t= { 0x0cc, BIT(10), NULL },\ndiff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c\nindex 006aa138b6..9273f3b7ea 100644\n--- a/drivers/clk/sunxi/clk_r40.c\n+++ b/drivers/clk/sunxi/clk_r40.c\n@@ -25,6 +25,10 @@ static struct ccu_clk_map r40_clks[] = {\n \t[CLK_BUS_OHCI1]\t\t= { 0x060, BIT(30), NULL },\n \t[CLK_BUS_OHCI2]\t\t= { 0x060, BIT(31), NULL },\n \n+\t[CLK_MMC0]\t\t= { 0x088, BIT(31), &mmc_clk_set_rate },\n+\t[CLK_MMC1]\t\t= { 0x08c, BIT(31), &mmc_clk_set_rate },\n+\t[CLK_MMC2]\t\t= { 0x090, BIT(31), &mmc_clk_set_rate },\n+\t[CLK_MMC3]\t\t= { 0x094, BIT(31), &mmc_clk_set_rate },\n \n \t[CLK_USB_PHY0]\t\t= { 0x0cc, BIT(8), NULL },\n \t[CLK_USB_PHY1]\t\t= { 0x0cc, BIT(9), NULL },\ndiff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c\nindex 791b1ac7f2..ca147ec9cc 100644\n--- a/drivers/clk/sunxi/clk_sunxi.c\n+++ b/drivers/clk/sunxi/clk_sunxi.c\n@@ -12,6 +12,24 @@\n #include <asm/arch/ccu.h>\n #include <linux/log2.h>\n \n+static ulong sunxi_clk_set_rate(struct clk *clk, ulong rate)\n+{\n+\tstruct sunxi_clk_priv *priv = dev_get_priv(clk->dev);\n+\tstruct ccu_clk_map *map = &priv->desc->clks[clk->id];\n+\tu32 *base;\n+\n+\tif (!map->ccu_clk_set_rate) {\n+\t\tdebug(\"%s (CLK#%ld) unhandled\\n\", __func__, clk->id);\n+\t\treturn 0;\n+\t}\n+\n+\tdebug(\"%s(#%ld) off#0x%x, BIT(%d)\\n\", __func__,\n+\t clk->id, map->off, ilog2(map->bit));\n+\n+\tbase = priv->base + map->off;\n+\treturn map->ccu_clk_set_rate(base, map->bit, rate);\n+}\n+\n static int sunxi_clk_enable(struct clk *clk)\n {\n \tstruct sunxi_clk_priv *priv = dev_get_priv(clk->dev);\n@@ -55,4 +73,5 @@ static int sunxi_clk_disable(struct clk *clk)\n struct clk_ops sunxi_clk_ops = {\n \t.enable = sunxi_clk_enable,\n \t.disable = sunxi_clk_disable,\n+\t.set_rate = sunxi_clk_set_rate,\n };\ndiff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c\nindex ab2cc45640..e0d757debe 100644\n--- a/drivers/clk/sunxi/clk_v3s.c\n+++ b/drivers/clk/sunxi/clk_v3s.c\n@@ -18,6 +18,10 @@ static struct ccu_clk_map v3s_clks[] = {\n \t[CLK_BUS_MMC2]\t\t= { 0x060, BIT(10), NULL },\n \t[CLK_BUS_OTG]\t\t= { 0x060, BIT(24), NULL },\n \n+\t[CLK_MMC0]\t\t= { 0x088, BIT(31), &mmc_clk_set_rate },\n+\t[CLK_MMC1]\t\t= { 0x08c, BIT(31), &mmc_clk_set_rate },\n+\t[CLK_MMC2]\t\t= { 0x090, BIT(31), &mmc_clk_set_rate },\n+\n \t[CLK_USB_PHY0] = { 0x0cc, BIT(8), NULL },\n };\n \ndiff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c\nindex 39f15eb423..bf82014a64 100644\n--- a/drivers/mmc/sunxi_mmc.c\n+++ b/drivers/mmc/sunxi_mmc.c\n@@ -13,6 +13,7 @@\n #include <malloc.h>\n #include <mmc.h>\n #include <asm/io.h>\n+#include <asm/arch/ccu.h>\n #include <asm/arch/clock.h>\n #include <asm/arch/cpu.h>\n #include <asm/arch/gpio.h>\n@@ -34,6 +35,8 @@ struct sunxi_mmc_priv {\n \tstruct mmc_config cfg;\n };\n \n+bool new_mode;\n+\n #if !CONFIG_IS_ENABLED(DM_MMC)\n /* support 4 mmc hosts */\n struct sunxi_mmc_priv mmc_host[4];\n@@ -95,23 +98,19 @@ static int mmc_resource_init(int sdc_no)\n }\n #endif\n \n-static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)\n+int mmc_clk_set_rate(void *base, u32 bit, ulong rate)\n {\n \tunsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;\n-\tbool new_mode = false;\n \tu32 val = 0;\n \n-\tif (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2))\n-\t\tnew_mode = true;\n-\n \t/*\n \t * The MMC clock has an extra /2 post-divider when operating in the new\n \t * mode.\n \t */\n \tif (new_mode)\n-\t\thz = hz * 2;\n+\t\trate = rate * 2;\n \n-\tif (hz <= 24000000) {\n+\tif (rate <= 24000000) {\n \t\tpll = CCM_MMC_CTRL_OSCM24;\n \t\tpll_hz = 24000000;\n \t} else {\n@@ -127,8 +126,8 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)\n #endif\n \t}\n \n-\tdiv = pll_hz / hz;\n-\tif (pll_hz % hz)\n+\tdiv = pll_hz / rate;\n+\tif (pll_hz % rate)\n \t\tdiv++;\n \n \tn = 0;\n@@ -138,32 +137,31 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)\n \t}\n \n \tif (n > 3) {\n-\t\tprintf(\"mmc %u error cannot set clock to %u\\n\", priv->mmc_no,\n-\t\t hz);\n+\t\tprintf(\"mmc error cannot set clock to %ld\\n\", rate);\n \t\treturn -1;\n \t}\n \n \t/* determine delays */\n-\tif (hz <= 400000) {\n+\tif (rate <= 400000) {\n \t\toclk_dly = 0;\n \t\tsclk_dly = 0;\n-\t} else if (hz <= 25000000) {\n+\t} else if (rate <= 25000000) {\n \t\toclk_dly = 0;\n \t\tsclk_dly = 5;\n #ifdef CONFIG_MACH_SUN9I\n-\t} else if (hz <= 52000000) {\n+\t} else if (rate <= 52000000) {\n \t\toclk_dly = 5;\n \t\tsclk_dly = 4;\n \t} else {\n-\t\t/* hz > 52000000 */\n+\t\t/* rate > 52000000 */\n \t\toclk_dly = 2;\n \t\tsclk_dly = 4;\n #else\n-\t} else if (hz <= 52000000) {\n+\t} else if (rate <= 52000000) {\n \t\toclk_dly = 3;\n \t\tsclk_dly = 4;\n \t} else {\n-\t\t/* hz > 52000000 */\n+\t\t/* rate > 52000000 */\n \t\toclk_dly = 1;\n \t\tsclk_dly = 4;\n #endif\n@@ -172,22 +170,35 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)\n \tif (new_mode) {\n #ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE\n \t\tval = CCM_MMC_CTRL_MODE_SEL_NEW;\n-\t\tsetbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);\n #endif\n \t} else {\n \t\tval = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |\n \t\t\tCCM_MMC_CTRL_SCLK_DLY(sclk_dly);\n \t}\n \n-\twritel(CCM_MMC_CTRL_ENABLE| pll | CCM_MMC_CTRL_N(n) |\n-\t CCM_MMC_CTRL_M(div) | val, priv->mclkreg);\n+\twritel(bit | pll | CCM_MMC_CTRL_N(n) |\n+\t CCM_MMC_CTRL_M(div) | val, base);\n \n-\tdebug(\"mmc %u set mod-clk req %u parent %u n %u m %u rate %u\\n\",\n-\t priv->mmc_no, hz, pll_hz, 1u << n, div, pll_hz / (1u << n) / div);\n+\tdebug(\"mmc set mod-clk req %ld parent %u n %u m %u rate %u\\n\",\n+\t rate, pll_hz, 1u << n, div, pll_hz / (1u << n) / div);\n \n \treturn 0;\n }\n \n+static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)\n+{\n+#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(CLK)\n+#else\n+\tif (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2))\n+\t\tnew_mode = true;\n+\n+\tif (new_mode)\n+\t\tsetbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);\n+\n+\treturn mmc_clk_set_rate(priv->mclkreg, CCM_MMC_CTRL_ENABLE, hz);\n+#endif\n+}\n+\n static int mmc_update_clk(struct sunxi_mmc_priv *priv)\n {\n \tunsigned int cmd;\n@@ -599,6 +610,9 @@ static int sunxi_mmc_probe(struct udevice *dev)\n \tcfg->f_min = 400000;\n \tcfg->f_max = 52000000;\n \n+\tif (device_is_compatible(dev, \"allwinner,sun8i-a83t-emmc\"))\n+\t\tnew_mode = true;\n+\n \tpriv->reg = (void *)dev_read_addr(dev);\n \n \t/* We don't have a sunxi clock driver so find the clock address here */\n", "prefixes": [ "U-Boot", "v2", "20/53" ] }