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GET /api/patches/955984/?format=api
{ "id": 955984, "url": "http://patchwork.ozlabs.org/api/patches/955984/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20180810060711.6547-43-jagan@amarulasolutions.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20180810060711.6547-43-jagan@amarulasolutions.com>", "list_archive_url": null, "date": "2018-08-10T06:07:00", "name": "[U-Boot,v2,42/53] clk: sunxi: Implement UART resets", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "60f6ba2a4b970459b8855c85abda9f9fac3a4dfe", "submitter": { "id": 69820, "url": "http://patchwork.ozlabs.org/api/people/69820/?format=api", "name": "Jagan Teki", "email": "jagan@amarulasolutions.com" }, "delegate": { "id": 17739, "url": "http://patchwork.ozlabs.org/api/users/17739/?format=api", "username": "jagan", "first_name": "Jagannadha Sutradharudu", "last_name": "Teki", "email": "jagannadh.teki@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20180810060711.6547-43-jagan@amarulasolutions.com/mbox/", "series": [ { "id": 60190, "url": "http://patchwork.ozlabs.org/api/series/60190/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=60190", "date": "2018-08-10T06:06:18", "name": "clk: Add Allwinner CLK, RESET support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/60190/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/955984/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/955984/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=amarulasolutions.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=amarulasolutions.com\n\theader.i=@amarulasolutions.com header.b=\"MFl8kl9S\"; \n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 41mwMp1RSGz9s8f\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 10 Aug 2018 16:34:46 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid E991AC21DAF; Fri, 10 Aug 2018 06:24:15 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 398AAC21E42;\n\tFri, 10 Aug 2018 06:14:13 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s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=gUMyiVHoZsiPJ/V0d/uxaMjYhRsUbeWCsdgEG9YAYrc=;\n\tb=FsnKQoAjBrvfKgxOYZ9CdQ8sxwmROlHJ688KCQCpRSfJzaIecd7JGH2ctPNazye2wX\n\t3fkSn2HEahqspVxfbmesx2OgTaTDJ0ZVGTCK8up9HtgIBOZ79k0v07fWYXetfRobdkAM\n\tVZCu+fKUB4AP5L3cF6wn/Mqit1gXlWo9MqQMVtXgDr9mOEc7klAe7UJvehUFDNtk2+OG\n\tjYZ2l7Lcj3G617wqemdArsYYeCpHi7rqnjEBqEA85i43GDFR6EYnjtVDL32TdqBPAUcE\n\tvTLD0/oPfTD/9oibO9QsxfAJip8NyXNaqgSKtww1jfCByIq+a9WPU69pdQ3GLye0Gxnk\n\tIOSw==", "X-Gm-Message-State": "AOUpUlFO/TVFQzDkDwrAfg9MJ8/c95wrEp0E0IRDkdc7+5idTah6OacQ\n\tiTGcnQ9udngUwrw/Ged1vS0J+Q==", "X-Google-Smtp-Source": "AA+uWPzHLZFdBlnqCDzYKYYdyDcF1uIaVEhRyIx65Jm2srv3BoXYGlap1HMMBnVhE2CY84VNoxM04w==", "X-Received": "by 2002:a17:902:d706:: with SMTP id\n\tw6-v6mr4834470ply.158.1533881418285; \n\tThu, 09 Aug 2018 23:10:18 -0700 (PDT)", "From": "Jagan Teki <jagan@amarulasolutions.com>", "To": "Maxime Ripard <maxime.ripard@bootlin.com>,\n\tAndre Przywara <andre.przywara@arm.com>, Chen-Yu Tsai <wens@csie.org>,\n\tIcenowy Zheng <icenowy@aosc.io>", "Date": "Fri, 10 Aug 2018 11:37:00 +0530", "Message-Id": "<20180810060711.6547-43-jagan@amarulasolutions.com>", "X-Mailer": "git-send-email 2.18.0.321.gffc6fa0e3", "In-Reply-To": "<20180810060711.6547-1-jagan@amarulasolutions.com>", "References": "<20180810060711.6547-1-jagan@amarulasolutions.com>", "MIME-Version": "1.0", "Cc": "Tom Rini <trini@konsulko.com>, u-boot@lists.denx.de", "Subject": "[U-Boot] [PATCH v2 42/53] clk: sunxi: Implement UART resets", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Implement UART resets for all relevant Allwinner SoC\nclock drivers via reset map descriptor table.\n\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\n---\n drivers/clk/sunxi/clk_a23.c | 6 ++++++\n drivers/clk/sunxi/clk_a31.c | 7 +++++++\n drivers/clk/sunxi/clk_a64.c | 6 ++++++\n drivers/clk/sunxi/clk_a83t.c | 6 ++++++\n drivers/clk/sunxi/clk_h3.c | 5 +++++\n drivers/clk/sunxi/clk_r40.c | 9 +++++++++\n drivers/clk/sunxi/clk_v3s.c | 4 ++++\n 7 files changed, 43 insertions(+)", "diff": "diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c\nindex 331c79af81..268148002b 100644\n--- a/drivers/clk/sunxi/clk_a23.c\n+++ b/drivers/clk/sunxi/clk_a23.c\n@@ -50,6 +50,12 @@ static struct ccu_reset_map a23_resets[] = {\n \t[RST_BUS_OTG]\t\t= { 0x2c0, BIT(24) },\n \t[RST_BUS_EHCI]\t\t= { 0x2c0, BIT(26) },\n \t[RST_BUS_OHCI]\t\t= { 0x2c0, BIT(29) },\n+\n+\t[RST_BUS_UART0]\t\t= { 0x2d8, BIT(16) },\n+\t[RST_BUS_UART1]\t\t= { 0x2d8, BIT(17) },\n+\t[RST_BUS_UART2]\t\t= { 0x2d8, BIT(18) },\n+\t[RST_BUS_UART3]\t\t= { 0x2d8, BIT(19) },\n+\t[RST_BUS_UART4]\t\t= { 0x2d8, BIT(20) },\n };\n \n static const struct ccu_desc sun8i_a23_ccu_desc = {\ndiff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c\nindex 40803a1d64..288979a18f 100644\n--- a/drivers/clk/sunxi/clk_a31.c\n+++ b/drivers/clk/sunxi/clk_a31.c\n@@ -72,6 +72,13 @@ static struct ccu_reset_map a31_resets[] = {\n \t[RST_AHB1_OHCI0]\t= { 0x2c0, BIT(29) },\n \t[RST_AHB1_OHCI1]\t= { 0x2c0, BIT(30) },\n \t[RST_AHB1_OHCI2]\t= { 0x2c0, BIT(31) },\n+\n+\t[RST_APB2_UART0]\t= { 0x2d8, BIT(16) },\n+\t[RST_APB2_UART1]\t= { 0x2d8, BIT(17) },\n+\t[RST_APB2_UART2]\t= { 0x2d8, BIT(18) },\n+\t[RST_APB2_UART3]\t= { 0x2d8, BIT(19) },\n+\t[RST_APB2_UART4]\t= { 0x2d8, BIT(20) },\n+\t[RST_APB2_UART5]\t= { 0x2d8, BIT(21) },\n };\n \n static const struct ccu_desc sun6i_a31_ccu_desc = {\ndiff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c\nindex 13b506f983..344cfb59aa 100644\n--- a/drivers/clk/sunxi/clk_a64.c\n+++ b/drivers/clk/sunxi/clk_a64.c\n@@ -60,6 +60,12 @@ static struct ccu_reset_map a64_resets[] = {\n \t[RST_BUS_EHCI1]\t\t= { 0x2c0, BIT(25) },\n \t[RST_BUS_OHCI0]\t\t= { 0x2c0, BIT(28) },\n \t[RST_BUS_OHCI1]\t\t= { 0x2c0, BIT(29) },\n+\n+\t[RST_BUS_UART0]\t\t= { 0x2d8, BIT(16) },\n+\t[RST_BUS_UART1]\t\t= { 0x2d8, BIT(17) },\n+\t[RST_BUS_UART2]\t\t= { 0x2d8, BIT(18) },\n+\t[RST_BUS_UART3]\t\t= { 0x2d8, BIT(19) },\n+\t[RST_BUS_UART4]\t\t= { 0x2d8, BIT(20) },\n };\n \n static const struct ccu_desc sun50i_a64_ccu_desc = {\ndiff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c\nindex 5c1235fa7b..cf9455da97 100644\n--- a/drivers/clk/sunxi/clk_a83t.c\n+++ b/drivers/clk/sunxi/clk_a83t.c\n@@ -50,6 +50,12 @@ static struct ccu_reset_map a83t_resets[] = {\n \t[RST_BUS_EHCI0]\t\t= { 0x2c0, BIT(26) },\n \t[RST_BUS_EHCI1]\t\t= { 0x2c0, BIT(27) },\n \t[RST_BUS_OHCI0]\t\t= { 0x2c0, BIT(29) },\n+\n+\t[RST_BUS_UART0]\t\t= { 0x2d8, BIT(16) },\n+\t[RST_BUS_UART1]\t\t= { 0x2d8, BIT(17) },\n+\t[RST_BUS_UART2]\t\t= { 0x2d8, BIT(18) },\n+\t[RST_BUS_UART3]\t\t= { 0x2d8, BIT(19) },\n+\t[RST_BUS_UART4]\t\t= { 0x2d8, BIT(20) },\n };\n \n static const struct ccu_desc sun8i_a83t_ccu_desc = {\ndiff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c\nindex b132ae0a0d..15d933a6c5 100644\n--- a/drivers/clk/sunxi/clk_h3.c\n+++ b/drivers/clk/sunxi/clk_h3.c\n@@ -70,6 +70,11 @@ static struct ccu_reset_map h3_resets[] = {\n \t[RST_BUS_OHCI1]\t\t= { 0x2c0, BIT(29) },\n \t[RST_BUS_OHCI2]\t\t= { 0x2c0, BIT(30) },\n \t[RST_BUS_OHCI3]\t\t= { 0x2c0, BIT(31) },\n+\n+\t[RST_BUS_UART0]\t\t= { 0x2d8, BIT(16) },\n+\t[RST_BUS_UART1]\t\t= { 0x2d8, BIT(17) },\n+\t[RST_BUS_UART2]\t\t= { 0x2d8, BIT(18) },\n+\t[RST_BUS_UART3]\t\t= { 0x2d8, BIT(19) },\n };\n \n static const struct ccu_desc sun8i_h3_ccu_desc = {\ndiff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c\nindex 1e5b1d10f7..ee699d26ee 100644\n--- a/drivers/clk/sunxi/clk_r40.c\n+++ b/drivers/clk/sunxi/clk_r40.c\n@@ -63,6 +63,15 @@ static struct ccu_reset_map r40_resets[] = {\n \t[RST_BUS_OHCI0]\t\t= { 0x2c0, BIT(29) },\n \t[RST_BUS_OHCI1]\t\t= { 0x2c0, BIT(30) },\n \t[RST_BUS_OHCI2]\t\t= { 0x2c0, BIT(31) },\n+\n+\t[RST_BUS_UART0]\t\t= { 0x2d8, BIT(16) },\n+\t[RST_BUS_UART1]\t\t= { 0x2d8, BIT(17) },\n+\t[RST_BUS_UART2]\t\t= { 0x2d8, BIT(18) },\n+\t[RST_BUS_UART3]\t\t= { 0x2d8, BIT(19) },\n+\t[RST_BUS_UART4]\t\t= { 0x2d8, BIT(20) },\n+\t[RST_BUS_UART5]\t\t= { 0x2d8, BIT(21) },\n+\t[RST_BUS_UART6]\t\t= { 0x2d8, BIT(22) },\n+\t[RST_BUS_UART7]\t\t= { 0x2d8, BIT(23) },\n };\n \n static const struct ccu_desc sun8i_r40_ccu_desc = {\ndiff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c\nindex c6e57147ee..87ca0350d8 100644\n--- a/drivers/clk/sunxi/clk_v3s.c\n+++ b/drivers/clk/sunxi/clk_v3s.c\n@@ -40,6 +40,10 @@ static struct ccu_reset_map v3s_resets[] = {\n \t[RST_BUS_MMC2]\t\t= { 0x2c0, BIT(10) },\n \t[RST_BUS_SPI0]\t\t= { 0x2c0, BIT(20) },\n \t[RST_BUS_OTG]\t\t= { 0x2c0, BIT(24) },\n+\n+\t[RST_BUS_UART0]\t\t= { 0x2d8, BIT(16) },\n+\t[RST_BUS_UART1]\t\t= { 0x2d8, BIT(17) },\n+\t[RST_BUS_UART2]\t\t= { 0x2d8, BIT(18) },\n };\n \n static const struct ccu_desc sun8i_v3s_ccu_desc = {\n", "prefixes": [ "U-Boot", "v2", "42/53" ] }