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GET /api/patches/955966/?format=api
{ "id": 955966, "url": "http://patchwork.ozlabs.org/api/patches/955966/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20180810060711.6547-20-jagan@amarulasolutions.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20180810060711.6547-20-jagan@amarulasolutions.com>", "list_archive_url": null, "date": "2018-08-10T06:06:37", "name": "[U-Boot,v2,19/53] clk: sunxi: Implement AHB bus MMC clocks", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "18ca5c9fcdba644d7f3f93d037ab47a8abfeebf9", "submitter": { "id": 69820, "url": "http://patchwork.ozlabs.org/api/people/69820/?format=api", "name": "Jagan Teki", "email": "jagan@amarulasolutions.com" }, "delegate": { "id": 17739, "url": "http://patchwork.ozlabs.org/api/users/17739/?format=api", "username": "jagan", "first_name": "Jagannadha Sutradharudu", "last_name": "Teki", "email": "jagannadh.teki@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20180810060711.6547-20-jagan@amarulasolutions.com/mbox/", "series": [ { "id": 60190, "url": "http://patchwork.ozlabs.org/api/series/60190/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=60190", "date": "2018-08-10T06:06:18", "name": "clk: Add Allwinner CLK, RESET support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/60190/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/955966/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/955966/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=amarulasolutions.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=amarulasolutions.com\n\theader.i=@amarulasolutions.com header.b=\"gzdYrd6D\"; \n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 41mw8y1lLGz9s7Q\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 10 Aug 2018 16:25:22 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid ED6C4C21DA6; Fri, 10 Aug 2018 06:22:00 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 900ADC21DA6;\n\tFri, 10 Aug 2018 06:12:15 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s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=cuEkYe5unbMN1Bmhz1F4HKzzGmRhG4Jpw3XsSkI4xPg=;\n\tb=dGq9zi0qkGihv5qKtUDsOE5UJreDFMEJNC0Ee8F+EbY5vVZfVbbTWoH8ueqLreQauT\n\tmSWBnKNA7fuFQir/cAWxV99/dR0Nu8ZOOU4KgVEpnzNM80NhBouzPQ0wwc/WmvHdAgwO\n\tCErBgEkS8frpvjks0rHz6UxQsfqXA9Xb5Ldw+207uz8EUXIfSDo6E2E/Cp5w0plmHN1m\n\tgeAqMCG3HZknJi3sy1dxMpTJq0NM36yexODxWcE1EGV5S3+hfOqnhV7agfH0nOFniRgf\n\t5RiFByvkE7qCBErYZZKTrJqM3FJlo9vNX26QSFK7P+kanfD4K17aXc4FLhiv6q314HxJ\n\tZXAw==", "X-Gm-Message-State": "AOUpUlH5cn9neO/3nbGS0+8IeD06jYNdnakbzQrjRnHmPuoTlkN71Y/o\n\t3MXItPMsUmP0xIWSIszMO0sGxw==", "X-Google-Smtp-Source": "AA+uWPz1J5T0gE0VlbisOlEtespRDYwRIeAbR1aFc9pX753Sc33qVa2L+RwcK7KRoCErMf//5fGpNQ==", "X-Received": "by 2002:a63:947:: with SMTP id\n\t68-v6mr5058842pgj.131.1533881329719; \n\tThu, 09 Aug 2018 23:08:49 -0700 (PDT)", "From": "Jagan Teki <jagan@amarulasolutions.com>", "To": "Maxime Ripard <maxime.ripard@bootlin.com>,\n\tAndre Przywara <andre.przywara@arm.com>, Chen-Yu Tsai <wens@csie.org>,\n\tIcenowy Zheng <icenowy@aosc.io>", "Date": "Fri, 10 Aug 2018 11:36:37 +0530", "Message-Id": "<20180810060711.6547-20-jagan@amarulasolutions.com>", "X-Mailer": "git-send-email 2.18.0.321.gffc6fa0e3", "In-Reply-To": "<20180810060711.6547-1-jagan@amarulasolutions.com>", "References": "<20180810060711.6547-1-jagan@amarulasolutions.com>", "MIME-Version": "1.0", "Cc": "Tom Rini <trini@konsulko.com>, u-boot@lists.denx.de", "Subject": "[U-Boot] [PATCH v2 19/53] clk: sunxi: Implement AHB bus MMC clocks", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Implement AHB bus MMC clocks for all Allwinner SoC\nclock drivers via clock map descriptor table.\n\nCc: Jaehoon Chung <jh80.chung@samsung.com>\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\n---\n drivers/clk/sunxi/clk_a10.c | 4 ++++\n drivers/clk/sunxi/clk_a10s.c | 3 +++\n drivers/clk/sunxi/clk_a23.c | 3 +++\n drivers/clk/sunxi/clk_a31.c | 4 ++++\n drivers/clk/sunxi/clk_a64.c | 3 +++\n drivers/clk/sunxi/clk_a83t.c | 3 +++\n drivers/clk/sunxi/clk_h3.c | 3 +++\n drivers/clk/sunxi/clk_r40.c | 4 ++++\n drivers/clk/sunxi/clk_v3s.c | 3 +++\n 9 files changed, 30 insertions(+)", "diff": "diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c\nindex 7492e1367a..fb11231dd1 100644\n--- a/drivers/clk/sunxi/clk_a10.c\n+++ b/drivers/clk/sunxi/clk_a10.c\n@@ -18,6 +18,10 @@ static struct ccu_clk_map a10_clks[] = {\n \t[CLK_AHB_OHCI0]\t\t= { 0x060, BIT(2), NULL },\n \t[CLK_AHB_EHCI1]\t\t= { 0x060, BIT(3), NULL },\n \t[CLK_AHB_OHCI1]\t\t= { 0x060, BIT(4), NULL },\n+\t[CLK_AHB_MMC0]\t\t= { 0x060, BIT(8), NULL },\n+\t[CLK_AHB_MMC1]\t\t= { 0x060, BIT(9), NULL },\n+\t[CLK_AHB_MMC2]\t\t= { 0x060, BIT(10), NULL },\n+\t[CLK_AHB_MMC3]\t\t= { 0x060, BIT(11), NULL },\n \n \t[CLK_USB_OHCI0]\t\t= { 0x0cc, BIT(6), NULL },\n \t[CLK_USB_OHCI1]\t\t= { 0x0cc, BIT(7), NULL },\ndiff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c\nindex 976595201f..bc4ae7352b 100644\n--- a/drivers/clk/sunxi/clk_a10s.c\n+++ b/drivers/clk/sunxi/clk_a10s.c\n@@ -16,6 +16,9 @@ static struct ccu_clk_map a10s_clks[] = {\n \t[CLK_AHB_OTG]\t\t= { 0x060, BIT(0), NULL },\n \t[CLK_AHB_EHCI]\t\t= { 0x060, BIT(1), NULL },\n \t[CLK_AHB_OHCI]\t\t= { 0x060, BIT(2), NULL },\n+\t[CLK_AHB_MMC0]\t\t= { 0x060, BIT(8), NULL },\n+\t[CLK_AHB_MMC1]\t\t= { 0x060, BIT(9), NULL },\n+\t[CLK_AHB_MMC2]\t\t= { 0x060, BIT(10), NULL },\n \n \t[CLK_USB_OHCI]\t\t= { 0x0cc, BIT(6), NULL },\n \t[CLK_USB_PHY0]\t\t= { 0x0cc, BIT(8), NULL },\ndiff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c\nindex ec9834e1a8..62770a58fe 100644\n--- a/drivers/clk/sunxi/clk_a23.c\n+++ b/drivers/clk/sunxi/clk_a23.c\n@@ -13,6 +13,9 @@\n #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>\n \n static struct ccu_clk_map a23_clks[] = {\n+\t[CLK_BUS_MMC0]\t\t= { 0x060, BIT(8), NULL },\n+\t[CLK_BUS_MMC1]\t\t= { 0x060, BIT(9), NULL },\n+\t[CLK_BUS_MMC2]\t\t= { 0x060, BIT(10), NULL },\n \t[CLK_BUS_OTG]\t\t= { 0x060, BIT(24), NULL },\n \t[CLK_BUS_EHCI]\t\t= { 0x060, BIT(26), NULL },\n \t[CLK_BUS_OHCI]\t\t= { 0x060, BIT(29), NULL },\ndiff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c\nindex c6d82be120..f314feff69 100644\n--- a/drivers/clk/sunxi/clk_a31.c\n+++ b/drivers/clk/sunxi/clk_a31.c\n@@ -13,6 +13,10 @@\n #include <dt-bindings/reset/sun6i-a31-ccu.h>\n \n static struct ccu_clk_map a31_clks[] = {\n+\t[CLK_AHB1_MMC0]\t\t= { 0x060, BIT(8), NULL },\n+\t[CLK_AHB1_MMC1]\t\t= { 0x060, BIT(9), NULL },\n+\t[CLK_AHB1_MMC2]\t\t= { 0x060, BIT(10), NULL },\n+\t[CLK_AHB1_MMC3]\t\t= { 0x060, BIT(12), NULL },\n \t[CLK_AHB1_OTG]\t\t= { 0x060, BIT(24), NULL },\n \t[CLK_AHB1_EHCI0]\t= { 0x060, BIT(26), NULL },\n \t[CLK_AHB1_EHCI1]\t= { 0x060, BIT(27), NULL },\ndiff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c\nindex e5257b62c7..71f3510c74 100644\n--- a/drivers/clk/sunxi/clk_a64.c\n+++ b/drivers/clk/sunxi/clk_a64.c\n@@ -13,6 +13,9 @@\n #include <dt-bindings/reset/sun50i-a64-ccu.h>\n \n static struct ccu_clk_map a64_clks[] = {\n+\t[CLK_BUS_MMC0]\t\t= { 0x060, BIT(8), NULL },\n+\t[CLK_BUS_MMC1]\t\t= { 0x060, BIT(9), NULL },\n+\t[CLK_BUS_MMC2]\t\t= { 0x060, BIT(10), NULL },\n \t[CLK_BUS_OTG]\t\t= { 0x060, BIT(23), NULL },\n \t[CLK_BUS_EHCI0]\t\t= { 0x060, BIT(24), NULL },\n \t[CLK_BUS_EHCI1]\t\t= { 0x060, BIT(25), NULL },\ndiff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c\nindex 58d28eb6ad..cc18975a06 100644\n--- a/drivers/clk/sunxi/clk_a83t.c\n+++ b/drivers/clk/sunxi/clk_a83t.c\n@@ -13,6 +13,9 @@\n #include <dt-bindings/reset/sun8i-a83t-ccu.h>\n \n static struct ccu_clk_map a83t_clks[] = {\n+\t[CLK_BUS_MMC0]\t\t= { 0x060, BIT(8), NULL },\n+\t[CLK_BUS_MMC1]\t\t= { 0x060, BIT(9), NULL },\n+\t[CLK_BUS_MMC2]\t\t= { 0x060, BIT(10), NULL },\n \t[CLK_BUS_OTG]\t\t= { 0x060, BIT(24), NULL },\n \t[CLK_BUS_EHCI0]\t\t= { 0x060, BIT(26), NULL },\n \t[CLK_BUS_EHCI1]\t\t= { 0x060, BIT(27), NULL },\ndiff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c\nindex 0b7f4947dd..85dd06ee2d 100644\n--- a/drivers/clk/sunxi/clk_h3.c\n+++ b/drivers/clk/sunxi/clk_h3.c\n@@ -13,6 +13,9 @@\n #include <dt-bindings/reset/sun8i-h3-ccu.h>\n \n static struct ccu_clk_map h3_clks[] = {\n+\t[CLK_BUS_MMC0]\t\t= { 0x060, BIT(8), NULL },\n+\t[CLK_BUS_MMC1]\t\t= { 0x060, BIT(9), NULL },\n+\t[CLK_BUS_MMC2]\t\t= { 0x060, BIT(10), NULL },\n \t[CLK_BUS_OTG]\t\t= { 0x060, BIT(23), NULL },\n \t[CLK_BUS_EHCI0]\t\t= { 0x060, BIT(24), NULL },\n \t[CLK_BUS_EHCI1]\t\t= { 0x060, BIT(25), NULL },\ndiff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c\nindex 746d6734b2..006aa138b6 100644\n--- a/drivers/clk/sunxi/clk_r40.c\n+++ b/drivers/clk/sunxi/clk_r40.c\n@@ -13,6 +13,10 @@\n #include <dt-bindings/reset/sun8i-r40-ccu.h>\n \n static struct ccu_clk_map r40_clks[] = {\n+\t[CLK_BUS_MMC0]\t\t= { 0x060, BIT(8), NULL },\n+\t[CLK_BUS_MMC1]\t\t= { 0x060, BIT(9), NULL },\n+\t[CLK_BUS_MMC2]\t\t= { 0x060, BIT(10), NULL },\n+\t[CLK_BUS_MMC3]\t\t= { 0x060, BIT(11), NULL },\n \t[CLK_BUS_OTG]\t\t= { 0x060, BIT(25), NULL },\n \t[CLK_BUS_EHCI0]\t\t= { 0x060, BIT(26), NULL },\n \t[CLK_BUS_EHCI1]\t\t= { 0x060, BIT(27), NULL },\ndiff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c\nindex 2494518798..ab2cc45640 100644\n--- a/drivers/clk/sunxi/clk_v3s.c\n+++ b/drivers/clk/sunxi/clk_v3s.c\n@@ -13,6 +13,9 @@\n #include <dt-bindings/reset/sun8i-v3s-ccu.h>\n \n static struct ccu_clk_map v3s_clks[] = {\n+\t[CLK_BUS_MMC0]\t\t= { 0x060, BIT(8), NULL },\n+\t[CLK_BUS_MMC1]\t\t= { 0x060, BIT(9), NULL },\n+\t[CLK_BUS_MMC2]\t\t= { 0x060, BIT(10), NULL },\n \t[CLK_BUS_OTG]\t\t= { 0x060, BIT(24), NULL },\n \n \t[CLK_USB_PHY0] = { 0x0cc, BIT(8), NULL },\n", "prefixes": [ "U-Boot", "v2", "19/53" ] }