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GET /api/patches/955964/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 955964,
    "url": "http://patchwork.ozlabs.org/api/patches/955964/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20180810060711.6547-14-jagan@amarulasolutions.com/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20180810060711.6547-14-jagan@amarulasolutions.com>",
    "list_archive_url": null,
    "date": "2018-08-10T06:06:31",
    "name": "[U-Boot,v2,13/53] clk: sunxi: Add Allwinner V3S CLK driver",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": false,
    "hash": "130478bf22c69dc3e33a93c2031a449a80a581c5",
    "submitter": {
        "id": 69820,
        "url": "http://patchwork.ozlabs.org/api/people/69820/?format=api",
        "name": "Jagan Teki",
        "email": "jagan@amarulasolutions.com"
    },
    "delegate": {
        "id": 17739,
        "url": "http://patchwork.ozlabs.org/api/users/17739/?format=api",
        "username": "jagan",
        "first_name": "Jagannadha Sutradharudu",
        "last_name": "Teki",
        "email": "jagannadh.teki@gmail.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20180810060711.6547-14-jagan@amarulasolutions.com/mbox/",
    "series": [
        {
            "id": 60190,
            "url": "http://patchwork.ozlabs.org/api/series/60190/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=60190",
            "date": "2018-08-10T06:06:18",
            "name": "clk: Add Allwinner CLK, RESET support",
            "version": 2,
            "mbox": "http://patchwork.ozlabs.org/series/60190/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/955964/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/955964/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Jagan Teki <jagan@amarulasolutions.com>",
        "To": "Maxime Ripard <maxime.ripard@bootlin.com>,\n\tAndre Przywara <andre.przywara@arm.com>, Chen-Yu Tsai <wens@csie.org>,\n\tIcenowy Zheng <icenowy@aosc.io>",
        "Date": "Fri, 10 Aug 2018 11:36:31 +0530",
        "Message-Id": "<20180810060711.6547-14-jagan@amarulasolutions.com>",
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        "In-Reply-To": "<20180810060711.6547-1-jagan@amarulasolutions.com>",
        "References": "<20180810060711.6547-1-jagan@amarulasolutions.com>",
        "MIME-Version": "1.0",
        "Cc": "Tom Rini <trini@konsulko.com>, u-boot@lists.denx.de",
        "Subject": "[U-Boot] [PATCH v2 13/53] clk: sunxi: Add Allwinner V3S CLK driver",
        "X-BeenThere": "u-boot@lists.denx.de",
        "X-Mailman-Version": "2.1.18",
        "Precedence": "list",
        "List-Id": "U-Boot discussion <u-boot.lists.denx.de>",
        "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>",
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        "Content-Type": "text/plain; charset=\"utf-8\"",
        "Content-Transfer-Encoding": "base64",
        "Errors-To": "u-boot-bounces@lists.denx.de",
        "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>"
    },
    "content": "Add initial clock driver for Allwinner V3S.\n\n- Implement USB bus and USB clocks via ccu_clk_map descriptor\n  for V3S, so it can accessed in common clk enable and disable\n  functions from clk_sunxi.c\n- Implement USB bus and USB resets via ccu_reset_map descriptor\n  for V3S, so it can accessed in common reset deassert and assert\n  functions from reset-sunxi.c\n\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\n---\n drivers/clk/sunxi/Kconfig   |  7 ++++\n drivers/clk/sunxi/Makefile  |  1 +\n drivers/clk/sunxi/clk_v3s.c | 69 +++++++++++++++++++++++++++++++++++++\n 3 files changed, 77 insertions(+)\n create mode 100644 drivers/clk/sunxi/clk_v3s.c",
    "diff": "diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig\nindex c45a4ba378..a6f84e9e56 100644\n--- a/drivers/clk/sunxi/Kconfig\n+++ b/drivers/clk/sunxi/Kconfig\n@@ -51,6 +51,13 @@ config CLK_SUN8I_R40\n \t  This enables common clock driver support for platforms based\n \t  on Allwinner R40 SoC.\n \n+config CLK_SUN8I_V3S\n+\tbool \"Clock driver for Allwinner V3S\"\n+\tdefault MACH_SUN8I_V3S\n+\thelp\n+\t  This enables common clock driver support for platforms based\n+\t  on Allwinner V3S SoC.\n+\n config CLK_SUN8I_H3\n \tbool \"Clock driver for Allwinner H3/H5\"\n \tdefault MACH_SUNXI_H3_H5\ndiff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile\nindex 61f8b87396..fbd43527a6 100644\n--- a/drivers/clk/sunxi/Makefile\n+++ b/drivers/clk/sunxi/Makefile\n@@ -12,5 +12,6 @@ obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o\n obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o\n obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o\n obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o\n+obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o\n obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o\n obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o\ndiff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c\nnew file mode 100644\nindex 0000000000..2494518798\n--- /dev/null\n+++ b/drivers/clk/sunxi/clk_v3s.c\n@@ -0,0 +1,69 @@\n+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n+/*\n+ * Copyright (C) 2018 Amarula Solutions.\n+ * Author: Jagan Teki <jagan@amarulasolutions.com>\n+ */\n+\n+#include <common.h>\n+#include <clk-uclass.h>\n+#include <dm.h>\n+#include <errno.h>\n+#include <asm/arch/ccu.h>\n+#include <dt-bindings/clock/sun8i-v3s-ccu.h>\n+#include <dt-bindings/reset/sun8i-v3s-ccu.h>\n+\n+static struct ccu_clk_map v3s_clks[] = {\n+\t[CLK_BUS_OTG]\t\t= { 0x060, BIT(24), NULL },\n+\n+\t[CLK_USB_PHY0]          = { 0x0cc, BIT(8), NULL },\n+};\n+\n+static struct ccu_reset_map v3s_resets[] = {\n+\t[RST_USB_PHY0]\t\t= { 0x0cc, BIT(0) },\n+\n+\t[RST_BUS_OTG]\t\t= { 0x2c0, BIT(24) },\n+};\n+\n+static const struct ccu_desc sun8i_v3s_ccu_desc = {\n+\t.clks = v3s_clks,\n+\t.num_clks = ARRAY_SIZE(v3s_clks),\n+\n+\t.resets = v3s_resets,\n+\t.num_resets =  ARRAY_SIZE(v3s_resets),\n+};\n+\n+static int v3s_clk_probe(struct udevice *dev)\n+{\n+\tstruct sunxi_clk_priv *priv = dev_get_priv(dev);\n+\n+\tpriv->base = dev_read_addr_ptr(dev);\n+\tif (!priv->base)\n+\t\treturn -ENOMEM;\n+\n+\tpriv->desc = (const struct ccu_desc *)dev_get_driver_data(dev);\n+\tif (!priv->desc)\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n+static int v3s_clk_bind(struct udevice *dev)\n+{\n+\treturn sunxi_reset_bind(dev, 53);\n+}\n+\n+static const struct udevice_id v3s_clk_ids[] = {\n+\t{ .compatible = \"allwinner,sun8i-v3s-ccu\",\n+\t  .data = (ulong)&sun8i_v3s_ccu_desc },\n+\t{ }\n+};\n+\n+U_BOOT_DRIVER(clk_sun8i_v3s) = {\n+\t.name\t\t= \"sun8i_v3s_ccu\",\n+\t.id\t\t= UCLASS_CLK,\n+\t.of_match\t= v3s_clk_ids,\n+\t.priv_auto_alloc_size\t= sizeof(struct sunxi_clk_priv),\n+\t.ops\t\t= &sunxi_clk_ops,\n+\t.probe\t\t= v3s_clk_probe,\n+\t.bind\t\t= v3s_clk_bind,\n+};\n",
    "prefixes": [
        "U-Boot",
        "v2",
        "13/53"
    ]
}