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GET /api/patches/955961/?format=api
{ "id": 955961, "url": "http://patchwork.ozlabs.org/api/patches/955961/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20180810060711.6547-25-jagan@amarulasolutions.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20180810060711.6547-25-jagan@amarulasolutions.com>", "list_archive_url": null, "date": "2018-08-10T06:06:42", "name": "[U-Boot,v2,24/53] dm: mmc: sunxi: Add CLK and RESET support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "afae792c1e1b20f234c2bd415987198209b0febb", "submitter": { "id": 69820, "url": "http://patchwork.ozlabs.org/api/people/69820/?format=api", "name": "Jagan Teki", "email": "jagan@amarulasolutions.com" }, "delegate": { "id": 17739, "url": "http://patchwork.ozlabs.org/api/users/17739/?format=api", "username": "jagan", "first_name": "Jagannadha Sutradharudu", "last_name": "Teki", "email": "jagannadh.teki@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20180810060711.6547-25-jagan@amarulasolutions.com/mbox/", "series": [ { "id": 60190, "url": "http://patchwork.ozlabs.org/api/series/60190/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=60190", "date": "2018-08-10T06:06:18", "name": "clk: Add Allwinner CLK, RESET support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/60190/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/955961/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/955961/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=amarulasolutions.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=amarulasolutions.com\n\theader.i=@amarulasolutions.com header.b=\"UR+cQTuP\"; \n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 41mw2x2BLmz9s7Q\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 10 Aug 2018 16:20:09 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid E34FAC21EA8; Fri, 10 Aug 2018 06:13:35 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id BB808C21BE5;\n\tFri, 10 Aug 2018 06:09:50 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid E2CA5C21E02; Fri, 10 Aug 2018 06:09:16 +0000 (UTC)", "from mail-pf1-f195.google.com (mail-pf1-f195.google.com\n\t[209.85.210.195])\n\tby lists.denx.de (Postfix) with ESMTPS id C899EC21D4A\n\tfor <u-boot@lists.denx.de>; Fri, 10 Aug 2018 06:09:09 +0000 (UTC)", "by mail-pf1-f195.google.com with SMTP id j8-v6so4016177pff.6\n\tfor <u-boot@lists.denx.de>; Thu, 09 Aug 2018 23:09:09 -0700 (PDT)", "from localhost.localdomain ([183.82.228.250])\n\tby smtp.gmail.com with ESMTPSA id\n\tr23-v6sm16880975pfj.5.2018.08.09.23.09.04\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tThu, 09 Aug 2018 23:09:07 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no\n\tversion=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=amarulasolutions.com; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=RRRpDXn+F7sNThQpONFc1NL0WvGaVsEKqlgB+XR4NJ8=;\n\tb=UR+cQTuPd+LBlsVK6sP2na9zxy9vaOncmp4gNtMlmPK9HVMNKw7z1p71LrWOC4gytX\n\thm0E9b4qrknutmcmhyO0cLEDSNdyjxndxrJUpIBWh0TpvB+MOblNUyBpJ6Vh7jBBHPHD\n\tOt33yECAart/dj0QcbeqKs58LagE7bkBQwxj0=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=RRRpDXn+F7sNThQpONFc1NL0WvGaVsEKqlgB+XR4NJ8=;\n\tb=tce5so0prs65EYkPosZn+bXzYOlCl3iv+JZV4ynvd3BdtfVlhuP8OF33WzrMOoIP2E\n\tITE6TwEMJE9f26jfRgVSF+/zmbLo+I92otjejmeEWYLlW7qfXcs7nwsgC/h/zGkZ8uwj\n\to0fAuifDFfXgDhtFnBGmFxC8Vum3qsyUMe0hLNLF99WvnBjgaJr6Ycrs6HRT4Rr6G3gk\n\tK80SrMtYPHSOQ/QJTblMjcZaDeNATs/vR8xi8UD05Acqr6ObQbu7nC+aDYE7s3Bb9iA0\n\t84SW4U4OTTXHYAk5VxVT+GYsfoc3N4mBba48FUw3WAr0kiQKT9GPHTPYXhypPc/O/afD\n\tVNdg==", "X-Gm-Message-State": "AOUpUlHFdxIw8h9KlBSjCYEbC2pl8cGgWU/0US7MYT3rQ57Uvv2p4aAf\n\tisR1osQ6HdLpKGXdM4v0FsbrFZvuC7w=", "X-Google-Smtp-Source": "AA+uWPwyAKUwqJIBrnZArVi2kvn0O3eJONtZVvnYz95zHXMJn63urd3aurt2+txWJ/5GUIEcJX95HA==", "X-Received": "by 2002:a63:6d0a:: with SMTP id\n\ti10-v6mr5089193pgc.215.1533881348343; \n\tThu, 09 Aug 2018 23:09:08 -0700 (PDT)", "From": "Jagan Teki <jagan@amarulasolutions.com>", "To": "Maxime Ripard <maxime.ripard@bootlin.com>,\n\tAndre Przywara <andre.przywara@arm.com>, Chen-Yu Tsai <wens@csie.org>,\n\tIcenowy Zheng <icenowy@aosc.io>", "Date": "Fri, 10 Aug 2018 11:36:42 +0530", "Message-Id": "<20180810060711.6547-25-jagan@amarulasolutions.com>", "X-Mailer": "git-send-email 2.18.0.321.gffc6fa0e3", "In-Reply-To": "<20180810060711.6547-1-jagan@amarulasolutions.com>", "References": "<20180810060711.6547-1-jagan@amarulasolutions.com>", "MIME-Version": "1.0", "Cc": "Tom Rini <trini@konsulko.com>, u-boot@lists.denx.de", "Subject": "[U-Boot] [PATCH v2 24/53] dm: mmc: sunxi: Add CLK and RESET support", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Now CLK and RESET driver for Allwinner SoC are available,\nso add the relevant operations on mmc sunxi driver.\n\nCc: Jaehoon Chung <jh80.chung@samsung.com>\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\n---\n drivers/mmc/sunxi_mmc.c | 60 +++++++++++++++++++++++++++++++----------\n 1 file changed, 46 insertions(+), 14 deletions(-)", "diff": "diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c\nindex bf82014a64..3011ec9498 100644\n--- a/drivers/mmc/sunxi_mmc.c\n+++ b/drivers/mmc/sunxi_mmc.c\n@@ -8,10 +8,12 @@\n */\n \n #include <common.h>\n+#include <clk.h>\n #include <dm.h>\n #include <errno.h>\n #include <malloc.h>\n #include <mmc.h>\n+#include <reset.h>\n #include <asm/io.h>\n #include <asm/arch/ccu.h>\n #include <asm/arch/clock.h>\n@@ -26,8 +28,12 @@ struct sunxi_mmc_plat {\n };\n \n struct sunxi_mmc_priv {\n+#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(CLK)\n+\tstruct clk mmc_clk;\n+#else\n \tunsigned mmc_no;\n \tuint32_t *mclkreg;\n+#endif\n \tunsigned fatal_err;\n \tstruct gpio_desc cd_gpio;\t/* Change Detect GPIO */\n \tint cd_inverted;\t\t/* Inverted Card Detect */\n@@ -188,6 +194,15 @@ int mmc_clk_set_rate(void *base, u32 bit, ulong rate)\n static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)\n {\n #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(CLK)\n+\tint ret;\n+\n+\tret = clk_set_rate(&priv->mmc_clk, hz);\n+\tif (ret) {\n+\t\tdev_err(dev, \"failed to set rate for mmc_clk\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn ret;\n #else\n \tif (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2))\n \t\tnew_mode = true;\n@@ -379,7 +394,7 @@ static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv,\n \t\twritel(data->blocks * data->blocksize, &priv->reg->bytecnt);\n \t}\n \n-\tdebug(\"mmc %d, cmd %d(0x%08x), arg 0x%08x\\n\", priv->mmc_no,\n+\tdebug(\"mmc cmd %d(0x%08x), arg 0x%08x\\n\",\n \t cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);\n \twritel(cmd->cmdarg, &priv->reg->arg);\n \n@@ -591,8 +606,8 @@ static int sunxi_mmc_probe(struct udevice *dev)\n \tstruct sunxi_mmc_plat *plat = dev_get_platdata(dev);\n \tstruct sunxi_mmc_priv *priv = dev_get_priv(dev);\n \tstruct mmc_config *cfg = &plat->cfg;\n-\tstruct ofnode_phandle_args args;\n-\tu32 *gate_reg;\n+\tstruct clk ahb_clk;\n+\tstruct reset_ctl reset;\n \tint bus_width, ret;\n \n \tcfg->name = dev->name;\n@@ -615,20 +630,37 @@ static int sunxi_mmc_probe(struct udevice *dev)\n \n \tpriv->reg = (void *)dev_read_addr(dev);\n \n-\t/* We don't have a sunxi clock driver so find the clock address here */\n-\tret = dev_read_phandle_with_args(dev, \"clocks\", \"#clock-cells\", 0,\n-\t\t\t\t\t 1, &args);\n-\tif (ret)\n+\tret = clk_get_by_name(dev, \"ahb\", &ahb_clk);\n+\tif (ret) {\n+\t\tdev_err(dev, \"falied to get ahb clock\\n\");\n \t\treturn ret;\n-\tpriv->mclkreg = (u32 *)ofnode_get_addr(args.node);\n+\t}\n \n-\tret = dev_read_phandle_with_args(dev, \"clocks\", \"#clock-cells\", 0,\n-\t\t\t\t\t 0, &args);\n-\tif (ret)\n+\tret = clk_get_by_name(dev, \"mmc\", &priv->mmc_clk);\n+\tif (ret) {\n+\t\tdev_err(dev, \"falied to get mmc clock\\n\");\n \t\treturn ret;\n-\tgate_reg = (u32 *)ofnode_get_addr(args.node);\n-\tsetbits_le32(gate_reg, 1 << args.args[0]);\n-\tpriv->mmc_no = args.args[0] - 8;\n+\t}\n+\n+\tret = reset_get_by_name_optional(dev, \"ahb\", &reset, true);\n+\tif (ret) {\n+\t\tdev_err(dev, \"falied to get ahb reset\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tret = clk_enable(&ahb_clk);\n+\tif (ret) {\n+\t\tdev_err(dev, \"failed to enable ahb clock\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tif (reset_valid(&reset)) {\n+\t\tret = reset_deassert(&reset);\n+\t\tif (ret) {\n+\t\t\tdev_err(dev, \"failed to deassert ahb reset\\n\");\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n \n \tret = mmc_set_mod_clk(priv, 24000000);\n \tif (ret)\n", "prefixes": [ "U-Boot", "v2", "24/53" ] }