Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/955960/?format=api
{ "id": 955960, "url": "http://patchwork.ozlabs.org/api/patches/955960/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20180810060711.6547-9-jagan@amarulasolutions.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20180810060711.6547-9-jagan@amarulasolutions.com>", "list_archive_url": null, "date": "2018-08-10T06:06:26", "name": "[U-Boot,v2,08/53] clk: sunxi: Add Allwinner A31 CLK driver", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "c5aa8bd36eafc0554b3ceff94b68feb2215287ae", "submitter": { "id": 69820, "url": "http://patchwork.ozlabs.org/api/people/69820/?format=api", "name": "Jagan Teki", "email": "jagan@amarulasolutions.com" }, "delegate": { "id": 17739, "url": "http://patchwork.ozlabs.org/api/users/17739/?format=api", "username": "jagan", "first_name": "Jagannadha Sutradharudu", "last_name": "Teki", "email": "jagannadh.teki@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20180810060711.6547-9-jagan@amarulasolutions.com/mbox/", "series": [ { "id": 60190, "url": "http://patchwork.ozlabs.org/api/series/60190/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=60190", "date": "2018-08-10T06:06:18", "name": "clk: Add Allwinner CLK, RESET support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/60190/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/955960/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/955960/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=amarulasolutions.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=amarulasolutions.com\n\theader.i=@amarulasolutions.com header.b=\"ByPx/cGv\"; \n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 41mw1n6fRrz9s7Q\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 10 Aug 2018 16:19:09 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid A6E80C21DFD; Fri, 10 Aug 2018 06:12:19 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 1FD39C21E30;\n\tFri, 10 Aug 2018 06:08:59 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 7BAE3C21DD4; Fri, 10 Aug 2018 06:08:14 +0000 (UTC)", "from mail-pg1-f195.google.com (mail-pg1-f195.google.com\n\t[209.85.215.195])\n\tby lists.denx.de (Postfix) with ESMTPS id 5B29CC21DF3\n\tfor <u-boot@lists.denx.de>; Fri, 10 Aug 2018 06:08:09 +0000 (UTC)", "by mail-pg1-f195.google.com with SMTP id f1-v6so3874319pgq.12\n\tfor <u-boot@lists.denx.de>; Thu, 09 Aug 2018 23:08:09 -0700 (PDT)", "from localhost.localdomain ([183.82.228.250])\n\tby smtp.gmail.com with ESMTPSA id\n\tr23-v6sm16880975pfj.5.2018.08.09.23.08.04\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tThu, 09 Aug 2018 23:08:07 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no\n\tversion=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=amarulasolutions.com; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=76l7F6L0KbLYey+J6r77eY6hUn6UJscCIapdLC6z3dw=;\n\tb=ByPx/cGvVx6sg6/eXiwFbCLd+pkkd/DW8/bl+AgCg15FpQhpyLsqJeB824fGeyg1bj\n\txa97Yh2uVrHUHpJtaDYUoyd+1gU/pUtpJRjopIZqtdFLFQZ6iKjryfMveH+84XslTdgz\n\tTBhBKX6lVg/uSCobmx5tMZ/Uf3zqRx/YSFPMQ=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=76l7F6L0KbLYey+J6r77eY6hUn6UJscCIapdLC6z3dw=;\n\tb=rVcYSpm5KuH8FXaDp73iC0+cRgH7wldZBXCEnAac6AvLtEicOhbU+rTxhXn4clJIui\n\tRhJWMi6XLOg5MU9y/VzEblflBbtcMOmdN/FlpdZjcrLfaxOYNG8vQO7LiwOcv7SB6fqs\n\t1doMlnuUZSs9OIx5i6pldILn5tOKlXdOMb/wcAHYUuY5TIkiFQjpF+KDN1jZQjKlO93o\n\t33jonsMCIIcxJDQH8K6QvJJGGy7+WPJrvWPAfjJ05AXNwEGpA+JnQNhHJ0JLBBiC9VyY\n\tkE3zuS6UXgNTsEP/XBnu1DakbeYV8UfYeJMKnaKkxeJfHYqMXfbn/YMA5dpa6MLY++pO\n\tfB8w==", "X-Gm-Message-State": "AOUpUlHXfSbwTDt1BlYKKBXCwxPG9qkldxGrv0GENgRjRUIWl3OwWeDq\n\tTT+NyoN3cO0UApdIU/QEmSgbzQ==", "X-Google-Smtp-Source": "AA+uWPzJykjkzsJmt4AnHPi+KTbyPg9cjCE/6wV3NQscF65trRMtCxyMimFPWW7excZP4QVAxIPJEQ==", "X-Received": "by 2002:a62:9b18:: with SMTP id\n\tr24-v6mr5543712pfd.105.1533881287898; \n\tThu, 09 Aug 2018 23:08:07 -0700 (PDT)", "From": "Jagan Teki <jagan@amarulasolutions.com>", "To": "Maxime Ripard <maxime.ripard@bootlin.com>,\n\tAndre Przywara <andre.przywara@arm.com>, Chen-Yu Tsai <wens@csie.org>,\n\tIcenowy Zheng <icenowy@aosc.io>", "Date": "Fri, 10 Aug 2018 11:36:26 +0530", "Message-Id": "<20180810060711.6547-9-jagan@amarulasolutions.com>", "X-Mailer": "git-send-email 2.18.0.321.gffc6fa0e3", "In-Reply-To": "<20180810060711.6547-1-jagan@amarulasolutions.com>", "References": "<20180810060711.6547-1-jagan@amarulasolutions.com>", "MIME-Version": "1.0", "Cc": "Tom Rini <trini@konsulko.com>, u-boot@lists.denx.de", "Subject": "[U-Boot] [PATCH v2 08/53] clk: sunxi: Add Allwinner A31 CLK driver", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Add initial clock driver for Allwinner A31.\n\n- Implement USB ahb1 and USB clocks via ccu_clk_map descriptor\n for A31, so it can accessed in common clk enable and disable\n functions from clk_sunxi.c\n- Implement USB ahb1 and USB resets via ccu_reset_map descriptor\n for A31, so it can accessed in common reset deassert and assert\n functions from reset-sunxi.c\n\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\n---\n drivers/clk/sunxi/Kconfig | 7 +++\n drivers/clk/sunxi/Makefile | 1 +\n drivers/clk/sunxi/clk_a31.c | 86 +++++++++++++++++++++++++++++++++++++\n 3 files changed, 94 insertions(+)\n create mode 100644 drivers/clk/sunxi/clk_a31.c", "diff": "diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig\nindex b228c2fa3a..535b0dc02c 100644\n--- a/drivers/clk/sunxi/Kconfig\n+++ b/drivers/clk/sunxi/Kconfig\n@@ -23,6 +23,13 @@ config CLK_SUN5I_A10S\n \t This enables common clock driver support for platforms based\n \t on Allwinner A10s/A13 SoC.\n \n+config CLK_SUN6I_A31\n+\tbool \"Clock driver for Allwinner A31/A31s\"\n+\tdefault MACH_SUN6I\n+\thelp\n+\t This enables common clock driver support for platforms based\n+\t on Allwinner A31/A31s SoC.\n+\n config CLK_SUN8I_H3\n \tbool \"Clock driver for Allwinner H3/H5\"\n \tdefault MACH_SUNXI_H3_H5\ndiff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile\nindex 466d4b79d6..3cf0071b0c 100644\n--- a/drivers/clk/sunxi/Makefile\n+++ b/drivers/clk/sunxi/Makefile\n@@ -8,5 +8,6 @@ obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o\n \n obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o\n obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o\n+obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o\n obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o\n obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o\ndiff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c\nnew file mode 100644\nindex 0000000000..c6d82be120\n--- /dev/null\n+++ b/drivers/clk/sunxi/clk_a31.c\n@@ -0,0 +1,86 @@\n+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n+/*\n+ * Copyright (C) 2018 Amarula Solutions B.V.\n+ * Author: Jagan Teki <jagan@amarulasolutions.com>\n+ */\n+\n+#include <common.h>\n+#include <clk-uclass.h>\n+#include <dm.h>\n+#include <errno.h>\n+#include <asm/arch/ccu.h>\n+#include <dt-bindings/clock/sun6i-a31-ccu.h>\n+#include <dt-bindings/reset/sun6i-a31-ccu.h>\n+\n+static struct ccu_clk_map a31_clks[] = {\n+\t[CLK_AHB1_OTG]\t\t= { 0x060, BIT(24), NULL },\n+\t[CLK_AHB1_EHCI0]\t= { 0x060, BIT(26), NULL },\n+\t[CLK_AHB1_EHCI1]\t= { 0x060, BIT(27), NULL },\n+\t[CLK_AHB1_OHCI0]\t= { 0x060, BIT(29), NULL },\n+\t[CLK_AHB1_OHCI1]\t= { 0x060, BIT(30), NULL },\n+\t[CLK_AHB1_OHCI2]\t= { 0x060, BIT(31), NULL },\n+\n+\t[CLK_USB_PHY0]\t\t= { 0x0cc, BIT(8), NULL },\n+\t[CLK_USB_PHY1]\t\t= { 0x0cc, BIT(9), NULL },\n+\t[CLK_USB_PHY2]\t\t= { 0x0cc, BIT(10), NULL },\n+\t[CLK_USB_OHCI0]\t\t= { 0x0cc, BIT(16), NULL },\n+\t[CLK_USB_OHCI1]\t\t= { 0x0cc, BIT(17), NULL },\n+\t[CLK_USB_OHCI2]\t\t= { 0x0cc, BIT(18), NULL },\n+};\n+\n+static struct ccu_reset_map a31_resets[] = {\n+\t[RST_USB_PHY0]\t\t= { 0x0cc, BIT(0) },\n+\t[RST_USB_PHY1]\t\t= { 0x0cc, BIT(1) },\n+\t[RST_USB_PHY2]\t\t= { 0x0cc, BIT(2) },\n+\n+\t[RST_AHB1_OTG]\t\t= { 0x2c0, BIT(24) },\n+\t[RST_AHB1_EHCI0]\t= { 0x2c0, BIT(26) },\n+\t[RST_AHB1_EHCI1]\t= { 0x2c0, BIT(27) },\n+\t[RST_AHB1_OHCI0]\t= { 0x2c0, BIT(29) },\n+\t[RST_AHB1_OHCI1]\t= { 0x2c0, BIT(30) },\n+\t[RST_AHB1_OHCI2]\t= { 0x2c0, BIT(31) },\n+};\n+\n+static const struct ccu_desc sun6i_a31_ccu_desc = {\n+\t.clks = a31_clks,\n+\t.num_clks = ARRAY_SIZE(a31_clks),\n+\n+\t.resets = a31_resets,\n+\t.num_resets = ARRAY_SIZE(a31_resets),\n+};\n+\n+static int a31_clk_probe(struct udevice *dev)\n+{\n+\tstruct sunxi_clk_priv *priv = dev_get_priv(dev);\n+\n+\tpriv->base = dev_read_addr_ptr(dev);\n+\tif (!priv->base)\n+\t\treturn -ENOMEM;\n+\n+\tpriv->desc = (const struct ccu_desc *)dev_get_driver_data(dev);\n+\tif (!priv->desc)\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n+static int a31_clk_bind(struct udevice *dev)\n+{\n+\treturn sunxi_reset_bind(dev, 56);\n+}\n+\n+static const struct udevice_id a31_clk_ids[] = {\n+\t{ .compatible = \"allwinner,sun6i-a31-ccu\",\n+\t .data = (ulong)&sun6i_a31_ccu_desc },\n+\t{ }\n+};\n+\n+U_BOOT_DRIVER(clk_sun6i_a31) = {\n+\t.name\t\t= \"sun6i_a31_ccu\",\n+\t.id\t\t= UCLASS_CLK,\n+\t.of_match\t= a31_clk_ids,\n+\t.priv_auto_alloc_size\t= sizeof(struct sunxi_clk_priv),\n+\t.ops\t\t= &sunxi_clk_ops,\n+\t.probe\t\t= a31_clk_probe,\n+\t.bind\t\t= a31_clk_bind,\n+};\n", "prefixes": [ "U-Boot", "v2", "08/53" ] }