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GET /api/patches/955945/?format=api
{ "id": 955945, "url": "http://patchwork.ozlabs.org/api/patches/955945/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20180810060711.6547-5-jagan@amarulasolutions.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20180810060711.6547-5-jagan@amarulasolutions.com>", "list_archive_url": null, "date": "2018-08-10T06:06:22", "name": "[U-Boot,v2,04/53] reset: Add Allwinner RESET driver", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "73b23331cf5db0dab3a0572fd29b2023fd872a8e", "submitter": { "id": 69820, "url": "http://patchwork.ozlabs.org/api/people/69820/?format=api", "name": "Jagan Teki", "email": "jagan@amarulasolutions.com" }, "delegate": { "id": 17739, "url": "http://patchwork.ozlabs.org/api/users/17739/?format=api", "username": "jagan", "first_name": "Jagannadha Sutradharudu", "last_name": "Teki", "email": "jagannadh.teki@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20180810060711.6547-5-jagan@amarulasolutions.com/mbox/", "series": [ { "id": 60190, "url": "http://patchwork.ozlabs.org/api/series/60190/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=60190", "date": "2018-08-10T06:06:18", "name": "clk: Add Allwinner CLK, RESET support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/60190/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/955945/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/955945/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=amarulasolutions.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=amarulasolutions.com\n\theader.i=@amarulasolutions.com header.b=\"YBvPP/st\"; \n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 41mvsf21FLz9s7Q\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 10 Aug 2018 16:12:06 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid BAAA6C21E18; Fri, 10 Aug 2018 06:09:21 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 5C681C21CB6;\n\tFri, 10 Aug 2018 06:08:11 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 44006C21C27; Fri, 10 Aug 2018 06:08:00 +0000 (UTC)", "from mail-pg1-f195.google.com (mail-pg1-f195.google.com\n\t[209.85.215.195])\n\tby lists.denx.de (Postfix) with ESMTPS id 868BEC21C57\n\tfor <u-boot@lists.denx.de>; Fri, 10 Aug 2018 06:07:54 +0000 (UTC)", "by mail-pg1-f195.google.com with SMTP id y4-v6so3882391pgp.9\n\tfor <u-boot@lists.denx.de>; Thu, 09 Aug 2018 23:07:54 -0700 (PDT)", "from localhost.localdomain ([183.82.228.250])\n\tby smtp.gmail.com with ESMTPSA id\n\tr23-v6sm16880975pfj.5.2018.08.09.23.07.49\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tThu, 09 Aug 2018 23:07:52 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no\n\tversion=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=amarulasolutions.com; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=TMh88YKTQb1KwF8cseETmFtVdDh2DflXCKnykeVZLlQ=;\n\tb=YBvPP/stR0407aaPUlcpVL/RtMfDcJa2tdMQkk+flMFK+dNWYD2nQQhHYxzWEnjkod\n\t7x6+xtwwRPeoryl2tOiJuwNZ5LVSBbGQBfM3tR1LdMrm+XZM5GErIYE90LeDQcWi9hoU\n\t++wgs9ochA+YTHlWZl8IDcxT3UBkyiFb669sY=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=TMh88YKTQb1KwF8cseETmFtVdDh2DflXCKnykeVZLlQ=;\n\tb=mjI47w9JZfPrZ8hp1ugtlCl35l5hPxE4paQp6YInc99tEZgPSAxUokGQ3yR5F+F74V\n\tf5dUT/a/OzXaF/Yr3BSbVIl4KjrPzeKPhhfbwUaHWLhcsCQhajxpU0yvH6W8Iiz8v7CM\n\tqTq+zHnxnbsWiL9/kQo6a4IYfjaYrvyy+/Qs84gUUezquhsXKzF7+FdnWXHrWsM8FSQZ\n\t35abXUacXVc2B2POb+J1TgCp2JtCKXjw+uWX3x2CrE6ytmPvLdsigMEPg21DEaDzktYV\n\t4tTmaxi+eeDb6E3llWBXbwPpj31kf9EYaFdWDguhSuas8yl17fwrMg2sEfiIzZDY6d8X\n\tvrfw==", "X-Gm-Message-State": "AOUpUlGmCKKFwJQVnqlU9/9k5cRatc9lqscAigZ26kyKZCO2FM+2AmxV\n\tLAf78O08wnHwcQLdkDd8VnuCWg==", "X-Google-Smtp-Source": "AA+uWPxisyBTHb6jcYQc0tSNz4NDe11cGJK5eHVAa3O9DXPPwTSJSpKcto7I3lOKNa3NR3EKB4KgxA==", "X-Received": "by 2002:a63:e001:: with SMTP id\n\te1-v6mr2458528pgh.380.1533881273077; \n\tThu, 09 Aug 2018 23:07:53 -0700 (PDT)", "From": "Jagan Teki <jagan@amarulasolutions.com>", "To": "Maxime Ripard <maxime.ripard@bootlin.com>,\n\tAndre Przywara <andre.przywara@arm.com>, Chen-Yu Tsai <wens@csie.org>,\n\tIcenowy Zheng <icenowy@aosc.io>", "Date": "Fri, 10 Aug 2018 11:36:22 +0530", "Message-Id": "<20180810060711.6547-5-jagan@amarulasolutions.com>", "X-Mailer": "git-send-email 2.18.0.321.gffc6fa0e3", "In-Reply-To": "<20180810060711.6547-1-jagan@amarulasolutions.com>", "References": "<20180810060711.6547-1-jagan@amarulasolutions.com>", "MIME-Version": "1.0", "Cc": "Tom Rini <trini@konsulko.com>, u-boot@lists.denx.de", "Subject": "[U-Boot] [PATCH v2 04/53] reset: Add Allwinner RESET driver", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Add common reset driver for all Allwinner SoC's.\n\nSince CLK and RESET share common DT compatible, it is CLK driver\njob is to bind the reset driver. So add CLK bind call on respective\nSoC driver by passing ccu map descriptor so-that reset deassert,\ndeassert operations held based on reset register map defined by\nCLK driver.\n\nSelect DM_RESET via CLK_SUNXI, this make hidden section of RESET\nsince CLK and RESET share common DT compatible and code.\n\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\n---\n arch/arm/include/asm/arch-sunxi/ccu.h | 25 ++++++\n drivers/clk/sunxi/Kconfig | 1 +\n drivers/clk/sunxi/clk_a64.c | 22 +++++\n drivers/reset/Kconfig | 8 ++\n drivers/reset/Makefile | 1 +\n drivers/reset/reset-sunxi.c | 124 ++++++++++++++++++++++++++\n 6 files changed, 181 insertions(+)\n create mode 100644 drivers/reset/reset-sunxi.c", "diff": "diff --git a/arch/arm/include/asm/arch-sunxi/ccu.h b/arch/arm/include/asm/arch-sunxi/ccu.h\nindex f628c893de..bacd052ef3 100644\n--- a/arch/arm/include/asm/arch-sunxi/ccu.h\n+++ b/arch/arm/include/asm/arch-sunxi/ccu.h\n@@ -20,15 +20,31 @@ struct ccu_clk_map {\n \tint (*ccu_clk_set_rate)(void *base, u32 bit, ulong rate);\n };\n \n+/**\n+ * ccu_reset_map - common clock unit reset map\n+ *\n+ * @off:\tccu reset offset\n+ * @bit:\tccu reset bit value\n+ */\n+struct ccu_reset_map {\n+\tu16 off;\n+\tu32 bit;\n+};\n+\n /**\n * struct ccu_desc - common clock unit descriptor\n *\n * @clks:\t\tmapping clocks descriptor\n * @num_clks:\t\tnumber of mapped clocks\n+ * @resets:\t\tmapping resets descriptor\n+ * @num_resets:\t\tnumber of mapped resets\n */\n struct ccu_desc {\n \tstruct ccu_clk_map *clks;\n \tunsigned long num_clks;\n+\n+\tstruct ccu_reset_map *resets;\n+\tunsigned long num_resets;\n };\n \n /**\n@@ -44,4 +60,13 @@ struct sunxi_clk_priv {\n \n extern struct clk_ops sunxi_clk_ops;\n \n+/**\n+ * sunxi_reset_bind() - reset binding\n+ *\n+ * @dev:\treset device\n+ * @count:\treset count\n+ * @return 0 success, or error value\n+ */\n+int sunxi_reset_bind(struct udevice *dev, ulong count);\n+\n #endif /* _ASM_ARCH_CCU_H */\ndiff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig\nindex bf5ecb3801..041d711e58 100644\n--- a/drivers/clk/sunxi/Kconfig\n+++ b/drivers/clk/sunxi/Kconfig\n@@ -1,6 +1,7 @@\n config CLK_SUNXI\n \tbool \"Clock support for Allwinner SoCs\"\n \tdepends on CLK && ARCH_SUNXI\n+\tselect DM_RESET\n \tdefault y\n \thelp\n \t This enables support for common clock driver API on Allwinner\ndiff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c\nindex 9393a01ccf..e5257b62c7 100644\n--- a/drivers/clk/sunxi/clk_a64.c\n+++ b/drivers/clk/sunxi/clk_a64.c\n@@ -10,6 +10,7 @@\n #include <errno.h>\n #include <asm/arch/ccu.h>\n #include <dt-bindings/clock/sun50i-a64-ccu.h>\n+#include <dt-bindings/reset/sun50i-a64-ccu.h>\n \n static struct ccu_clk_map a64_clks[] = {\n \t[CLK_BUS_OTG]\t\t= { 0x060, BIT(23), NULL },\n@@ -26,9 +27,24 @@ static struct ccu_clk_map a64_clks[] = {\n \t[CLK_USB_OHCI1]\t\t= { 0x0cc, BIT(17), NULL },\n };\n \n+static struct ccu_reset_map a64_resets[] = {\n+\t[RST_USB_PHY0]\t\t= { 0x0cc, BIT(0) },\n+\t[RST_USB_PHY1]\t\t= { 0x0cc, BIT(1) },\n+\t[RST_USB_HSIC]\t\t= { 0x0cc, BIT(2) },\n+\n+\t[RST_BUS_OTG]\t\t= { 0x2c0, BIT(23) },\n+\t[RST_BUS_EHCI0]\t\t= { 0x2c0, BIT(24) },\n+\t[RST_BUS_EHCI1]\t\t= { 0x2c0, BIT(25) },\n+\t[RST_BUS_OHCI0]\t\t= { 0x2c0, BIT(28) },\n+\t[RST_BUS_OHCI1]\t\t= { 0x2c0, BIT(29) },\n+};\n+\n static const struct ccu_desc sun50i_a64_ccu_desc = {\n \t.clks = a64_clks,\n \t.num_clks = ARRAY_SIZE(a64_clks),\n+\n+\t.resets = a64_resets,\n+\t.num_resets = ARRAY_SIZE(a64_resets),\n };\n \n static int a64_clk_probe(struct udevice *dev)\n@@ -46,6 +62,11 @@ static int a64_clk_probe(struct udevice *dev)\n \treturn 0;\n }\n \n+static int a64_clk_bind(struct udevice *dev)\n+{\n+\treturn sunxi_reset_bind(dev, 50);\n+}\n+\n static const struct udevice_id a64_clk_ids[] = {\n \t{ .compatible = \"allwinner,sun50i-a64-ccu\",\n \t .data = (ulong)&sun50i_a64_ccu_desc },\n@@ -59,4 +80,5 @@ U_BOOT_DRIVER(clk_sun50i_a64) = {\n \t.priv_auto_alloc_size\t= sizeof(struct sunxi_clk_priv),\n \t.ops\t\t= &sunxi_clk_ops,\n \t.probe\t\t= a64_clk_probe,\n+\t.bind\t\t= a64_clk_bind,\n };\ndiff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig\nindex 33c39b7fb6..bdc06564a0 100644\n--- a/drivers/reset/Kconfig\n+++ b/drivers/reset/Kconfig\n@@ -98,4 +98,12 @@ config RESET_SOCFPGA\n \thelp\n \t Support for reset controller on SoCFPGA platform.\n \n+config RESET_SUNXI\n+\tbool \"RESET support for Allwinner SoCs\"\n+\tdepends on DM_RESET && ARCH_SUNXI\n+\tdefault y\n+\thelp\n+\t This enables support for common reset driver for\n+\t Allwinner SoCs.\n+\n endmenu\ndiff --git a/drivers/reset/Makefile b/drivers/reset/Makefile\nindex ad08be4c8c..698d15a0e0 100644\n--- a/drivers/reset/Makefile\n+++ b/drivers/reset/Makefile\n@@ -15,3 +15,4 @@ obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o\n obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o\n obj-$(CONFIG_RESET_MESON) += reset-meson.o\n obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o\n+obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o\ndiff --git a/drivers/reset/reset-sunxi.c b/drivers/reset/reset-sunxi.c\nnew file mode 100644\nindex 0000000000..c0abe41bec\n--- /dev/null\n+++ b/drivers/reset/reset-sunxi.c\n@@ -0,0 +1,124 @@\n+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n+/*\n+ * Copyright (C) 2018 Amarula Solutions.\n+ * Author: Jagan Teki <jagan@amarulasolutions.com>\n+ */\n+\n+#include <common.h>\n+#include <dm.h>\n+#include <errno.h>\n+#include <reset-uclass.h>\n+#include <asm/io.h>\n+#include <dm/lists.h>\n+#include <linux/log2.h>\n+#include <asm/arch/ccu.h>\n+\n+struct sunxi_reset_priv {\n+\tvoid *base;\n+\tulong count;\n+\tconst struct ccu_desc *desc;\n+};\n+\n+static int sunxi_reset_request(struct reset_ctl *reset_ctl)\n+{\n+\tstruct sunxi_reset_priv *priv = dev_get_priv(reset_ctl->dev);\n+\n+\tdebug(\"%s (RST#%ld)\\n\", __func__, reset_ctl->id);\n+\n+\t/* check dt-bindings/reset/sun8i-h3-ccu.h for max id */\n+\tif (reset_ctl->id >= priv->count)\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n+static int sunxi_reset_free(struct reset_ctl *reset_ctl)\n+{\n+\tdebug(\"%s (RST#%ld)\\n\", __func__, reset_ctl->id);\n+\n+\treturn 0;\n+}\n+\n+static int sunxi_reset_assert(struct reset_ctl *reset_ctl)\n+{\n+\tstruct sunxi_reset_priv *priv = dev_get_priv(reset_ctl->dev);\n+\tstruct ccu_reset_map *map = &priv->desc->resets[reset_ctl->id];\n+\tu32 reg;\n+\n+\tif (!map->off || !map->bit) {\n+\t\tdebug(\"%s (RST#%ld) unhandled\\n\", __func__, reset_ctl->id);\n+\t\treturn 0;\n+\t}\n+\n+\tdebug(\"%s(#%ld) off#0x%x, BIT(%d)\\n\", __func__,\n+\t reset_ctl->id, map->off, ilog2(map->bit));\n+\n+\treg = readl(priv->base + map->off);\n+\twritel(reg & ~map->bit, priv->base + map->off);\n+\n+\treturn 0;\n+}\n+\n+static int sunxi_reset_deassert(struct reset_ctl *reset_ctl)\n+{\n+\tstruct sunxi_reset_priv *priv = dev_get_priv(reset_ctl->dev);\n+\tstruct ccu_reset_map *map = &priv->desc->resets[reset_ctl->id];\n+\tu32 reg;\n+\n+\tif (!map->off || !map->bit) {\n+\t\tdebug(\"%s (RST#%ld) unhandled\\n\", __func__, reset_ctl->id);\n+\t\treturn 0;\n+\t}\n+\n+\tdebug(\"%s(#%ld) off#0x%x, BIT(%d)\\n\", __func__,\n+\t reset_ctl->id, map->off, ilog2(map->bit));\n+\n+\treg = readl(priv->base + map->off);\n+\twritel(reg | map->bit, priv->base + map->off);\n+\n+\treturn 0;\n+}\n+\n+struct reset_ops sunxi_reset_ops = {\n+\t.request = sunxi_reset_request,\n+\t.free = sunxi_reset_free,\n+\t.rst_assert = sunxi_reset_assert,\n+\t.rst_deassert = sunxi_reset_deassert,\n+};\n+\n+static int sunxi_reset_probe(struct udevice *dev)\n+{\n+\tstruct sunxi_reset_priv *priv = dev_get_priv(dev);\n+\n+\tpriv->base = dev_read_addr_ptr(dev);\n+\n+\treturn 0;\n+}\n+\n+int sunxi_reset_bind(struct udevice *dev, ulong count)\n+{\n+\tstruct udevice *rst_dev;\n+\tstruct sunxi_reset_priv *priv;\n+\tint ret;\n+\n+\tret = device_bind_driver_to_node(dev, \"sunxi_reset\", \"reset\",\n+\t\t\t\t\t dev_ofnode(dev), &rst_dev);\n+\tif (ret) {\n+\t\tdebug(\"Warning: failed to bind sunxi_reset driver: ret=%d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\tpriv = malloc(sizeof(struct sunxi_reset_priv));\n+\tpriv->count = count;\n+\tpriv->desc = (const struct ccu_desc *)dev_get_driver_data(dev);\n+\trst_dev->priv = priv;\n+\n+\treturn 0;\n+}\n+\n+U_BOOT_DRIVER(reset_sun8i_h3) = {\n+\t.name\t\t= \"sunxi_reset\",\n+\t.id\t\t= UCLASS_RESET,\n+\t.ops\t\t= &sunxi_reset_ops,\n+\t.probe\t\t= sunxi_reset_probe,\n+\t.priv_auto_alloc_size = sizeof(struct sunxi_reset_priv),\n+};\n", "prefixes": [ "U-Boot", "v2", "04/53" ] }