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GET /api/patches/955944/?format=api
{ "id": 955944, "url": "http://patchwork.ozlabs.org/api/patches/955944/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20180810060711.6547-3-jagan@amarulasolutions.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20180810060711.6547-3-jagan@amarulasolutions.com>", "list_archive_url": null, "date": "2018-08-10T06:06:20", "name": "[U-Boot,v2,02/53] clk: Add Allwinner A64 CLK driver", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "e740a533909fe378c364d4d56a0fd1cf8fcd67c9", "submitter": { "id": 69820, "url": "http://patchwork.ozlabs.org/api/people/69820/?format=api", "name": "Jagan Teki", "email": "jagan@amarulasolutions.com" }, "delegate": { "id": 17739, "url": "http://patchwork.ozlabs.org/api/users/17739/?format=api", "username": "jagan", "first_name": "Jagannadha Sutradharudu", "last_name": "Teki", "email": "jagannadh.teki@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20180810060711.6547-3-jagan@amarulasolutions.com/mbox/", "series": [ { "id": 60190, "url": "http://patchwork.ozlabs.org/api/series/60190/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=60190", "date": "2018-08-10T06:06:18", "name": "clk: Add Allwinner CLK, RESET support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/60190/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/955944/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/955944/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=amarulasolutions.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=amarulasolutions.com\n\theader.i=@amarulasolutions.com header.b=\"BOz24HgV\"; \n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 41mvqp09Rxz9s7Q\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 10 Aug 2018 16:10:29 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid A496BC21E77; Fri, 10 Aug 2018 06:08:34 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 0570DC21DD9;\n\tFri, 10 Aug 2018 06:08:03 +0000 (UTC)", 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<maxime.ripard@bootlin.com>,\n\tAndre Przywara <andre.przywara@arm.com>, Chen-Yu Tsai <wens@csie.org>,\n\tIcenowy Zheng <icenowy@aosc.io>", "Date": "Fri, 10 Aug 2018 11:36:20 +0530", "Message-Id": "<20180810060711.6547-3-jagan@amarulasolutions.com>", "X-Mailer": "git-send-email 2.18.0.321.gffc6fa0e3", "In-Reply-To": "<20180810060711.6547-1-jagan@amarulasolutions.com>", "References": "<20180810060711.6547-1-jagan@amarulasolutions.com>", "MIME-Version": "1.0", "Cc": "Tom Rini <trini@konsulko.com>, u-boot@lists.denx.de", "Subject": "[U-Boot] [PATCH v2 02/53] clk: Add Allwinner A64 CLK driver", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Add initial clock driver for Allwinner A64.\n\nImplement USB clock enable and disable functions for\nOHCI, EHCI, OTG and USBPHY gate and clock registers.\n\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\n---\n arch/arm/include/asm/arch-sunxi/ccu.h | 47 ++++++++++++++++++++\n drivers/clk/Kconfig | 1 +\n drivers/clk/Makefile | 1 +\n drivers/clk/sunxi/Kconfig | 18 ++++++++\n drivers/clk/sunxi/Makefile | 9 ++++\n drivers/clk/sunxi/clk_a64.c | 62 +++++++++++++++++++++++++++\n drivers/clk/sunxi/clk_sunxi.c | 58 +++++++++++++++++++++++++\n 7 files changed, 196 insertions(+)\n create mode 100644 arch/arm/include/asm/arch-sunxi/ccu.h\n create mode 100644 drivers/clk/sunxi/Kconfig\n create mode 100644 drivers/clk/sunxi/Makefile\n create mode 100644 drivers/clk/sunxi/clk_a64.c\n create mode 100644 drivers/clk/sunxi/clk_sunxi.c", "diff": "diff --git a/arch/arm/include/asm/arch-sunxi/ccu.h b/arch/arm/include/asm/arch-sunxi/ccu.h\nnew file mode 100644\nindex 0000000000..f628c893de\n--- /dev/null\n+++ b/arch/arm/include/asm/arch-sunxi/ccu.h\n@@ -0,0 +1,47 @@\n+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n+/*\n+ * Copyright (C) 2018 Amarula Solutions.\n+ * Author: Jagan Teki <jagan@amarulasolutions.com>\n+ */\n+\n+#ifndef _ASM_ARCH_CCU_H\n+#define _ASM_ARCH_CCU_H\n+\n+/**\n+ * ccu_clk_map - common clock unit clock map\n+ *\n+ * @off:\t\tccu clock offset\n+ * @bit:\t\tccu clock bit value\n+ * @ccu_clk_set_rate:\tccu clock set rate func\n+ */\n+struct ccu_clk_map {\n+\tu16 off;\n+\tu32 bit;\n+\tint (*ccu_clk_set_rate)(void *base, u32 bit, ulong rate);\n+};\n+\n+/**\n+ * struct ccu_desc - common clock unit descriptor\n+ *\n+ * @clks:\t\tmapping clocks descriptor\n+ * @num_clks:\t\tnumber of mapped clocks\n+ */\n+struct ccu_desc {\n+\tstruct ccu_clk_map *clks;\n+\tunsigned long num_clks;\n+};\n+\n+/**\n+ * struct sunxi_clk_priv - sunxi clock private structure\n+ *\n+ * @base:\tbase address\n+ * @desc:\tccu descriptor\n+ */\n+struct sunxi_clk_priv {\n+\tvoid *base;\n+\tconst struct ccu_desc *desc;\n+};\n+\n+extern struct clk_ops sunxi_clk_ops;\n+\n+#endif /* _ASM_ARCH_CCU_H */\ndiff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig\nindex a99abed9e9..b4992e9ff1 100644\n--- a/drivers/clk/Kconfig\n+++ b/drivers/clk/Kconfig\n@@ -88,6 +88,7 @@ source \"drivers/clk/exynos/Kconfig\"\n source \"drivers/clk/mvebu/Kconfig\"\n source \"drivers/clk/owl/Kconfig\"\n source \"drivers/clk/renesas/Kconfig\"\n+source \"drivers/clk/sunxi/Kconfig\"\n source \"drivers/clk/tegra/Kconfig\"\n source \"drivers/clk/uniphier/Kconfig\"\n \ndiff --git a/drivers/clk/Makefile b/drivers/clk/Makefile\nindex 146283c723..7cefcd99a0 100644\n--- a/drivers/clk/Makefile\n+++ b/drivers/clk/Makefile\n@@ -11,6 +11,7 @@ obj-y += tegra/\n obj-$(CONFIG_ARCH_ASPEED) += aspeed/\n obj-$(CONFIG_ARCH_MESON) += clk_meson.o\n obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/\n+obj-$(CONFIG_ARCH_SUNXI) += sunxi/\n obj-$(CONFIG_CLK_AT91) += at91/\n obj-$(CONFIG_CLK_MVEBU) += mvebu/\n obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o\ndiff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig\nnew file mode 100644\nindex 0000000000..bf5ecb3801\n--- /dev/null\n+++ b/drivers/clk/sunxi/Kconfig\n@@ -0,0 +1,18 @@\n+config CLK_SUNXI\n+\tbool \"Clock support for Allwinner SoCs\"\n+\tdepends on CLK && ARCH_SUNXI\n+\tdefault y\n+\thelp\n+\t This enables support for common clock driver API on Allwinner\n+\t SoCs.\n+\n+if CLK_SUNXI\n+\n+config CLK_SUN50I_A64\n+\tbool \"Clock driver for Allwinner A64\"\n+\tdefault MACH_SUN50I\n+\thelp\n+\t This enables common clock driver support for platforms based\n+\t on Allwinner A64 SoC.\n+\n+endif # CLK_SUNXI\ndiff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile\nnew file mode 100644\nindex 0000000000..fb20d28333\n--- /dev/null\n+++ b/drivers/clk/sunxi/Makefile\n@@ -0,0 +1,9 @@\n+#\n+# Copyright (C) 2018 Amarula Solutions.\n+#\n+# SPDX-License-Identifier: GPL-2.0+\n+#\n+\n+obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o\n+\n+obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o\ndiff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c\nnew file mode 100644\nindex 0000000000..9393a01ccf\n--- /dev/null\n+++ b/drivers/clk/sunxi/clk_a64.c\n@@ -0,0 +1,62 @@\n+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n+/*\n+ * Copyright (C) 2018 Amarula Solutions.\n+ * Author: Jagan Teki <jagan@amarulasolutions.com>\n+ */\n+\n+#include <common.h>\n+#include <clk-uclass.h>\n+#include <dm.h>\n+#include <errno.h>\n+#include <asm/arch/ccu.h>\n+#include <dt-bindings/clock/sun50i-a64-ccu.h>\n+\n+static struct ccu_clk_map a64_clks[] = {\n+\t[CLK_BUS_OTG]\t\t= { 0x060, BIT(23), NULL },\n+\t[CLK_BUS_EHCI0]\t\t= { 0x060, BIT(24), NULL },\n+\t[CLK_BUS_EHCI1]\t\t= { 0x060, BIT(25), NULL },\n+\t[CLK_BUS_OHCI0]\t\t= { 0x060, BIT(28), NULL },\n+\t[CLK_BUS_OHCI1]\t\t= { 0x060, BIT(29), NULL },\n+\n+\t[CLK_USB_PHY0]\t\t= { 0x0cc, BIT(8), NULL },\n+\t[CLK_USB_PHY1]\t\t= { 0x0cc, BIT(9), NULL },\n+\t[CLK_USB_HSIC]\t\t= { 0x0cc, BIT(10), NULL },\n+\t[CLK_USB_HSIC_12M]\t= { 0x0cc, BIT(11), NULL },\n+\t[CLK_USB_OHCI0]\t\t= { 0x0cc, BIT(16), NULL },\n+\t[CLK_USB_OHCI1]\t\t= { 0x0cc, BIT(17), NULL },\n+};\n+\n+static const struct ccu_desc sun50i_a64_ccu_desc = {\n+\t.clks = a64_clks,\n+\t.num_clks = ARRAY_SIZE(a64_clks),\n+};\n+\n+static int a64_clk_probe(struct udevice *dev)\n+{\n+\tstruct sunxi_clk_priv *priv = dev_get_priv(dev);\n+\n+\tpriv->base = dev_read_addr_ptr(dev);\n+\tif (!priv->base)\n+\t\treturn -ENOMEM;\n+\n+\tpriv->desc = (const struct ccu_desc *)dev_get_driver_data(dev);\n+\tif (!priv->desc)\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n+static const struct udevice_id a64_clk_ids[] = {\n+\t{ .compatible = \"allwinner,sun50i-a64-ccu\",\n+\t .data = (ulong)&sun50i_a64_ccu_desc },\n+\t{ }\n+};\n+\n+U_BOOT_DRIVER(clk_sun50i_a64) = {\n+\t.name\t\t= \"sun50i_a64_ccu\",\n+\t.id\t\t= UCLASS_CLK,\n+\t.of_match\t= a64_clk_ids,\n+\t.priv_auto_alloc_size\t= sizeof(struct sunxi_clk_priv),\n+\t.ops\t\t= &sunxi_clk_ops,\n+\t.probe\t\t= a64_clk_probe,\n+};\ndiff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c\nnew file mode 100644\nindex 0000000000..791b1ac7f2\n--- /dev/null\n+++ b/drivers/clk/sunxi/clk_sunxi.c\n@@ -0,0 +1,58 @@\n+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n+/*\n+ * Copyright (C) 2018 Amarula Solutions.\n+ * Author: Jagan Teki <jagan@amarulasolutions.com>\n+ */\n+\n+#include <common.h>\n+#include <clk-uclass.h>\n+#include <dm.h>\n+#include <errno.h>\n+#include <asm/io.h>\n+#include <asm/arch/ccu.h>\n+#include <linux/log2.h>\n+\n+static int sunxi_clk_enable(struct clk *clk)\n+{\n+\tstruct sunxi_clk_priv *priv = dev_get_priv(clk->dev);\n+\tstruct ccu_clk_map *map = &priv->desc->clks[clk->id];\n+\tu32 reg;\n+\n+\tif (!map->off || !map->bit) {\n+\t\tdebug(\"%s (CLK#%ld) unhandled\\n\", __func__, clk->id);\n+\t\treturn 0;\n+\t}\n+\n+\tdebug(\"%s(#%ld) off#0x%x, BIT(%d)\\n\", __func__,\n+\t clk->id, map->off, ilog2(map->bit));\n+\n+\treg = readl(priv->base + map->off);\n+\twritel(reg | map->bit, priv->base + map->off);\n+\n+\treturn 0;\n+}\n+\n+static int sunxi_clk_disable(struct clk *clk)\n+{\n+\tstruct sunxi_clk_priv *priv = dev_get_priv(clk->dev);\n+\tstruct ccu_clk_map *map = &priv->desc->clks[clk->id];\n+\tu32 reg;\n+\n+\tif (!map->off || !map->bit) {\n+\t\tdebug(\"%s (CLK#%ld) unhandled\\n\", __func__, clk->id);\n+\t\treturn 0;\n+\t}\n+\n+\tdebug(\"%s(#%ld) off#0x%x, BIT(%d)\\n\", __func__,\n+\t clk->id, map->off, ilog2(map->bit));\n+\n+\treg = readl(priv->base + map->off);\n+\twritel(reg & ~map->bit, priv->base + map->off);\n+\n+\treturn 0;\n+}\n+\n+struct clk_ops sunxi_clk_ops = {\n+\t.enable = sunxi_clk_enable,\n+\t.disable = sunxi_clk_disable,\n+};\n", "prefixes": [ "U-Boot", "v2", "02/53" ] }