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GET /api/patches/954099/?format=api
{ "id": 954099, "url": "http://patchwork.ozlabs.org/api/patches/954099/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-46-git-send-email-aleksandar.markovic@rt-rk.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1533574847-19294-46-git-send-email-aleksandar.markovic@rt-rk.com>", "list_archive_url": null, "date": "2018-08-06T17:00:12", "name": "[v7,45/80] disas: Add support for microMIPS and nanoMIPS", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "1e278581aba6050da9a160f7b5fa6eefe956104c", "submitter": { "id": 68635, "url": "http://patchwork.ozlabs.org/api/people/68635/?format=api", "name": "Aleksandar Markovic", "email": "aleksandar.markovic@rt-rk.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-46-git-send-email-aleksandar.markovic@rt-rk.com/mbox/", "series": [ { "id": 59520, "url": "http://patchwork.ozlabs.org/api/series/59520/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=59520", "date": "2018-08-06T16:59:27", "name": "Add nanoMIPS support to QEMU", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/59520/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/954099/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/954099/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=rt-rk.com" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 41klm93BJbz9s3q\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 7 Aug 2018 03:59:53 +1000 (AEST)", "from localhost ([::1]:35488 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1fmjnK-0004oJ-Ry\n\tfor incoming@patchwork.ozlabs.org; Mon, 06 Aug 2018 13:59:50 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:36525)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmjB8-0002EF-Mc\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:21:17 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmjAK-0003Qp-H7\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:20:22 -0400", "from mx2.rt-rk.com ([89.216.37.149]:59965 helo=mail.rt-rk.com)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <aleksandar.markovic@rt-rk.com>)\n\tid 1fmjAI-0003PK-8l\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:19:32 -0400", "from localhost (localhost [127.0.0.1])\n\tby mail.rt-rk.com (Postfix) with ESMTP id 060E81A20DD;\n\tMon, 6 Aug 2018 19:19:29 +0200 (CEST)", "from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local\n\t[10.10.13.43])\n\tby mail.rt-rk.com (Postfix) with ESMTPSA id 591811A2036;\n\tMon, 6 Aug 2018 19:19:28 +0200 (CEST)" ], "X-Virus-Scanned": "amavisd-new at rt-rk.com", "From": "Aleksandar Markovic <aleksandar.markovic@rt-rk.com>", "To": "qemu-devel@nongnu.org", "Date": "Mon, 6 Aug 2018 19:00:12 +0200", "Message-Id": "<1533574847-19294-46-git-send-email-aleksandar.markovic@rt-rk.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "References": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 3.x [fuzzy]", "X-Received-From": "89.216.37.149", "X-Mailman-Approved-At": "Mon, 06 Aug 2018 13:45:46 -0400", "Subject": "[Qemu-devel] [PATCH v7 45/80] disas: Add support for microMIPS and\n\tnanoMIPS", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, thuth@redhat.com, pburton@wavecomp.com,\n\tsmarkovic@wavecomp.com, riku.voipio@iki.fi,\n\trichard.henderson@linaro.org, laurent@vivier.eu,\n\tarmbru@redhat.com, arikalo@wavecomp.com,\n\tphilippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com,\n\tpjovanovic@wavecomp.com, aurelien@aurel32.net", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Matthew Fortune <matthew.fortune@mips.com>\n\nModify disassembler engine to execute a separate disassembler\nfor microMIPS and nanoMIPS platforms.\n\nSigned-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>\nSigned-off-by: Stefan Markovic <smarkovic@wavecomp.com>\n---\n disas/Makefile.objs | 1 +\n disas/mips.c | 358 +-\n disas/nanomips.cpp | 15752 ++++++++++++++++++++++++++++++++++++++++++++++++++\n disas/nanomips.h | 1208 ++++\n include/disas/bfd.h | 1 +\n target/mips/cpu.c | 12 +-\n 6 files changed, 17329 insertions(+), 3 deletions(-)\n create mode 100644 disas/nanomips.cpp\n create mode 100644 disas/nanomips.h", "diff": "diff --git a/disas/Makefile.objs b/disas/Makefile.objs\nindex 213be2f..b31a7c2 100644\n--- a/disas/Makefile.objs\n+++ b/disas/Makefile.objs\n@@ -14,6 +14,7 @@ common-obj-$(CONFIG_I386_DIS) += i386.o\n common-obj-$(CONFIG_M68K_DIS) += m68k.o\n common-obj-$(CONFIG_MICROBLAZE_DIS) += microblaze.o\n common-obj-$(CONFIG_MIPS_DIS) += mips.o\n+common-obj-$(CONFIG_MIPS_DIS) += nanomips.o\n common-obj-$(CONFIG_NIOS2_DIS) += nios2.o\n common-obj-$(CONFIG_MOXIE_DIS) += moxie.o\n common-obj-$(CONFIG_PPC_DIS) += ppc.o\ndiff --git a/disas/mips.c b/disas/mips.c\nindex 97f661a..5b02de1 100644\n--- a/disas/mips.c\n+++ b/disas/mips.c\n@@ -558,6 +558,8 @@ struct mips_opcode\n #define INSN_ISA32R6 0x00000200\n #define INSN_ISA64R6 0x00000400\n \n+#define INSN_ISANANOMIPS32 0x00000800\n+\n /* Masks used for MIPS-defined ASEs. */\n #define INSN_ASE_MASK\t\t 0x0000f000\n \n@@ -1167,6 +1169,8 @@ extern const int bfd_mips16_num_opcodes;\n #define I32R6 INSN_ISA32R6\n #define I64R6 INSN_ISA64R6\n \n+#define M32R7 INSN_ISANANOMIPS32\n+\n /* MIPS64 MIPS-3D ASE support. */\n #define I16 INSN_MIPS16\n \n@@ -5086,7 +5090,7 @@ print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)\n {\n return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);\n }\n-\f\n+\n /* Disassemble mips16 instructions. */\n #if 0\n static int\n@@ -5798,3 +5802,355 @@ with the -M switch (multiple options should be separated by commas):\\n\");\n fprintf (stream, \"\\n\");\n }\n #endif\n+\n+const struct mips_opcode micromips_opcodes[] = {\n+/*\n+ * These instructions appear first so that the disassembler will find\n+ * them first. The assemblers uses a hash table based on the\n+ * instruction name anyhow.\n+ */\n+\n+/* name, args, match, mask, pinfo, membership */\n+{\"add\", \"d,t,v\", 0x20000110, 0xfc0003ff, WR_t, 0, M32R7},\n+/* put sigrie before addiu */\n+{\"sigrie\", \"mij\", 0x00000000, 0xffe00000, WR_d, 0, M32R7},\n+{\"addiu\", \"v,t,mid\", 0x00000000, 0xfc006000, WR_d, 0, M32R7},\n+/* addiugp */\n+{\"addiu\", \"v,m8,mik\", 0x40000000, 0xfc000003, WR_d, 0, M32R7},\n+{\"au20ipc\", \"v,miv\", 0xe0000002, 0xfc000002, WR_d, 0, M32R7},\n+/* aluipcgp */\n+{\"alu20ipc\", \"m8,miv\", 0xe0000002, 0xffe00002, WR_d, 0, M32R7},\n+{\"addu\", \"d,t,v\", 0x20000150, 0xfc0003ff, WR_d, 0, M32R7},\n+{\"align\", \"d,t,v\", 0x2000001f, 0xfc00003f, WR_d, 0, M32R7},\n+{\"and\", \"d,t,v\", 0x20000250, 0xfc0003ff, WR_d, 0, M32R7},\n+{\"andi\", \"v,t,miC\", 0x80002000, 0xfc00f000, WR_d, 0, M32R7},\n+{\"balc\", \"map\", 0x2a000000, 0xfe000000, WR_d, 0, M32R7},\n+{\"bc\", \"map\", 0x28000000, 0xfc000000, WR_d, 0, M32R7},\n+{\"beqc\", \"t,v,mae\", 0x88000000, 0xfc00c000, WR_d, 0, M32R7},\n+{\"beqic\", \"v,miB,mab\", 0xc8000000, 0xfc1c0000, WR_d, 0, M32R7},\n+{\"beqzc\", \"v,mak\", 0xe8000000, 0xfc100000, WR_d, 0, M32R7},\n+{\"bgec\", \"t,v,mae\", 0x88008000, 0xfc00c000, WR_d, 0, M32R7},\n+{\"bgeic\", \"v,miB,mab\", 0xc8080000, 0xfc1c0000, WR_d, 0, M32R7},\n+{\"bgeuc\", \"t,v,mae\", 0x8800c000, 0xfc00c000, WR_d, 0, M32R7},\n+{\"bgeiuc\", \"v,miB,mab\", 0xc80c0000, 0xfc1c0000, WR_d, 0, M32R7},\n+{\"bitswap\", \"v,t\", 0x20000b3f, 0xfc00ffff, WR_d, 0, M32R7},\n+{\"bltc\", \"t,v,mae\", 0xa8008000, 0xfc00c000, WR_d, 0, M32R7},\n+{\"bltic\", \"v,miB,mab\", 0xc8180000, 0xfc1c0000, WR_d, 0, M32R7},\n+{\"bltuc\", \"t,v,mae\", 0xa800c000, 0xfc00c000, WR_d, 0, M32R7},\n+{\"bltiuc\", \"v,miB,mab\", 0xc81c0000, 0xfc1c0000, WR_d, 0, M32R7},\n+{\"bnec\", \"t,v,mae\", 0xa8000000, 0xfc00c000, WR_d, 0, M32R7},\n+{\"bneic\", \"v,miB,mab\", 0xc8100000, 0xfc1c0000, WR_d, 0, M32R7},\n+{\"bnezc\", \"v,mak\", 0xe8100000, 0xfc100000, WR_d, 0, M32R7},\n+{\"break\", \"mij\", 0x00100000, 0xfff80000, WR_d, 0, M32R7},\n+{\"cache\", \"6,mi8(t)\", 0xa4001900, 0xfc007f00, WR_d, 0, M32R7},\n+{\"clo\", \"v,t\", 0x20004b3f, 0xfc00ffff, WR_d, 0, M32R7},\n+{\"clz\", \"v,t\", 0x20005b3f, 0xfc00ffff, WR_d, 0, M32R7},\n+{\"di\", \"\", 0x2000477f, 0xffe0ffff, WR_d, 0, M32R7},\n+{\"di\", \"v\", 0x2000477f, 0xfc00ffff, WR_d, 0, M32R7},\n+{\"div\", \"d,t,v\", 0x20000118, 0xfc0003ff, WR_d, 0, M32R7},\n+{\"divu\", \"d,t,v\", 0x20000198, 0xfc0003ff, WR_d, 0, M32R7},\n+{\"ei\", \"\", 0x2000577f, 0xffe0ffff, WR_d, 0, M32R7},\n+{\"ei\", \"v\", 0x2000577f, 0xfc00ffff, WR_d, 0, M32R7},\n+{\"eret\", \"\", 0x2000f37f, 0xfc01ffff, WR_d, 0, M32R7},\n+{\"eretnc\", \"\", 0x2001f37f, 0xfc01ffff, WR_d, 0, M32R7},\n+{\"ext\", \"v,t,mi5,miz\", 0x8000f000, 0xfc00f820, WR_d, 0, M32R7},\n+{\"ins\", \"v,t,mi5,miZ\", 0x8000e000, 0xfc00f820, WR_d, 0, M32R7},\n+{\"jalrc\", \"v,t\", 0x48000000, 0xfc00f000, WR_d, 0, M32R7},\n+{\"jalrc.hb\", \"v,t\", 0x48001000, 0xfc00f000, WR_d, 0, M32R7},\n+{\"lb\", \"v,mic(t)\", 0x84000000, 0xfc00f000, WR_d, 0, M32R7},\n+/* lbgp */\n+{\"lb\", \"v,mii(m8)\", 0x44000000, 0xfc1c0000, WR_d, 0, M32R7},\n+/* lbs9 */\n+{\"lb\", \"v,mi8(t)\", 0xa4000000, 0xfc007f00, WR_d, 0, M32R7},\n+{\"lbu\", \"v,mic(t)\", 0x84002000, 0xfc00f000, WR_d, 0, M32R7},\n+/* lbugp */\n+{\"lbu\", \"v,mii(m8)\", 0x44080000, 0xfc1c0000, WR_d, 0, M32R7},\n+/* lbus9 */\n+{\"lbu\", \"v,mi8(t)\", 0xa4001000, 0xfc007f00, WR_d, 0, M32R7},\n+{\"lbux\", \"d,t(v)\", 0x40000107, 0xfc0007ff, WR_d, 0, M32R7},\n+{\"lbx\", \"d,t(v)\", 0x40000107, 0xfc000007, WR_d, 0, M32R7},\n+{\"lh\", \"v,mic(t)\", 0x84004000, 0xfc00f000, WR_d, 0, M32R7},\n+/* lhgp */\n+{\"lh\", \"v,mii(m8)\", 0x44100000, 0xfc1c0000, WR_d, 0, M32R7},\n+/* lhs9 */\n+{\"lh\", \"v,mi8(t)\", 0xa4002000, 0xfc007f00, WR_d, 0, M32R7},\n+{\"lhu\", \"v,mic(t)\", 0x84006000, 0xfc00f000, WR_d, 0, M32R7},\n+/* lhugp */\n+{\"lhu\", \"v,mii(m8)\", 0x44180000, 0xfc1c0000, WR_d, 0, M32R7},\n+/* lhus9 */\n+{\"lhu\", \"v,mi8(t)\", 0xa4003000, 0xfc007f00, WR_d, 0, M32R7},\n+{\"lhux\", \"d,t(v)\", 0x40000307, 0xfc0007ff, WR_d, 0, M32R7},\n+{\"lhuxs\", \"d,t(v)\", 0x40000347, 0xfc0007ff, WR_d, 0, M32R7},\n+{\"lhx\", \"d,t(v)\", 0x40000207, 0xfc0007ff, WR_d, 0, M32R7},\n+{\"lhxs\", \"d,t(v)\", 0x40000247, 0xfc0007ff, WR_d, 0, M32R7},\n+{\"ll\", \"v,mi8(t)\", 0xa4004100, 0xfc007f03, WR_d, 0, M32R7},\n+{\"llwp\", \"v,mu,(t)\", 0xa4004101, 0xfc007f03, WR_d, 0, M32R7},\n+{\"lsa\", \"d,t,v,mi(\", 0x4000000f, 0xfc00003f, WR_d, 0, M32R7},\n+{\"lu20i\", \"v,miv\", 0xe0000000, 0xfc000002, WR_t, 0, M32R7},\n+{\"lw\", \"v,mic(t)\", 0x84008000, 0xfc00f000, WR_d, 0, M32R7},\n+/* lws9 */\n+{\"lw\", \"v,mi8(t)\", 0xa4004000, 0xfc007f00, WR_d, 0, M32R7},\n+/* lwgp */\n+{\"lw\", \"v,mik(m8)\", 0x40000002, 0xfc000003, WR_d, 0, M32R7},\n+{\"lwx\", \"d,t(v)\", 0x20000407, 0xfc0007ff, WR_d, 0, M32R7},\n+{\"lwxs\", \"d,t(v)\", 0x20000447, 0xfc0007ff, WR_d, 0, M32R7},\n+{\"mfc0\", \"v,mG\", 0x20000030, 0xfc003bff, WR_d, 0, M32R7},\n+{\"mfc0\", \"v,mD\", 0x20000030, 0xfc0003ff, WR_d, 0, M32R7},\n+{\"mod\", \"d,t,v\", 0x20000158, 0xfc0003ff, WR_d, 0, M32R7},\n+{\"modu\", \"d,t,v\", 0x200001d8, 0xfc0003ff, WR_d, 0, M32R7},\n+{\"move.balc\", \"mo,ml,mal\", 0x08000000, 0xfc000000, WR_d, 0, M32R7},\n+{\"movn\", \"d,t,v\", 0x20000610, 0xfc0007ff, WR_d, 0, M32R7},\n+{\"movz\", \"d,t,v\", 0x20000210, 0xfc0007ff, WR_d, 0, M32R7},\n+{\"mtc0\", \"v,mG\", 0x20000070, 0xfc003bff, WR_d, 0, M32R7},\n+{\"mtc0\", \"v,mD\", 0x20000070, 0xfc0003ff, WR_d, 0, M32R7},\n+{\"muh\", \"d,t,v\", 0x20000058, 0xfc0003ff, WR_d, 0, M32R7},\n+{\"muhu\", \"d,t,v\", 0x200000d8, 0xfc0003ff, WR_d, 0, M32R7},\n+{\"mul\", \"d,t,v\", 0x20000018, 0xfc0003ff, WR_d, 0, M32R7},\n+{\"mulu\", \"d,t,v\", 0x20000098, 0xfc0003ff, WR_d, 0, M32R7},\n+{\"nop\", \"\", 0x8000c000, 0xffe0f1ff, WR_d, 0, M32R7},\n+{\"nor\", \"d,t,v\", 0x200002d0, 0xfc0003ff, WR_d, 0, M32R7},\n+{\"or\", \"d,t,v\", 0x20000290, 0xfc0003ff, WR_d, 0, M32R7},\n+{\"ori\", \"v,t,miC\", 0x80000000, 0xfc00f000, WR_d, 0, M32R7},\n+{\"pause\", \"\", 0x8000c005, 0xffe0f1ff, WR_d, 0, M32R7},\n+/* put synci before pref */\n+{\"synci\", \"mi8(t)\", 0xa7e01800, 0xffe07f00, WR_d, 0, M32R7},\n+{\"pref\", \"miL,mi8(t)\", 0xa4001800, 0xfc007f00, WR_d, 0, M32R7},\n+{\"rdhwr\", \"v,mg\", 0x200001c0, 0xfc0003ff, WR_d, 0, M32R7},\n+{\"rdpgpr\", \"v,t\", 0x2000e17f, 0xfc00ffff, WR_d, 0, M32R7},\n+{\"restore\", \"mib,v\", 0x80013000, 0xfc01f004, WR_d, 0, M32R7},\n+{\"restore.jrc\", \"mib,v\", 0x80013004, 0xfc01f004, WR_d, 0, M32R7},\n+{\"rotr\", \"v,t,mi5\", 0x8000c0c0, 0xfc00f1e0, WR_d, 0, M32R7},\n+{\"rotrv\", \"d,t,v\", 0x200000d0, 0xfc0003ff, WR_d, 0, M32R7},\n+{\"save\", \"mib,v\", 0x80003000, 0xfc01f000, WR_d, 0, M32R7},\n+{\"sb\", \"v,mic(t)\", 0x84001000, 0xfc00f000, WR_d, 0, M32R7},\n+/* sbs9 */\n+{\"sb\", \"v,mi8(t)\", 0xa4000800, 0xfc007f00, WR_d, 0, M32R7},\n+/* sbgp */\n+{\"sb\", \"v,mii(m8)\", 0x44040000, 0xfc1c0000, WR_d, 0, M32R7},\n+{\"sbx\", \"d,t(v)\", 0x20000087, 0xfc0007ff, WR_d, 0, M32R7},\n+{\"sc\", \"v,mi8(t)\", 0xa4004900, 0xfc007f03, WR_d, 0, M32R7},\n+{\"scwp\", \"v,m3,(t)\", 0xa4004901, 0xfc007f03, WR_d, 0, M32R7},\n+{\"seb\", \"v,t\", 0x20002b3f, 0xfc00ffff, WR_d, 0, M32R7},\n+{\"seh\", \"v,t\", 0x20003b3f, 0xfc00ffff, WR_d, 0, M32R7},\n+{\"seqi\", \"v,t,mic\", 0x20006000, 0xfc00f000, WR_d, 0, M32R7},\n+{\"sh\", \"v,mic(t)\", 0x84005000, 0xfc00f000, WR_d, 0, M32R7},\n+/* shs9 */\n+{\"sh\", \"v,mi8(t)\", 0xa4002800, 0xfc007f00, WR_d, 0, M32R7},\n+/* shgp */\n+{\"sh\", \"v,mii(m8)\", 0x44140000, 0xfc1c0000, WR_d, 0, M32R7},\n+{\"shx\", \"d,t(v)\", 0x20000287, 0xfc0007ff, WR_d, 0, M32R7},\n+{\"shxs\", \"d,t(v)\", 0x200002c7, 0xfc0007ff, WR_d, 0, M32R7},\n+/* put sync/ehb before sll */\n+{\"sync\", \"miG\", 0x8000c006, 0xffe0f1ff, WR_d, 0, M32R7},\n+{\"ehb\", \"\", 0x8000c003, 0xffe0f1ff, WR_d, 0, M32R7},\n+{\"sll\", \"v,t,mi5\", 0x8000c000, 0xfc00f1e0, WR_d, 0, M32R7},\n+{\"sllv\", \"d,t,v\", 0x20000010, 0xfc0003ff, WR_d, 0, M32R7},\n+{\"slt\", \"d,t,v\", 0x20000350, 0xfc0003ff, WR_d, 0, M32R7},\n+{\"slti\", \"v,t,mic\", 0x80004000, 0xfc00f000, WR_d, 0, M32R7},\n+{\"sltiu\", \"v,t,mic\", 0x80005000, 0xfc00f000, WR_d, 0, M32R7},\n+{\"sltu\", \"d,t,v\", 0x20000390, 0xfc0003ff, WR_d, 0, M32R7},\n+{\"sov\", \"d,t,v\", 0x200003d0, 0xfc0003ff, WR_d, 0, M32R7},\n+{\"sra\", \"v,t,mi5\", 0x8000c080, 0xfc00f1e0, WR_d, 0, M32R7},\n+{\"srav\", \"d,t,v\", 0x20000090, 0xfc0003ff, WR_d, 0, M32R7},\n+{\"srl\", \"v,t,mi5\", 0x8000c040, 0xfc00f1e0, WR_d, 0, M32R7},\n+{\"srlv\", \"d,t,v\", 0x20000050, 0xfc0003ff, WR_d, 0, M32R7},\n+{\"sub\", \"d,t,v\", 0x20000190, 0xfc0003ff, WR_d, 0, M32R7},\n+{\"subu\", \"d,t,v\", 0x200001d0, 0xfc0003ff, WR_d, 0, M32R7},\n+{\"sw\", \"v,mic(t)\", 0x84009000, 0xfc00f000, WR_d, 0, M32R7},\n+/* sws9 */\n+{\"sw\", \"v,mi8(t)\", 0xa4004800, 0xfc007f00, WR_d, 0, M32R7},\n+/* swgp */\n+{\"sw\", \"v,mik(m8)\", 0x40000003, 0xfc000003, WR_d, 0, M32R7},\n+{\"swx\", \"d,t(v)\", 0x20000487, 0xfc0007ff, WR_d, 0, M32R7},\n+{\"swxs\", \"d,t(v)\", 0x200004c7, 0xfc0007ff, WR_d, 0, M32R7},\n+{\"syscall\", \"mii\", 0x00080000, 0xfffc0000, WR_d, 0, M32R7},\n+{\"ualw\", \"v,mi8(t)\", 0xa4000100, 0xfc007f00, WR_d, 0, M32R7},\n+{\"uasw\", \"v,mi8(t)\", 0xa4000900, 0xfc007f00, WR_d, 0, M32R7},\n+{\"wait\", \"miG\", 0x2000c37f, 0xfc00ffff, WR_d, 0, M32R7},\n+{\"wrpgpr\", \"v,t\", 0x2000f17f, 0xfc00ffff, WR_d, 0, M32R7},\n+{\"wsbh\", \"v,t\", 0x20007b3f, 0xfc00ffff, WR_d, 0, M32R7},\n+{\"xor\", \"d,t,v\", 0x20000310, 0xfc0003ff, WR_d, 0, M32R7},\n+{\"xori\", \"v,t,miC\", 0x80001000, 0xfc00f000, WR_d, 0, M32R7},\n+{\"deret\", \"\", 0x2000e37f, 0xfc00ffff, WR_d, 0, M32R7},\n+{\"sdbbp\", \"mij\", 0x00180000, 0xfff80000, WR_d, 0, M32R7},\n+{\"tlbinv\", \"\", 0x2000077f, 0xfc00ffff, WR_d, 0, M32R7},\n+{\"tlbinvf\", \"\", 0x2000177f, 0xfc00ffff, WR_d, 0, M32R7},\n+{\"tlbp\", \"\", 0x2000037f, 0xfc00ffff, WR_d, 0, M32R7},\n+{\"tlbr\", \"\", 0x2000137f, 0xfc00ffff, WR_d, 0, M32R7},\n+{\"tlbwi\", \"\", 0x2000237f, 0xfc00ffff, WR_d, 0, M32R7},\n+{\"tlbwr\", \"\", 0x2000337f, 0xfc00ffff, WR_d, 0, M32R7},\n+{\"dvp\", \"v\", 0x20000390, 0xfc00ffff, WR_d, 0, M32R7},\n+{\"evp\", \"v\", 0x20000790, 0xfc00ffff, WR_d, 0, M32R7},\n+{\"balrc\", \"v,t\", 0x48008000, 0xfc00f200, WR_d, 0, M32R7},\n+{\"balrsc\", \"v,t\", 0x48008200, 0xfc00f200, WR_d, 0, M32R7},\n+{\"brc\", \"t\", 0x48008000, 0xffe0f200, WR_d, 0, M32R7},\n+{\"brsc\", \"t\", 0x48008200, 0xffe0f200, WR_d, 0, M32R7},\n+/* ADDIU48 */\n+{\"addiu\", \"v,miw\", 0x60010000, 0xfc1f0000, WR_d, 0, M32R7},\n+/* ADDIUGP48 */\n+{\"addiu\", \"v,m8,miw\", 0x60020000, 0xfc1f0000, WR_d, 0, M32R7},\n+/* li48 */\n+{\"li\", \"v,miw\", 0x60000000, 0xfc1f0000, WR_d, 0, M32R7},\n+\n+/* put before addiurs5 */\n+{\"nop\", \"\", 0x9008, 0xffff, WR_t, 0, M32R7},\n+/* addiu r1 sp */\n+{\"addiu\", \"mt,m9,mi7\", 0x7040, 0xfc40, WR_t, 0, M32R7},\n+/* addiu r2 */\n+{\"addiu\", \"mt,ms,mi4\", 0x9000, 0xfc08, WR_t, 0, M32R7},\n+/* addiu rs5 */\n+{\"addiu\", \"m5,mi3\", 0x9008, 0xfc08, WR_t, 0, M32R7},\n+{\"addu\", \"md,ms,mt\", 0xb000, 0xfc01, WR_t, 0, M32R7},\n+{\"and\", \"mt,ms\", 0x5008, 0xfc0f, WR_t, 0, M32R7},\n+{\"andi\", \"mt,ms,mi0\", 0xf000, 0xfc00, WR_t, 0, M32R7},\n+{\"balc\", \"maa\", 0x3800, 0xfc00, WR_t, 0, M32R7},\n+{\"bc\", \"maa\", 0x1800, 0xfc00, WR_t, 0, M32R7},\n+/* put jrc, jalrc before b{eq|ne}c */\n+{\"jrc\", \"m5\", 0xd800, 0xfc1f, WR_t, 0, M32R7},\n+{\"jalrc\", \"m5\", 0xd810, 0xfc1f, WR_t, 0, M32R7},\n+/* b{eq|ne}c */\n+{\"\", \"mQmt,ms,ma4\", 0xd800, 0xfc00, WR_t, 0, M32R7},\n+{\"beqzc\", \"mt,ma7\", 0x9800, 0xfc00, WR_t, 0, M32R7},\n+{\"bnezc\", \"mt,ma7\", 0xb800, 0xfc00, WR_t, 0, M32R7},\n+{\"break\", \"mi2\", 0x1010, 0xfff8, WR_t, 0, M32R7},\n+\n+{\"lb\", \"mt,mi1(ms)\", 0x1400, 0xfc0c, WR_t, 0, M32R7},\n+{\"lbu\", \"mt,mi1(ms\", 0x1408, 0xfc0c, WR_t, 0, M32R7},\n+{\"lh\", \"mt,mi@(ms)\", 0x3400, 0xfc09, WR_t, 0, M32R7},\n+{\"lhu\", \"mt,mi@(ms)\", 0x3408, 0xfc09, WR_t, 0, M32R7},\n+{\"li\", \"mt,mi)\", 0xd000, 0xfc00, WR_t, 0, M32R7},\n+\n+/* lw 4x4 */\n+{\"lw\", \"m(,mi#(m$)\", 0x9400, 0xfc00, WR_t, 0, M32R7},\n+{\"lw\", \"mt,mi%(ms)\", 0x7400, 0xfc00, WR_t, 0, M32R7},\n+/* lwgp16 */\n+{\"lw\", \"mt,mi*(m8)\", 0xb400, 0xfc00, WR_t, 0, M32R7},\n+/* lwsp */\n+{\"lw\", \"m5,mi6(m9)\", 0x5400, 0xfc00, WR_t, 0, M32R7},\n+{\"lwxs\", \"md,ms(mt)\", 0x5001, 0xfc01, WR_t, 0, M32R7},\n+/* put sdbbp befroe move */\n+{\"sdbbp\", \"mi2\", 0x1018, 0xfff8, WR_t, 0, M32R7},\n+{\"move\", \"m5,m0\", 0x1000, 0xfc00, WR_t, 0, M32R7},\n+{\"movep\", \"mP\", 0xbc00, 0xfc00, WR_t, 0, M32R7},\n+/* moveprev */\n+{\"movep\", \"mV\", 0xfc00, 0xfc00, WR_t, 0, M32R7},\n+{\"not\", \"mt,ms\", 0x5000, 0xfc0f, WR_t, 0, M32R7},\n+{\"or\", \"mt,ms\", 0x500c, 0xfc0f, WR_t, 0, M32R7},\n+{\"restore\", \"mi^\", 0x1fe0, 0xffe1, WR_t, 0, M32R7},\n+{\"restore.jrc\", \"mi^\", 0x1c20, 0xfc21, WR_t, 0, M32R7},\n+{\"save\", \"mi^\", 0x1c00, 0xfc21, WR_t, 0, M32R7},\n+{\"sb\", \"mT,mi1(ms)\", 0x1404, 0xfc0c, WR_t, 0, M32R7},\n+{\"sh\", \"mT,mi@(ms)\", 0x1401, 0xfc09, WR_t, 0, M32R7},\n+{\"sll\", \"mt,ms,mi2\", 0x3000, 0xfc08, WR_t, 0, M32R7},\n+{\"srl\", \"mt,ms,mi2\", 0x3008, 0xfc08, WR_t, 0, M32R7},\n+{\"subu\", \"md,ms,mt\", 0xb001, 0xfc01, WR_t, 0, M32R7},\n+{\"sw\", \"mT,mi%(ms)\", 0xf400, 0xfc00, WR_t, 0, M32R7},\n+/* swsp */\n+{\"sw\", \"m5,mi6(m9)\", 0xd400, 0xfc00, WR_t, 0, M32R7},\n+/* sw 4x4 */\n+{\"sw\", \"m(,mi#(m$)\", 0x9c00, 0xfc00, WR_t, 0, M32R7},\n+{\"syscall\", \"mi1\", 0x1008, 0xfffc, WR_t, 0, M32R7},\n+{\"xor\", \"mt,ms\", 0x5004, 0xfc0f, WR_t, 0, M32R7},\n+};\n+\n+#define MICROMIPS_NUM_OPCODES \\\n+ ((sizeof micromips_opcodes) / (sizeof(micromips_opcodes[0])))\n+const int bfd_micromips_num_opcodes = MICROMIPS_NUM_OPCODES;\n+\n+/* The mips16 registers. */\n+\n+/*\n+ * static const unsigned int umips_decode_gpr3[] =\n+ * { 16, 17, 18, 19, 4, 5, 6, 7};\n+ *\n+ * static const unsigned int umips_decode_gpr3_src_store[] =\n+ * { 0, 17, 18, 19, 4, 5, 6, 7};\n+ */\n+\n+#define umips_decode_gpr3_reg_names(rn) mips_gpr_names[umips_decode_gpr3[rn]]\n+#define umips_decode_gpr3_src_store_reg_names(rn) \\\n+ mips_gpr_names[umips_decode_gpr3_src_store[rn]]\n+\n+int nanomips_dis(char *buf, unsigned address, unsigned short one,\n+ unsigned short two, unsigned short three);\n+\n+int print_insn_micromips(bfd_vma memaddr, struct disassemble_info *info)\n+{\n+ int status;\n+ bfd_byte buffer[2];\n+ uint16_t insn1 = 0, insn2 = 0, insn3 = 0;\n+ char buf[200];\n+\n+ info->bytes_per_chunk = 2;\n+ info->display_endian = info->endian;\n+ info->insn_info_valid = 1;\n+ info->branch_delay_insns = 0;\n+ info->data_size = 0;\n+ info->insn_type = dis_nonbranch;\n+ info->target = 0;\n+ info->target2 = 0;\n+\n+ set_default_mips_dis_options(info);\n+ parse_mips_dis_options(info->disassembler_options);\n+\n+ status = (*info->read_memory_func)(memaddr, buffer, 2, info);\n+ if (status != 0) {\n+ (*info->memory_error_func)(status, memaddr, info);\n+ return -1;\n+ }\n+\n+ if (info->endian == BFD_ENDIAN_BIG) {\n+ insn1 = bfd_getb16(buffer);\n+ } else {\n+ insn1 = bfd_getl16(buffer);\n+ }\n+ (*info->fprintf_func)(info->stream, \"%04x \", insn1);\n+\n+ /* Handle 32-bit opcodes. */\n+ if ((insn1 & 0x1000) == 0) {\n+ status = (*info->read_memory_func)(memaddr + 2, buffer, 2, info);\n+ if (status != 0) {\n+ (*info->memory_error_func)(status, memaddr + 2, info);\n+ return -1;\n+ }\n+\n+ if (info->endian == BFD_ENDIAN_BIG) {\n+ insn2 = bfd_getb16(buffer);\n+ } else {\n+ insn2 = bfd_getl16(buffer);\n+ }\n+ (*info->fprintf_func)(info->stream, \"%04x \", insn2);\n+ } else {\n+ (*info->fprintf_func)(info->stream, \" \");\n+ }\n+ /* Handle 48-bit opcodes. */\n+ if ((insn1 >> 10) == 0x18) {\n+ status = (*info->read_memory_func)(memaddr + 4, buffer, 2, info);\n+ if (status != 0) {\n+ (*info->memory_error_func)(status, memaddr + 4, info);\n+ return -1;\n+ }\n+\n+ if (info->endian == BFD_ENDIAN_BIG) {\n+ insn3 = bfd_getb16(buffer);\n+ } else {\n+ insn3 = bfd_getl16(buffer);\n+ }\n+ (*info->fprintf_func)(info->stream, \"%04x \", insn3);\n+ } else {\n+ (*info->fprintf_func)(info->stream, \" \");\n+ }\n+\n+ int length = nanomips_dis(buf, memaddr, insn1, insn2, insn3);\n+\n+ /* FIXME: Should probably use a hash table on the major opcode here. */\n+\n+ (*info->fprintf_func) (info->stream, \"%s\", buf);\n+ if (length > 0) {\n+ return length / 8;\n+ }\n+\n+ info->insn_type = dis_noninsn;\n+\n+ return insn3 ? 6 : insn2 ? 4 : 2;\n+}\ndiff --git a/disas/nanomips.cpp b/disas/nanomips.cpp\nnew file mode 100644\nindex 0000000..35c3973\n--- /dev/null\n+++ b/disas/nanomips.cpp\n@@ -0,0 +1,15752 @@\n+\n+#include <cstring>\n+#include <stdexcept>\n+#include <sstream>\n+\n+#define INCLUDE_STANDALONE_UNIT_TEST\n+\n+#ifdef INCLUDE_STANDALONE_UNIT_TEST\n+#include <stdio.h>\n+#include <stdarg.h>\n+\n+#include \"nanomips.h\"\n+\n+#define IMGASSERTONCE(test)\n+\n+namespace img\n+{\n+ address addr32(address a)\n+ {\n+ return a;\n+ }\n+\n+ std::string format(const char *format, ...)\n+ {\n+ char buffer[256];\n+ va_list args;\n+ va_start(args, format);\n+ int err = vsprintf(buffer, format, args);\n+ if (err < 0) {\n+ perror(buffer);\n+ }\n+ va_end(args);\n+ return buffer;\n+ }\n+\n+ std::string format(const char *format,\n+ std::string s)\n+ {\n+ char buffer[256];\n+\n+ sprintf(buffer, format, s.c_str());\n+\n+ return buffer;\n+ }\n+\n+ std::string format(const char *format,\n+ std::string s1,\n+ std::string s2)\n+ {\n+ char buffer[256];\n+\n+ sprintf(buffer, format, s1.c_str(), s2.c_str());\n+\n+ return buffer;\n+ }\n+\n+ std::string format(const char *format,\n+ std::string s1,\n+ std::string s2,\n+ std::string s3)\n+ {\n+ char buffer[256];\n+\n+ sprintf(buffer, format, s1.c_str(), s2.c_str(), s3.c_str());\n+\n+ return buffer;\n+ }\n+\n+ std::string format(const char *format,\n+ std::string s1,\n+ std::string s2,\n+ std::string s3,\n+ std::string s4)\n+ {\n+ char buffer[256];\n+\n+ sprintf(buffer, format, s1.c_str(), s2.c_str(), s3.c_str(),\n+ s4.c_str());\n+\n+ return buffer;\n+ }\n+\n+ std::string format(const char *format,\n+ std::string s1,\n+ std::string s2,\n+ std::string s3,\n+ std::string s4,\n+ std::string s5)\n+ {\n+ char buffer[256];\n+\n+ sprintf(buffer, format, s1.c_str(), s2.c_str(), s3.c_str(),\n+ s4.c_str(), s5.c_str());\n+\n+ return buffer;\n+ }\n+\n+ std::string format(const char *format,\n+ uint64 d,\n+ std::string s2)\n+ {\n+ char buffer[256];\n+\n+ sprintf(buffer, format, d, s2.c_str());\n+\n+ return buffer;\n+ }\n+\n+ std::string format(const char *format,\n+ std::string s1,\n+ uint64 d,\n+ std::string s2)\n+ {\n+ char buffer[256];\n+\n+ sprintf(buffer, format, s1.c_str(), d, s2.c_str());\n+\n+ return buffer;\n+ }\n+\n+ std::string format(const char *format,\n+ std::string s1,\n+ std::string s2,\n+ uint64 d)\n+ {\n+ char buffer[256];\n+\n+ sprintf(buffer, format, s1.c_str(), s2.c_str(), d);\n+\n+ return buffer;\n+ }\n+\n+ char as_char(int c)\n+ {\n+ return static_cast<char>(c);\n+ }\n+};\n+\n+std::string to_string(img::address a)\n+{\n+ char buffer[256];\n+ sprintf(buffer, \"0x%08llx\", a);\n+ return buffer;\n+}\n+\n+#else\n+#include \"imgleeds/imgleeds/format.h\"\n+#endif\n+\n+\n+uint64 extract_bits(uint64 data, uint32 bit_offset, uint32 bit_size)\n+{\n+ return (data << (64 - (bit_size + bit_offset))) >> (64 - bit_size);\n+}\n+\n+int64 sign_extend(int64 data, int msb)\n+{\n+ uint64 shift = 63 - msb;\n+ return (data << shift) >> shift;\n+}\n+\n+uint64 NMD::renumber_registers(uint64 index, uint64 *register_list,\n+ size_t register_list_size)\n+{\n+ if (index < register_list_size) {\n+ return register_list[index];\n+ }\n+\n+ throw std::runtime_error(img::format(\n+ \"Invalid register mapping index %d, size of list = %d\",\n+ index, register_list_size));\n+}\n+\n+/*\n+ * these functions should be decode functions but the json does not have\n+ * decode sections so they are based on the encode, the equivalent decode\n+ * functions need writing eventually.\n+ */\n+uint64 NMD::encode_gpr3(uint64 d)\n+{\n+ static uint64 register_list[] = { 16, 17, 18, 19, 4, 5, 6, 7 };\n+ return renumber_registers(d, register_list,\n+ sizeof(register_list) / sizeof(register_list[0]));\n+}\n+uint64 NMD::encode_gpr3_store(uint64 d)\n+{\n+ static uint64 register_list[] = { 0, 17, 18, 19, 4, 5, 6, 7 };\n+ return renumber_registers(d, register_list,\n+ sizeof(register_list) / sizeof(register_list[0]));\n+}\n+uint64 NMD::encode_rd1_from_rd(uint64 d)\n+{\n+ static uint64 register_list[] = { 4, 5 };\n+ return renumber_registers(d, register_list,\n+ sizeof(register_list) / sizeof(register_list[0]));\n+}\n+uint64 NMD::encode_gpr4_zero(uint64 d)\n+{\n+ static uint64 register_list[] = { 8, 9, 10, 0, 4, 5, 6, 7,\n+ 16, 17, 18, 19, 20, 21, 22, 23 };\n+ return renumber_registers(d, register_list,\n+ sizeof(register_list) / sizeof(register_list[0]));\n+}\n+uint64 NMD::encode_gpr4(uint64 d)\n+{\n+ static uint64 register_list[] = { 8, 9, 10, 11, 4, 5, 6, 7,\n+ 16, 17, 18, 19, 20, 21, 22, 23 };\n+ return renumber_registers(d, register_list,\n+ sizeof(register_list) / sizeof(register_list[0]));\n+}\n+uint64 NMD::encode_rd2_reg1(uint64 d)\n+{\n+ static uint64 register_list[] = { 4, 5, 6, 7 };\n+ return renumber_registers(d, register_list,\n+ sizeof(register_list) / sizeof(register_list[0]));\n+}\n+uint64 NMD::encode_rd2_reg2(uint64 d)\n+{\n+ static uint64 register_list[] = { 5, 6, 7, 8 };\n+ return renumber_registers(d, register_list,\n+ sizeof(register_list) / sizeof(register_list[0]));\n+}\n+\n+uint64 NMD::copy(uint64 d)\n+{\n+ return d;\n+}\n+int64 NMD::copy(int64 d)\n+{\n+ return d;\n+}\n+int64 NMD::neg_copy(uint64 d)\n+{\n+ return 0ll - d;\n+}\n+int64 NMD::neg_copy(int64 d)\n+{\n+ return -d;\n+}\n+/* strange wrapper around gpr3 */\n+uint64 NMD::encode_rs3_and_check_rs3_ge_rt3(uint64 d)\n+{\n+return encode_gpr3(d);\n+}\n+/* strange wrapper around gpr3 */\n+uint64 NMD::encode_rs3_and_check_rs3_lt_rt3(uint64 d)\n+{\n+ return encode_gpr3(d);\n+}\n+/* nop - done by extraction function */\n+uint64 NMD::encode_s_from_address(uint64 d)\n+{\n+ return d;\n+}\n+/* nop - done by extraction function */\n+uint64 NMD::encode_u_from_address(uint64 d)\n+{\n+ return d;\n+}\n+/* nop - done by extraction function */\n+uint64 NMD::encode_s_from_s_hi(uint64 d)\n+{\n+ return d;\n+}\n+uint64 NMD::encode_count3_from_count(uint64 d)\n+{\n+ IMGASSERTONCE(d < 8);\n+ return d == 0ull ? 8ull : d;\n+}\n+uint64 NMD::encode_shift3_from_shift(uint64 d)\n+{\n+ IMGASSERTONCE(d < 8);\n+ return d == 0ull ? 8ull : d;\n+}\n+/* special value for load literal */\n+int64 NMD::encode_eu_from_s_li16(uint64 d)\n+{\n+ IMGASSERTONCE(d < 128);\n+ return d == 127 ? -1 : (int64)d;\n+}\n+uint64 NMD::encode_msbd_from_size(uint64 d)\n+{\n+ IMGASSERTONCE(d < 32);\n+ return d + 1;\n+}\n+uint64 NMD::encode_eu_from_u_andi16(uint64 d)\n+{\n+ IMGASSERTONCE(d < 16);\n+ if (d == 12) {\n+ return 0x00ffull;\n+ }\n+ if (d == 13) {\n+ return 0xffffull;\n+ }\n+ return d;\n+}\n+uint64 NMD::encode_msbd_from_pos_and_size(uint64 d)\n+{\n+ IMGASSERTONCE(0);\n+ return d;\n+}\n+/* save16 / restore16 ???? */\n+uint64 NMD::encode_rt1_from_rt(uint64 d)\n+{\n+ return d ? 31 : 30;\n+}\n+/* ? */\n+uint64 NMD::encode_lsb_from_pos_and_size(uint64 d)\n+{\n+ return d;\n+}\n+\n+\n+std::string NMD::save_restore_list(uint64 rt, uint64 count, uint64 gp)\n+{\n+ std::string str;\n+\n+ for (uint64 counter = 0; counter != count; counter++) {\n+ bool use_gp = gp && (counter == count - 1);\n+ uint64 this_rt = use_gp ? 28 : ((rt & 0x10) | (rt + counter)) & 0x1f;\n+ str += img::format(\",%s\", GPR(this_rt));\n+ }\n+\n+ return str;\n+}\n+\n+std::string NMD::GPR(uint64 reg)\n+{\n+ static const char *gpr_reg[32] = {\n+ \"zero\", \"at\", \"v0\", \"v1\", \"a0\", \"a1\", \"a2\", \"a3\",\n+ \"a4\", \"a5\", \"a6\", \"a7\", \"r12\", \"r13\", \"r14\", \"r15\",\n+ \"s0\", \"s1\", \"s2\", \"s3\", \"s4\", \"s5\", \"s6\", \"s7\",\n+ \"r24\", \"r25\", \"k0\", \"k1\", \"gp\", \"sp\", \"fp\", \"ra\"\n+ };\n+\n+ if (reg < 32) {\n+ return gpr_reg[reg];\n+ }\n+\n+ throw std::runtime_error(img::format(\"Invalid GPR register index %d\", reg));\n+}\n+\n+std::string NMD::FPR(uint64 reg)\n+{\n+ static const char *fpr_reg[32] = {\n+ \"f0\", \"f1\", \"f2\", \"f3\", \"f4\", \"f5\", \"f6\", \"f7\",\n+ \"f8\", \"f9\", \"f10\", \"f11\", \"f12\", \"f13\", \"f14\", \"f15\",\n+ \"f16\", \"f17\", \"f18\", \"f19\", \"f20\", \"f21\", \"f22\", \"f23\",\n+ \"f24\", \"f25\", \"f26\", \"f27\", \"f28\", \"f29\", \"f30\", \"f31\"\n+ };\n+\n+ if (reg < 32) {\n+ return fpr_reg[reg];\n+ }\n+\n+ throw std::runtime_error(img::format(\"Invalid FPR register index %d\", reg));\n+}\n+\n+std::string NMD::AC(uint64 reg)\n+{\n+ static const char *ac_reg[4] = {\n+ \"ac0\", \"ac1\", \"ac2\", \"ac3\"\n+ };\n+\n+ if (reg < 4) {\n+ return ac_reg[reg];\n+ }\n+\n+ throw std::runtime_error(img::format(\"Invalid AC register index %d\", reg));\n+}\n+\n+std::string NMD::IMMEDIATE(uint64 value)\n+{\n+ return img::format(\"0x%x\", value);\n+}\n+\n+std::string NMD::IMMEDIATE(int64 value)\n+{\n+ return img::format(\"%d\", value);\n+}\n+\n+std::string NMD::CPR(uint64 reg)\n+{\n+ /* needs more work */\n+ return img::format(\"CP%d\", reg);\n+}\n+\n+std::string NMD::ADDRESS(uint64 value, int instruction_size)\n+{\n+ /* token for string replace */\n+ /* const char TOKEN_REPLACE = (char)0xa2; */\n+ img::address address = m_pc + value + instruction_size;\n+ /* symbol replacement */\n+ /* return img::as_char(TOKEN_REPLACE) + to_string(address); */\n+ return to_string(address);\n+}\n+\n+uint64 NMD::extract_op_code_value(const uint16 * data, int size)\n+{\n+ switch (size) {\n+ case 16:\n+ return data[0];\n+ case 32:\n+ return ((uint64)data[0] << 16) | data[1];\n+ case 48:\n+ return ((uint64)data[0] << 32) | ((uint64)data[1] << 16) | data[2];\n+ default:\n+ return data[0];\n+ }\n+}\n+\n+/*\n+ * Recurse through tables until the instruction is found then return\n+ * the string and size\n+ *\n+ * inputs:\n+ * pointer to a word stream,\n+ * disassember table and size\n+ * returns:\n+ * instruction size - negative is error\n+ * disassembly string - on error will constain error string\n+ */\n+int NMD::Disassemble(const uint16 * data, std::string & dis,\n+ NMD::TABLE_ENTRY_TYPE & type)\n+{\n+ return Disassemble(data, dis, type, MAJOR, 2);\n+}\n+\n+\n+int NMD::Disassemble(const uint16 * data, std::string & dis,\n+ NMD::TABLE_ENTRY_TYPE & type, const Pool *table,\n+ int table_size)\n+{\n+ try\n+ {\n+ for (int i = 0; i < table_size; i++) {\n+ uint64 op_code = extract_op_code_value(data,\n+ table[i].instructions_size);\n+ if ((op_code & table[i].mask) == table[i].value) {\n+ /* possible match */\n+ conditional_function cond = table[i].condition;\n+ if ((cond == 0) || (this->*cond)(op_code)) {\n+ try\n+ {\n+ if (table[i].type == pool) {\n+ return Disassemble(data, dis, type,\n+ table[i].next_table,\n+ table[i].next_table_size);\n+ } else if ((table[i].type == instruction) ||\n+ (table[i].type == call_instruction) ||\n+ (table[i].type == branch_instruction) ||\n+ (table[i].type == return_instruction)) {\n+ if ((table[i].attributes != 0) &&\n+ (m_requested_instruction_catagories &\n+ table[i].attributes) == 0) {\n+ /*\n+ * failed due to instruction having\n+ * an ASE attribute and the requested version\n+ * not having that attribute\n+ */\n+ dis = \"ASE attribute missmatch\";\n+ return -5;\n+ }\n+ disassembly_function dis_fn = table[i].disassembly;\n+ if (dis_fn == 0) {\n+ dis = \"disassembler failure - bad table entry\";\n+ return -6;\n+ }\n+ type = table[i].type;\n+ dis = (this->*dis_fn)(op_code);\n+ return table[i].instructions_size;\n+ } else {\n+ dis = \"reserved instruction\";\n+ return -2;\n+ }\n+ }\n+ catch (std::runtime_error & e)\n+ {\n+ dis = e.what();\n+ return -3; /* runtime error */\n+ }\n+ }\n+ }\n+ }\n+ }\n+ catch (std::exception & e)\n+ {\n+ dis = e.what();\n+ return -4; /* runtime error */\n+ }\n+\n+ dis = \"failed to disassemble\";\n+ return -1; /* failed to disassemble */\n+}\n+\n+uint64 NMD::extr_codeil0il0bs19Fmsb18(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 0, 19) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_shift3il0il0bs3Fmsb2(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 0, 3) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_uil3il3bs9Fmsb11(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 3, 9) << 3;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_countil0il0bs4Fmsb3(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 0, 4) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_rtz3il7il0bs3Fmsb2(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 7, 3) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_uil1il1bs17Fmsb17(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 1, 17) << 1;\n+ return value;\n+}\n+\n+\n+int64 NMD::extr_sil11il0bs10Tmsb9(uint64 instruction)\n+{\n+ int64 value = 0;\n+ value |= extract_bits(instruction, 11, 10) << 0;\n+ value = sign_extend(value, 9);\n+ return value;\n+}\n+\n+\n+int64 NMD::extr_sil0il11bs1_il1il1bs10Tmsb11(uint64 instruction)\n+{\n+ int64 value = 0;\n+ value |= extract_bits(instruction, 0, 1) << 11;\n+ value |= extract_bits(instruction, 1, 10) << 1;\n+ value = sign_extend(value, 11);\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_uil10il0bs1Fmsb0(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 10, 1) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_rtz4il21il0bs3_il25il3bs1Fmsb3(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 21, 3) << 0;\n+ value |= extract_bits(instruction, 25, 1) << 3;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_sail11il0bs5Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 11, 5) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_shiftil0il0bs5Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 0, 5) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_shiftxil7il1bs4Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 7, 4) << 1;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_hintil21il0bs5Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 21, 5) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_count3il12il0bs3Fmsb2(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 12, 3) << 0;\n+ return value;\n+}\n+\n+\n+int64 NMD::extr_sil0il31bs1_il2il21bs10_il12il12bs9Tmsb31(uint64 instruction)\n+{\n+ int64 value = 0;\n+ value |= extract_bits(instruction, 0, 1) << 31;\n+ value |= extract_bits(instruction, 2, 10) << 21;\n+ value |= extract_bits(instruction, 12, 9) << 12;\n+ value = sign_extend(value, 31);\n+ return value;\n+}\n+\n+\n+int64 NMD::extr_sil0il7bs1_il1il1bs6Tmsb7(uint64 instruction)\n+{\n+ int64 value = 0;\n+ value |= extract_bits(instruction, 0, 1) << 7;\n+ value |= extract_bits(instruction, 1, 6) << 1;\n+ value = sign_extend(value, 7);\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_u2il9il0bs2Fmsb1(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 9, 2) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_codeil16il0bs10Fmsb9(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 16,\n+ 10) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_rsil16il0bs5Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 16,\n+ 5) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_uil1il1bs2Fmsb2(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 1, 2) << 1;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_stripeil6il0bs1Fmsb0(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 6, 1) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_xil17il0bs1Fmsb0(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 17, 1) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_xil2il0bs1_il15il0bs1Fmsb0(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 2, 1) << 0;\n+ value |= extract_bits(instruction, 15, 1) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_acil14il0bs2Fmsb1(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 14, 2) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_shiftil16il0bs5Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 16,\n+ 5) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_rd1il24il0bs1Fmsb0(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 24, 1) << 0;\n+ return value;\n+}\n+\n+\n+int64 NMD::extr_sil0il10bs1_il1il1bs9Tmsb10(uint64 instruction)\n+{\n+ int64 value = 0;\n+ value |= extract_bits(instruction, 0, 1) << 10;\n+ value |= extract_bits(instruction, 1, 9) << 1;\n+ value = sign_extend(value, 10);\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_euil0il0bs7Fmsb6(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 0, 7) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_shiftil0il0bs6Fmsb5(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 0, 6) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_xil10il0bs6Fmsb5(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 10, 6) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_countil16il0bs4Fmsb3(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 16,\n+ 4) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_codeil0il0bs3Fmsb2(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 0, 3) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_xil10il0bs4_il22il0bs4Fmsb3(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 10, 4) << 0;\n+ value |= extract_bits(instruction, 22, 4) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_uil0il0bs12Fmsb11(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 0, 12) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_rsil0il0bs5Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 0, 5) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_uil3il3bs18Fmsb20(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 3, 18) << 3;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_xil12il0bs1Fmsb0(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 12, 1) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_uil0il2bs4Fmsb5(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 0, 4) << 2;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_cofunil3il0bs23Fmsb22(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 3, 23) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_uil0il2bs3Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 0, 3) << 2;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_xil10il0bs1Fmsb0(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 10, 1) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_rd3il1il0bs3Fmsb2(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 1, 3) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_sail12il0bs4Fmsb3(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 12, 4) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_rtil21il0bs5Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 21, 5) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_ruil3il0bs5Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 3, 5) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_xil21il0bs5Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 21, 5) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_xil9il0bs3Fmsb2(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 9, 3) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_uil0il0bs18Fmsb17(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 0, 18) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_xil14il0bs1_il15il0bs1Fmsb0(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 14, 1) << 0;\n+ value |= extract_bits(instruction, 15, 1) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_rsz4il0il0bs3_il4il3bs1Fmsb3(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 0, 3) << 0;\n+ value |= extract_bits(instruction, 4, 1) << 3;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_xil24il0bs1Fmsb0(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 24, 1) << 0;\n+ return value;\n+}\n+\n+\n+int64 NMD::extr_sil0il21bs1_il1il1bs20Tmsb21(uint64 instruction)\n+{\n+ int64 value = 0;\n+ value |= extract_bits(instruction, 0, 1) << 21;\n+ value |= extract_bits(instruction, 1, 20) << 1;\n+ value = sign_extend(value, 21);\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_opil3il0bs23Fmsb22(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 3, 23) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_rs4il0il0bs3_il4il3bs1Fmsb3(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 0, 3) << 0;\n+ value |= extract_bits(instruction, 4, 1) << 3;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_bitil21il0bs3Fmsb2(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 21, 3) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_rtil37il0bs5Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 37, 5) << 0;\n+ return value;\n+}\n+\n+\n+int64 NMD::extr_sil16il0bs6Tmsb5(uint64 instruction)\n+{\n+ int64 value = 0;\n+ value |= extract_bits(instruction, 16,\n+ 6) << 0;\n+ value = sign_extend(value, 5);\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_xil6il0bs3_il10il0bs1Fmsb2(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 6, 3) << 0;\n+ value |= extract_bits(instruction, 10, 1) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_rd2il3il1bs1_il8il0bs1Fmsb1(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 3, 1) << 1;\n+ value |= extract_bits(instruction, 8, 1) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_xil16il0bs5Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 16,\n+ 5) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_codeil0il0bs18Fmsb17(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 0, 18) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_xil0il0bs12Fmsb11(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 0, 12) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_sizeil16il0bs5Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 16,\n+ 5) << 0;\n+ return value;\n+}\n+\n+\n+int64 NMD::extr_sil2il2bs6_il15il8bs1Tmsb8(uint64 instruction)\n+{\n+ int64 value = 0;\n+ value |= extract_bits(instruction, 2, 6) << 2;\n+ value |= extract_bits(instruction, 15, 1) << 8;\n+ value = sign_extend(value, 8);\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_uil0il0bs16Fmsb15(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 0, 16) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_fsil16il0bs5Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 16,\n+ 5) << 0;\n+ return value;\n+}\n+\n+\n+int64 NMD::extr_sil0il0bs8_il15il8bs1Tmsb8(uint64 instruction)\n+{\n+ int64 value = 0;\n+ value |= extract_bits(instruction, 0, 8) << 0;\n+ value |= extract_bits(instruction, 15, 1) << 8;\n+ value = sign_extend(value, 8);\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_stypeil16il0bs5Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 16,\n+ 5) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_rt1il9il0bs1Fmsb0(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 9, 1) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_hsil16il0bs5Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 16,\n+ 5) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_xil10il0bs1_il14il0bs2Fmsb1(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 10, 1) << 0;\n+ value |= extract_bits(instruction, 14, 2) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_selil11il0bs3Fmsb2(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 11, 3) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_lsbil0il0bs5Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 0, 5) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_xil14il0bs2Fmsb1(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 14, 2) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_gpil2il0bs1Fmsb0(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 2, 1) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_rt3il7il0bs3Fmsb2(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 7, 3) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_ftil21il0bs5Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 21, 5) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_uil11il0bs7Fmsb6(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 11, 7) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_csil16il0bs5Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 16,\n+ 5) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_xil16il0bs10Fmsb9(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 16,\n+ 10) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_rt4il5il0bs3_il9il3bs1Fmsb3(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 5, 3) << 0;\n+ value |= extract_bits(instruction, 9, 1) << 3;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_msbdil6il0bs5Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 6, 5) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_uil0il2bs6Fmsb7(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 0, 6) << 2;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_xil17il0bs9Fmsb8(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 17, 9) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_sail13il0bs3Fmsb2(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 13, 3) << 0;\n+ return value;\n+}\n+\n+\n+int64 NMD::extr_sil0il14bs1_il1il1bs13Tmsb14(uint64 instruction)\n+{\n+ int64 value = 0;\n+ value |= extract_bits(instruction, 0, 1) << 14;\n+ value |= extract_bits(instruction, 1, 13) << 1;\n+ value = sign_extend(value, 14);\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_rs3il4il0bs3Fmsb2(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 4, 3) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_uil0il32bs32Fmsb63(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 0, 32) << 32;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_shiftil6il0bs5Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 6, 5) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_csil21il0bs5Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 21, 5) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_shiftxil6il0bs6Fmsb5(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 6, 6) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_rtil5il0bs5Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 5, 5) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_opil21il0bs5Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 21, 5) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_uil0il2bs7Fmsb8(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 0, 7) << 2;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_bitil11il0bs6Fmsb5(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 11, 6) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_xil10il0bs1_il11il0bs5Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 10, 1) << 0;\n+ value |= extract_bits(instruction, 11, 5) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_maskil14il0bs7Fmsb6(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 14, 7) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_euil0il0bs4Fmsb3(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 0, 4) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_uil4il4bs4Fmsb7(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 4, 4) << 4;\n+ return value;\n+}\n+\n+\n+int64 NMD::extr_sil3il3bs5_il15il8bs1Tmsb8(uint64 instruction)\n+{\n+ int64 value = 0;\n+ value |= extract_bits(instruction, 3, 5) << 3;\n+ value |= extract_bits(instruction, 15, 1) << 8;\n+ value = sign_extend(value, 8);\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_ftil11il0bs5Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 11, 5) << 0;\n+ return value;\n+}\n+\n+\n+int64 NMD::extr_sil0il16bs16_il16il0bs16Tmsb31(uint64 instruction)\n+{\n+ int64 value = 0;\n+ value |= extract_bits(instruction, 0, 16) << 16;\n+ value |= extract_bits(instruction, 16,\n+ 16) << 0;\n+ value = sign_extend(value, 31);\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_uil13il0bs8Fmsb7(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 13, 8) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_xil15il0bs1Fmsb0(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 15, 1) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_xil11il0bs5Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 11, 5) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_uil2il2bs16Fmsb17(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 2, 16) << 2;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_rdil11il0bs5Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 11, 5) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_c0sil16il0bs5Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 16,\n+ 5) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_codeil0il0bs2Fmsb1(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 0, 2) << 0;\n+ return value;\n+}\n+\n+\n+int64 NMD::extr_sil0il25bs1_il1il1bs24Tmsb25(uint64 instruction)\n+{\n+ int64 value = 0;\n+ value |= extract_bits(instruction, 0, 1) << 25;\n+ value |= extract_bits(instruction, 1, 24) << 1;\n+ value = sign_extend(value, 25);\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_xil0il0bs3_il4il0bs1Fmsb2(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 0, 3) << 0;\n+ value |= extract_bits(instruction, 4, 1) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_uil0il0bs2Fmsb1(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 0, 2) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_uil3il3bs1_il8il2bs1Fmsb3(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 3, 1) << 3;\n+ value |= extract_bits(instruction, 8, 1) << 2;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_xil9il0bs3_il16il0bs5Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 9, 3) << 0;\n+ value |= extract_bits(instruction, 16,\n+ 5) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_fdil11il0bs5Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 11, 5) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_xil6il0bs3Fmsb2(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 6, 3) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_uil0il2bs5Fmsb6(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 0, 5) << 2;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_rtz4il5il0bs3_il9il3bs1Fmsb3(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 5, 3) << 0;\n+ value |= extract_bits(instruction, 9, 1) << 3;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_selil11il0bs5Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 11, 5) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_ctil21il0bs5Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 21, 5) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_xil11il0bs1Fmsb0(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 11, 1) << 0;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_uil2il2bs19Fmsb20(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 2, 19) << 2;\n+ return value;\n+}\n+\n+\n+int64 NMD::extr_sil0il0bs3_il4il3bs1Tmsb3(uint64 instruction)\n+{\n+ int64 value = 0;\n+ value |= extract_bits(instruction, 0, 3) << 0;\n+ value |= extract_bits(instruction, 4, 1) << 3;\n+ value = sign_extend(value, 3);\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_uil0il1bs4Fmsb4(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 0, 4) << 1;\n+ return value;\n+}\n+\n+\n+uint64 NMD::extr_xil9il0bs2Fmsb1(uint64 instruction)\n+{\n+ uint64 value = 0;\n+ value |= extract_bits(instruction, 9, 2) << 0;\n+ return value;\n+}\n+\n+\n+bool NMD::BNEC_16__cond(uint64 instruction)\n+{\n+ uint64 rs3 = extr_rs3il4il0bs3Fmsb2(instruction);\n+ uint64 rt3 = extr_rt3il7il0bs3Fmsb2(instruction);\n+ uint64 u = extr_uil0il1bs4Fmsb4(instruction);\n+ return rs3 >= rt3 && u != 0;\n+}\n+\n+\n+bool NMD::ADDIU_32__cond(uint64 instruction)\n+{\n+ uint64 rt = extr_rtil21il0bs5Fmsb4(instruction);\n+ return rt != 0;\n+}\n+\n+\n+bool NMD::P16_BR1_cond(uint64 instruction)\n+{\n+ uint64 u = extr_uil0il1bs4Fmsb4(instruction);\n+ return u != 0;\n+}\n+\n+\n+bool NMD::ADDIU_RS5__cond(uint64 instruction)\n+{\n+ uint64 rt = extr_rtil5il0bs5Fmsb4(instruction);\n+ return rt != 0;\n+}\n+\n+\n+bool NMD::BEQC_16__cond(uint64 instruction)\n+{\n+ uint64 rs3 = extr_rs3il4il0bs3Fmsb2(instruction);\n+ uint64 rt3 = extr_rt3il7il0bs3Fmsb2(instruction);\n+ uint64 u = extr_uil0il1bs4Fmsb4(instruction);\n+ return rs3 < rt3 && u != 0;\n+}\n+\n+\n+bool NMD::SLTU_cond(uint64 instruction)\n+{\n+ uint64 rd = extr_rdil11il0bs5Fmsb4(instruction);\n+ return rd != 0;\n+}\n+\n+\n+bool NMD::PREF_S9__cond(uint64 instruction)\n+{\n+ uint64 hint = extr_hintil21il0bs5Fmsb4(instruction);\n+ return hint != 31;\n+}\n+\n+\n+bool NMD::BALRSC_cond(uint64 instruction)\n+{\n+ uint64 rt = extr_rtil21il0bs5Fmsb4(instruction);\n+ return rt != 0;\n+}\n+\n+\n+bool NMD::MOVE_cond(uint64 instruction)\n+{\n+ uint64 rt = extr_rtil5il0bs5Fmsb4(instruction);\n+ return rt != 0;\n+}\n+\n+\n+bool NMD::PREFE_cond(uint64 instruction)\n+{\n+ uint64 hint = extr_hintil21il0bs5Fmsb4(instruction);\n+ return hint != 31;\n+}\n+\n+\n+std::string NMD::SIGRIE(uint64 instruction)\n+{\n+ uint64 code_value = extr_codeil0il0bs19Fmsb18(instruction);\n+\n+ std::string code = IMMEDIATE(copy(code_value));\n+\n+ return img::format(\"SIGRIE %s\", code);\n+}\n+\n+\n+std::string NMD::SYSCALL_32_(uint64 instruction)\n+{\n+ uint64 code_value = extr_codeil0il0bs18Fmsb17(instruction);\n+\n+ std::string code = IMMEDIATE(copy(code_value));\n+\n+ return img::format(\"SYSCALL %s\", code);\n+}\n+\n+\n+std::string NMD::HYPCALL(uint64 instruction)\n+{\n+ uint64 code_value = extr_codeil0il0bs18Fmsb17(instruction);\n+\n+ std::string code = IMMEDIATE(copy(code_value));\n+\n+ return img::format(\"HYPCALL %s\", code);\n+}\n+\n+\n+std::string NMD::BREAK_32_(uint64 instruction)\n+{\n+ uint64 code_value = extr_codeil0il0bs19Fmsb18(instruction);\n+\n+ std::string code = IMMEDIATE(copy(code_value));\n+\n+ return img::format(\"BREAK %s\", code);\n+}\n+\n+\n+std::string NMD::SDBBP_32_(uint64 instruction)\n+{\n+ uint64 code_value = extr_codeil0il0bs19Fmsb18(instruction);\n+\n+ std::string code = IMMEDIATE(copy(code_value));\n+\n+ return img::format(\"SDBBP %s\", code);\n+}\n+\n+\n+std::string NMD::ADDIU_32_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil0il0bs16Fmsb15(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+\n+ return img::format(\"ADDIU %s, %s, %s\", rt, rs, u);\n+}\n+\n+\n+std::string NMD::TEQ(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"TEQ %s, %s\", rs, rt);\n+}\n+\n+\n+std::string NMD::TNE(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"TNE %s, %s\", rs, rt);\n+}\n+\n+\n+std::string NMD::SEB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SEB %s, %s\", rt, rs);\n+}\n+\n+\n+std::string NMD::SLLV(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"SLLV %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::MUL_32_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"MUL %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::MFC0(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 c0s_value = extr_c0sil16il0bs5Fmsb4(instruction);\n+ uint64 sel_value = extr_selil11il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string c0s = CPR(copy(c0s_value));\n+ std::string sel = IMMEDIATE(copy(sel_value));\n+\n+ return img::format(\"MFC0 %s, %s, %s\", rt, c0s, sel);\n+}\n+\n+\n+std::string NMD::MFHC0(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 c0s_value = extr_c0sil16il0bs5Fmsb4(instruction);\n+ uint64 sel_value = extr_selil11il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string c0s = CPR(copy(c0s_value));\n+ std::string sel = IMMEDIATE(copy(sel_value));\n+\n+ return img::format(\"MFHC0 %s, %s, %s\", rt, c0s, sel);\n+}\n+\n+\n+std::string NMD::SEH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SEH %s, %s\", rt, rs);\n+}\n+\n+\n+std::string NMD::SRLV(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"SRLV %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::MUH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"MUH %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::MTC0(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 c0s_value = extr_c0sil16il0bs5Fmsb4(instruction);\n+ uint64 sel_value = extr_selil11il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string c0s = CPR(copy(c0s_value));\n+ std::string sel = IMMEDIATE(copy(sel_value));\n+\n+ return img::format(\"MTC0 %s, %s, %s\", rt, c0s, sel);\n+}\n+\n+\n+std::string NMD::MTHC0(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 c0s_value = extr_c0sil16il0bs5Fmsb4(instruction);\n+ uint64 sel_value = extr_selil11il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string c0s = CPR(copy(c0s_value));\n+ std::string sel = IMMEDIATE(copy(sel_value));\n+\n+ return img::format(\"MTHC0 %s, %s, %s\", rt, c0s, sel);\n+}\n+\n+\n+std::string NMD::SRAV(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"SRAV %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::MULU(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"MULU %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::MFGC0(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 c0s_value = extr_c0sil16il0bs5Fmsb4(instruction);\n+ uint64 sel_value = extr_selil11il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string c0s = CPR(copy(c0s_value));\n+ std::string sel = IMMEDIATE(copy(sel_value));\n+\n+ return img::format(\"MFGC0 %s, %s, %s\", rt, c0s, sel);\n+}\n+\n+\n+std::string NMD::MFHGC0(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 c0s_value = extr_c0sil16il0bs5Fmsb4(instruction);\n+ uint64 sel_value = extr_selil11il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string c0s = CPR(copy(c0s_value));\n+ std::string sel = IMMEDIATE(copy(sel_value));\n+\n+ return img::format(\"MFHGC0 %s, %s, %s\", rt, c0s, sel);\n+}\n+\n+\n+std::string NMD::ROTRV(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"ROTRV %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::MUHU(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"MUHU %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::MTGC0(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 c0s_value = extr_c0sil16il0bs5Fmsb4(instruction);\n+ uint64 sel_value = extr_selil11il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string c0s = CPR(copy(c0s_value));\n+ std::string sel = IMMEDIATE(copy(sel_value));\n+\n+ return img::format(\"MTGC0 %s, %s, %s\", rt, c0s, sel);\n+}\n+\n+\n+std::string NMD::MTHGC0(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 c0s_value = extr_c0sil16il0bs5Fmsb4(instruction);\n+ uint64 sel_value = extr_selil11il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string c0s = CPR(copy(c0s_value));\n+ std::string sel = IMMEDIATE(copy(sel_value));\n+\n+ return img::format(\"MTHGC0 %s, %s, %s\", rt, c0s, sel);\n+}\n+\n+\n+std::string NMD::ADD(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"ADD %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::DIV(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DIV %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::DMFC0(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 c0s_value = extr_c0sil16il0bs5Fmsb4(instruction);\n+ uint64 sel_value = extr_selil11il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string c0s = CPR(copy(c0s_value));\n+ std::string sel = IMMEDIATE(copy(sel_value));\n+\n+ return img::format(\"DMFC0 %s, %s, %s\", rt, c0s, sel);\n+}\n+\n+\n+std::string NMD::ADDU_32_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"ADDU %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::MOD(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"MOD %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::DMTC0(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 c0s_value = extr_c0sil16il0bs5Fmsb4(instruction);\n+ uint64 sel_value = extr_selil11il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string c0s = CPR(copy(c0s_value));\n+ std::string sel = IMMEDIATE(copy(sel_value));\n+\n+ return img::format(\"DMTC0 %s, %s, %s\", rt, c0s, sel);\n+}\n+\n+\n+std::string NMD::SUB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"SUB %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::DIVU(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DIVU %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::DMFGC0(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 c0s_value = extr_c0sil16il0bs5Fmsb4(instruction);\n+ uint64 sel_value = extr_selil11il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string c0s = CPR(copy(c0s_value));\n+ std::string sel = IMMEDIATE(copy(sel_value));\n+\n+ return img::format(\"DMFGC0 %s, %s, %s\", rt, c0s, sel);\n+}\n+\n+\n+std::string NMD::RDHWR(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 hs_value = extr_hsil16il0bs5Fmsb4(instruction);\n+ uint64 sel_value = extr_selil11il0bs3Fmsb2(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string hs = CPR(copy(hs_value));\n+ std::string sel = IMMEDIATE(copy(sel_value));\n+\n+ return img::format(\"RDHWR %s, %s, %s\", rt, hs, sel);\n+}\n+\n+\n+std::string NMD::SUBU_32_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"SUBU %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::MODU(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"MODU %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::DMTGC0(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 c0s_value = extr_c0sil16il0bs5Fmsb4(instruction);\n+ uint64 sel_value = extr_selil11il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string c0s = CPR(copy(c0s_value));\n+ std::string sel = IMMEDIATE(copy(sel_value));\n+\n+ return img::format(\"DMTGC0 %s, %s, %s\", rt, c0s, sel);\n+}\n+\n+\n+std::string NMD::MOVZ(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"MOVZ %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::MOVN(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"MOVN %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::FORK(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"FORK %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::MFTR(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 c0s_value = extr_c0sil16il0bs5Fmsb4(instruction);\n+ uint64 sel_value = extr_selil11il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil10il0bs1Fmsb0(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string c0s = IMMEDIATE(copy(c0s_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string sel = IMMEDIATE(copy(sel_value));\n+\n+ return img::format(\"MFTR %s, %s, %s, %s\", rt, c0s, u, sel);\n+}\n+\n+\n+std::string NMD::MFHTR(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 c0s_value = extr_c0sil16il0bs5Fmsb4(instruction);\n+ uint64 sel_value = extr_selil11il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil10il0bs1Fmsb0(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string c0s = IMMEDIATE(copy(c0s_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string sel = IMMEDIATE(copy(sel_value));\n+\n+ return img::format(\"MFHTR %s, %s, %s, %s\", rt, c0s, u, sel);\n+}\n+\n+\n+std::string NMD::AND_32_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"AND %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::YIELD(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"YIELD %s, %s\", rt, rs);\n+}\n+\n+\n+std::string NMD::MTTR(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 c0s_value = extr_c0sil16il0bs5Fmsb4(instruction);\n+ uint64 sel_value = extr_selil11il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil10il0bs1Fmsb0(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string c0s = IMMEDIATE(copy(c0s_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string sel = IMMEDIATE(copy(sel_value));\n+\n+ return img::format(\"MTTR %s, %s, %s, %s\", rt, c0s, u, sel);\n+}\n+\n+\n+std::string NMD::MTHTR(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 c0s_value = extr_c0sil16il0bs5Fmsb4(instruction);\n+ uint64 sel_value = extr_selil11il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil10il0bs1Fmsb0(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string c0s = IMMEDIATE(copy(c0s_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string sel = IMMEDIATE(copy(sel_value));\n+\n+ return img::format(\"MTHTR %s, %s, %s, %s\", rt, c0s, u, sel);\n+}\n+\n+\n+std::string NMD::OR_32_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"OR %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::DMT(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DMT %s\", rt);\n+}\n+\n+\n+std::string NMD::DVPE(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DVPE %s\", rt);\n+}\n+\n+\n+std::string NMD::EMT(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"EMT %s\", rt);\n+}\n+\n+\n+std::string NMD::EVPE(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"EVPE %s\", rt);\n+}\n+\n+\n+std::string NMD::NOR(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"NOR %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::XOR_32_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"XOR %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::SLT(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"SLT %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::DVP(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DVP %s\", rt);\n+}\n+\n+\n+std::string NMD::EVP(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"EVP %s\", rt);\n+}\n+\n+\n+std::string NMD::SLTU(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"SLTU %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::SOV(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"SOV %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::SPECIAL2(uint64 instruction)\n+{\n+ uint64 op_value = extr_opil3il0bs23Fmsb22(instruction);\n+\n+ std::string op = IMMEDIATE(copy(op_value));\n+\n+ return img::format(\"SPECIAL2 %s\", op);\n+}\n+\n+\n+std::string NMD::COP2_1(uint64 instruction)\n+{\n+ uint64 cofun_value = extr_cofunil3il0bs23Fmsb22(instruction);\n+\n+ std::string cofun = IMMEDIATE(copy(cofun_value));\n+\n+ return img::format(\"COP2_1 %s\", cofun);\n+}\n+\n+\n+std::string NMD::UDI(uint64 instruction)\n+{\n+ uint64 op_value = extr_opil3il0bs23Fmsb22(instruction);\n+\n+ std::string op = IMMEDIATE(copy(op_value));\n+\n+ return img::format(\"UDI %s\", op);\n+}\n+\n+\n+std::string NMD::CMP_EQ_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"CMP.EQ.PH %s, %s\", rs, rt);\n+}\n+\n+\n+std::string NMD::ADDQ_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"ADDQ.PH %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::ADDQ_S_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"ADDQ_S.PH %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::SHILO(uint64 instruction)\n+{\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ int64 s_value = extr_sil16il0bs6Tmsb5(instruction);\n+\n+ std::string ac = AC(copy(ac_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+\n+ return img::format(\"SHILO %s, %s\", ac, s);\n+}\n+\n+\n+std::string NMD::MULEQ_S_W_PHL(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"MULEQ_S.W.PHL %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::MUL_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"MUL.PH %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::MUL_S_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"MUL_S.PH %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::REPL_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil11il0bs10Tmsb9(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+\n+ return img::format(\"REPL.PH %s, %s\", rt, s);\n+}\n+\n+\n+std::string NMD::CMP_LT_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"CMP.LT.PH %s, %s\", rs, rt);\n+}\n+\n+\n+std::string NMD::ADDQH_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"ADDQH.PH %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::ADDQH_R_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"ADDQH_R.PH %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::MULEQ_S_W_PHR(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"MULEQ_S.W.PHR %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::PRECR_QB_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"PRECR.QB.PH %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::CMP_LE_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"CMP.LE.PH %s, %s\", rs, rt);\n+}\n+\n+\n+std::string NMD::ADDQH_W(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"ADDQH.W %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::ADDQH_R_W(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"ADDQH_R.W %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::MULEU_S_PH_QBL(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"MULEU_S.PH.QBL %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::PRECRQ_QB_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"PRECRQ.QB.PH %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::CMPGU_EQ_QB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"CMPGU.EQ.QB %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::ADDU_QB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"ADDU.QB %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::ADDU_S_QB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"ADDU_S.QB %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::MULEU_S_PH_QBR(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"MULEU_S.PH.QBR %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::PRECRQ_PH_W(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"PRECRQ.PH.W %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::CMPGU_LT_QB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"CMPGU.LT.QB %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::ADDU_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"ADDU.PH %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::ADDU_S_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"ADDU_S.PH %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::MULQ_RS_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"MULQ_RS.PH %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::PRECRQ_RS_PH_W(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"PRECRQ_RS.PH.W %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::CMPGU_LE_QB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"CMPGU.LE.QB %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::ADDUH_QB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"ADDUH.QB %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::ADDUH_R_QB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"ADDUH_R.QB %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::MULQ_S_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"MULQ_S.PH %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::PRECRQU_S_QB_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"PRECRQU_S.QB.PH %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::CMPGDU_EQ_QB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"CMPGDU.EQ.QB %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::SHRAV_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SHRAV.PH %s, %s, %s\", rd, rt, rs);\n+}\n+\n+\n+std::string NMD::SHRAV_R_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SHRAV_R.PH %s, %s, %s\", rd, rt, rs);\n+}\n+\n+\n+std::string NMD::MULQ_RS_W(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"MULQ_RS.W %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::PACKRL_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"PACKRL.PH %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::CMPGDU_LT_QB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"CMPGDU.LT.QB %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::SHRAV_QB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SHRAV.QB %s, %s, %s\", rd, rt, rs);\n+}\n+\n+\n+std::string NMD::SHRAV_R_QB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SHRAV_R.QB %s, %s, %s\", rd, rt, rs);\n+}\n+\n+\n+std::string NMD::MULQ_S_W(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"MULQ_S.W %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::PICK_QB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"PICK.QB %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::CMPGDU_LE_QB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"CMPGDU.LE.QB %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::SUBQ_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"SUBQ.PH %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::SUBQ_S_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"SUBQ_S.PH %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::APPEND(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 sa_value = extr_sail11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string sa = IMMEDIATE(copy(sa_value));\n+\n+ return img::format(\"APPEND %s, %s, %s\", rt, rs, sa);\n+}\n+\n+\n+std::string NMD::PICK_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"PICK.PH %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::CMPU_EQ_QB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"CMPU.EQ.QB %s, %s\", rs, rt);\n+}\n+\n+\n+std::string NMD::SUBQH_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"SUBQH.PH %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::SUBQH_R_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"SUBQH_R.PH %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::PREPEND(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 sa_value = extr_sail11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string sa = IMMEDIATE(copy(sa_value));\n+\n+ return img::format(\"PREPEND %s, %s, %s\", rt, rs, sa);\n+}\n+\n+\n+std::string NMD::CMPU_LT_QB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"CMPU.LT.QB %s, %s\", rs, rt);\n+}\n+\n+\n+std::string NMD::SUBQH_W(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"SUBQH.W %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::SUBQH_R_W(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"SUBQH_R.W %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::MODSUB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"MODSUB %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::CMPU_LE_QB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"CMPU.LE.QB %s, %s\", rs, rt);\n+}\n+\n+\n+std::string NMD::SUBU_QB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"SUBU.QB %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::SUBU_S_QB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"SUBU_S.QB %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::SHRAV_R_W(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SHRAV_R.W %s, %s, %s\", rd, rt, rs);\n+}\n+\n+\n+std::string NMD::SHRA_R_W(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 sa_value = extr_sail11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string sa = IMMEDIATE(copy(sa_value));\n+\n+ return img::format(\"SHRA_R.W %s, %s, %s\", rt, rs, sa);\n+}\n+\n+\n+std::string NMD::ADDQ_S_W(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"ADDQ_S.W %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::SUBU_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"SUBU.PH %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::SUBU_S_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"SUBU_S.PH %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::SHRLV_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SHRLV.PH %s, %s, %s\", rd, rt, rs);\n+}\n+\n+\n+std::string NMD::SHRA_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 sa_value = extr_sail12il0bs4Fmsb3(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string sa = IMMEDIATE(copy(sa_value));\n+\n+ return img::format(\"SHRA.PH %s, %s, %s\", rt, rs, sa);\n+}\n+\n+\n+std::string NMD::SHRA_R_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 sa_value = extr_sail12il0bs4Fmsb3(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string sa = IMMEDIATE(copy(sa_value));\n+\n+ return img::format(\"SHRA_R.PH %s, %s, %s\", rt, rs, sa);\n+}\n+\n+\n+std::string NMD::SUBQ_S_W(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"SUBQ_S.W %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::SUBUH_QB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"SUBUH.QB %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::SUBUH_R_QB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"SUBUH_R.QB %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::SHRLV_QB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SHRLV.QB %s, %s, %s\", rd, rt, rs);\n+}\n+\n+\n+std::string NMD::ADDSC(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"ADDSC %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::SHLLV_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SHLLV.PH %s, %s, %s\", rd, rt, rs);\n+}\n+\n+\n+std::string NMD::SHLLV_S_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SHLLV_S.PH %s, %s, %s\", rd, rt, rs);\n+}\n+\n+\n+std::string NMD::SHLLV_QB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SHLLV.QB %s, %s, %s\", rd, rt, rs);\n+}\n+\n+\n+std::string NMD::SHLL_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 sa_value = extr_sail12il0bs4Fmsb3(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string sa = IMMEDIATE(copy(sa_value));\n+\n+ return img::format(\"SHLL.PH %s, %s, %s\", rt, rs, sa);\n+}\n+\n+\n+std::string NMD::SHLL_S_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 sa_value = extr_sail12il0bs4Fmsb3(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string sa = IMMEDIATE(copy(sa_value));\n+\n+ return img::format(\"SHLL_S.PH %s, %s, %s\", rt, rs, sa);\n+}\n+\n+\n+std::string NMD::ADDWC(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"ADDWC %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::PRECR_SRA_PH_W(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 sa_value = extr_sail11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string sa = IMMEDIATE(copy(sa_value));\n+\n+ return img::format(\"PRECR_SRA.PH.W %s, %s, %s\", rt, rs, sa);\n+}\n+\n+\n+std::string NMD::PRECR_SRA_R_PH_W(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 sa_value = extr_sail11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string sa = IMMEDIATE(copy(sa_value));\n+\n+ return img::format(\"PRECR_SRA_R.PH.W %s, %s, %s\", rt, rs, sa);\n+}\n+\n+\n+std::string NMD::SHLLV_S_W(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SHLLV_S.W %s, %s, %s\", rd, rt, rs);\n+}\n+\n+\n+std::string NMD::SHLL_S_W(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 sa_value = extr_sail11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string sa = IMMEDIATE(copy(sa_value));\n+\n+ return img::format(\"SHLL_S.W %s, %s, %s\", rt, rs, sa);\n+}\n+\n+\n+std::string NMD::LBX(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"LBX %s, %s(%s)\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::SBX(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"SBX %s, %s(%s)\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::LBUX(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"LBUX %s, %s(%s)\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::LHX(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"LHX %s, %s(%s)\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::SHX(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"SHX %s, %s(%s)\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::LHUX(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"LHUX %s, %s(%s)\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::LWUX(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"LWUX %s, %s(%s)\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::LWX(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"LWX %s, %s(%s)\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::SWX(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"SWX %s, %s(%s)\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::LWC1X(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"LWC1X %s, %s(%s)\", ft, rs, rt);\n+}\n+\n+\n+std::string NMD::SWC1X(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"SWC1X %s, %s(%s)\", ft, rs, rt);\n+}\n+\n+\n+std::string NMD::LDX(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"LDX %s, %s(%s)\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::SDX(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"SDX %s, %s(%s)\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::LDC1X(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"LDC1X %s, %s(%s)\", ft, rs, rt);\n+}\n+\n+\n+std::string NMD::SDC1X(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"SDC1X %s, %s(%s)\", ft, rs, rt);\n+}\n+\n+\n+std::string NMD::LHXS(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"LHXS %s, %s(%s)\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::SHXS(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"SHXS %s, %s(%s)\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::LHUXS(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"LHUXS %s, %s(%s)\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::LWUXS(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"LWUXS %s, %s(%s)\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::LWXS_32_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"LWXS %s, %s(%s)\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::SWXS(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"SWXS %s, %s(%s)\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::LWC1XS(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"LWC1XS %s, %s(%s)\", ft, rs, rt);\n+}\n+\n+\n+std::string NMD::SWC1XS(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"SWC1XS %s, %s(%s)\", ft, rs, rt);\n+}\n+\n+\n+std::string NMD::LDXS(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"LDXS %s, %s(%s)\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::SDXS(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"SDXS %s, %s(%s)\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::LDC1XS(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"LDC1XS %s, %s(%s)\", ft, rs, rt);\n+}\n+\n+\n+std::string NMD::SDC1XS(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"SDC1XS %s, %s(%s)\", ft, rs, rt);\n+}\n+\n+\n+std::string NMD::LSA(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 u2_value = extr_u2il9il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u2 = IMMEDIATE(copy(u2_value));\n+\n+ return img::format(\"LSA %s, %s, %s, %s\", rd, rs, rt, u2);\n+}\n+\n+\n+std::string NMD::EXTW(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 shift_value = extr_shiftil6il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+ std::string shift = IMMEDIATE(copy(shift_value));\n+\n+ return img::format(\"EXTW %s, %s, %s, %s\", rd, rs, rt, shift);\n+}\n+\n+\n+std::string NMD::MFHI_DSP_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string ac = AC(copy(ac_value));\n+\n+ return img::format(\"MFHI %s, %s\", rt, ac);\n+}\n+\n+\n+std::string NMD::MFLO_DSP_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string ac = AC(copy(ac_value));\n+\n+ return img::format(\"MFLO %s, %s\", rt, ac);\n+}\n+\n+\n+std::string NMD::MTHI_DSP_(uint64 instruction)\n+{\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rs = GPR(copy(rs_value));\n+ std::string ac = AC(copy(ac_value));\n+\n+ return img::format(\"MTHI %s, %s\", rs, ac);\n+}\n+\n+\n+std::string NMD::MTLO_DSP_(uint64 instruction)\n+{\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rs = GPR(copy(rs_value));\n+ std::string ac = AC(copy(ac_value));\n+\n+ return img::format(\"MTLO %s, %s\", rs, ac);\n+}\n+\n+\n+std::string NMD::MTHLIP(uint64 instruction)\n+{\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rs = GPR(copy(rs_value));\n+ std::string ac = AC(copy(ac_value));\n+\n+ return img::format(\"MTHLIP %s, %s\", rs, ac);\n+}\n+\n+\n+std::string NMD::SHILOV(uint64 instruction)\n+{\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SHILOV %s, %s\", ac, rs);\n+}\n+\n+\n+std::string NMD::RDDSP(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 mask_value = extr_maskil14il0bs7Fmsb6(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string mask = IMMEDIATE(copy(mask_value));\n+\n+ return img::format(\"RDDSP %s, %s\", rt, mask);\n+}\n+\n+\n+std::string NMD::WRDSP(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 mask_value = extr_maskil14il0bs7Fmsb6(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string mask = IMMEDIATE(copy(mask_value));\n+\n+ return img::format(\"WRDSP %s, %s\", rt, mask);\n+}\n+\n+\n+std::string NMD::EXTP(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 size_value = extr_sizeil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string ac = AC(copy(ac_value));\n+ std::string size = IMMEDIATE(copy(size_value));\n+\n+ return img::format(\"EXTP %s, %s, %s\", rt, ac, size);\n+}\n+\n+\n+std::string NMD::EXTPDP(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 size_value = extr_sizeil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string ac = AC(copy(ac_value));\n+ std::string size = IMMEDIATE(copy(size_value));\n+\n+ return img::format(\"EXTPDP %s, %s, %s\", rt, ac, size);\n+}\n+\n+\n+std::string NMD::SHLL_QB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 sa_value = extr_sail13il0bs3Fmsb2(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string sa = IMMEDIATE(copy(sa_value));\n+\n+ return img::format(\"SHLL.QB %s, %s, %s\", rt, rs, sa);\n+}\n+\n+\n+std::string NMD::SHRL_QB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 sa_value = extr_sail13il0bs3Fmsb2(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string sa = IMMEDIATE(copy(sa_value));\n+\n+ return img::format(\"SHRL.QB %s, %s, %s\", rt, rs, sa);\n+}\n+\n+\n+std::string NMD::MAQ_S_W_PHR(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"MAQ_S.W.PHR %s, %s, %s\", ac, rs, rt);\n+}\n+\n+\n+std::string NMD::MAQ_SA_W_PHR(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"MAQ_SA.W.PHR %s, %s, %s\", ac, rs, rt);\n+}\n+\n+\n+std::string NMD::MAQ_S_W_PHL(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"MAQ_S.W.PHL %s, %s, %s\", ac, rs, rt);\n+}\n+\n+\n+std::string NMD::MAQ_SA_W_PHL(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"MAQ_SA.W.PHL %s, %s, %s\", ac, rs, rt);\n+}\n+\n+\n+std::string NMD::EXTR_W(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 shift_value = extr_shiftil16il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string ac = AC(copy(ac_value));\n+ std::string shift = IMMEDIATE(copy(shift_value));\n+\n+ return img::format(\"EXTR.W %s, %s, %s\", rt, ac, shift);\n+}\n+\n+\n+std::string NMD::EXTR_R_W(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 shift_value = extr_shiftil16il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string ac = AC(copy(ac_value));\n+ std::string shift = IMMEDIATE(copy(shift_value));\n+\n+ return img::format(\"EXTR_R.W %s, %s, %s\", rt, ac, shift);\n+}\n+\n+\n+std::string NMD::EXTR_RS_W(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 shift_value = extr_shiftil16il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string ac = AC(copy(ac_value));\n+ std::string shift = IMMEDIATE(copy(shift_value));\n+\n+ return img::format(\"EXTR_RS.W %s, %s, %s\", rt, ac, shift);\n+}\n+\n+\n+std::string NMD::EXTR_S_H(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 shift_value = extr_shiftil16il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string ac = AC(copy(ac_value));\n+ std::string shift = IMMEDIATE(copy(shift_value));\n+\n+ return img::format(\"EXTR_S.H %s, %s, %s\", rt, ac, shift);\n+}\n+\n+\n+std::string NMD::DPA_W_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DPA.W.PH %s, %s, %s\", ac, rs, rt);\n+}\n+\n+\n+std::string NMD::DPAQ_S_W_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DPAQ_S.W.PH %s, %s, %s\", ac, rs, rt);\n+}\n+\n+\n+std::string NMD::DPS_W_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DPS.W.PH %s, %s, %s\", ac, rs, rt);\n+}\n+\n+\n+std::string NMD::DPSQ_S_W_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DPSQ_S.W.PH %s, %s, %s\", ac, rs, rt);\n+}\n+\n+\n+std::string NMD::MADD_DSP_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"MADD %s, %s, %s\", ac, rs, rt);\n+}\n+\n+\n+std::string NMD::MULT_DSP_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"MULT %s, %s, %s\", ac, rs, rt);\n+}\n+\n+\n+std::string NMD::EXTRV_W(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"EXTRV.W %s, %s, %s\", rt, ac, rs);\n+}\n+\n+\n+std::string NMD::DPAX_W_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DPAX.W.PH %s, %s, %s\", ac, rs, rt);\n+}\n+\n+\n+std::string NMD::DPAQ_SA_L_W(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DPAQ_SA.L.W %s, %s, %s\", ac, rs, rt);\n+}\n+\n+\n+std::string NMD::DPSX_W_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DPSX.W.PH %s, %s, %s\", ac, rs, rt);\n+}\n+\n+\n+std::string NMD::DPSQ_SA_L_W(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DPSQ_SA.L.W %s, %s, %s\", ac, rs, rt);\n+}\n+\n+\n+std::string NMD::MADDU_DSP_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"MADDU %s, %s, %s\", ac, rs, rt);\n+}\n+\n+\n+std::string NMD::MULTU_DSP_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"MULTU %s, %s, %s\", ac, rs, rt);\n+}\n+\n+\n+std::string NMD::EXTRV_R_W(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"EXTRV_R.W %s, %s, %s\", rt, ac, rs);\n+}\n+\n+\n+std::string NMD::DPAU_H_QBL(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DPAU.H.QBL %s, %s, %s\", ac, rs, rt);\n+}\n+\n+\n+std::string NMD::DPAQX_S_W_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DPAQX_S.W.PH %s, %s, %s\", ac, rs, rt);\n+}\n+\n+\n+std::string NMD::DPSU_H_QBL(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DPSU.H.QBL %s, %s, %s\", ac, rs, rt);\n+}\n+\n+\n+std::string NMD::DPSQX_S_W_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DPSQX_S.W.PH %s, %s, %s\", ac, rs, rt);\n+}\n+\n+\n+std::string NMD::EXTPV(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"EXTPV %s, %s, %s\", rt, ac, rs);\n+}\n+\n+\n+std::string NMD::MSUB_DSP_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"MSUB %s, %s, %s\", ac, rs, rt);\n+}\n+\n+\n+std::string NMD::MULSA_W_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"MULSA.W.PH %s, %s, %s\", ac, rs, rt);\n+}\n+\n+\n+std::string NMD::EXTRV_RS_W(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"EXTRV_RS.W %s, %s, %s\", rt, ac, rs);\n+}\n+\n+\n+std::string NMD::DPAU_H_QBR(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DPAU.H.QBR %s, %s, %s\", ac, rs, rt);\n+}\n+\n+\n+std::string NMD::DPAQX_SA_W_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DPAQX_SA.W.PH %s, %s, %s\", ac, rs, rt);\n+}\n+\n+\n+std::string NMD::DPSU_H_QBR(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DPSU.H.QBR %s, %s, %s\", ac, rs, rt);\n+}\n+\n+\n+std::string NMD::DPSQX_SA_W_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DPSQX_SA.W.PH %s, %s, %s\", ac, rs, rt);\n+}\n+\n+\n+std::string NMD::EXTPDPV(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"EXTPDPV %s, %s, %s\", rt, ac, rs);\n+}\n+\n+\n+std::string NMD::MSUBU_DSP_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"MSUBU %s, %s, %s\", ac, rs, rt);\n+}\n+\n+\n+std::string NMD::MULSAQ_S_W_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"MULSAQ_S.W.PH %s, %s, %s\", ac, rs, rt);\n+}\n+\n+\n+std::string NMD::EXTRV_S_H(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ac_value = extr_acil14il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string ac = AC(copy(ac_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"EXTRV_S.H %s, %s, %s\", rt, ac, rs);\n+}\n+\n+\n+std::string NMD::ABSQ_S_QB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"ABSQ_S.QB %s, %s\", rt, rs);\n+}\n+\n+\n+std::string NMD::REPLV_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"REPLV.PH %s, %s\", rt, rs);\n+}\n+\n+\n+std::string NMD::ABSQ_S_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"ABSQ_S.PH %s, %s\", rt, rs);\n+}\n+\n+\n+std::string NMD::REPLV_QB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"REPLV.QB %s, %s\", rt, rs);\n+}\n+\n+\n+std::string NMD::ABSQ_S_W(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"ABSQ_S.W %s, %s\", rt, rs);\n+}\n+\n+\n+std::string NMD::INSV(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"INSV %s, %s\", rt, rs);\n+}\n+\n+\n+std::string NMD::CLO(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"CLO %s, %s\", rt, rs);\n+}\n+\n+\n+std::string NMD::MFC2(uint64 instruction)\n+{\n+ uint64 cs_value = extr_csil16il0bs5Fmsb4(instruction);\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string cs = CPR(copy(cs_value));\n+\n+ return img::format(\"MFC2 %s, %s\", rt, cs);\n+}\n+\n+\n+std::string NMD::PRECEQ_W_PHL(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"PRECEQ.W.PHL %s, %s\", rt, rs);\n+}\n+\n+\n+std::string NMD::CLZ(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"CLZ %s, %s\", rt, rs);\n+}\n+\n+\n+std::string NMD::MTC2(uint64 instruction)\n+{\n+ uint64 cs_value = extr_csil16il0bs5Fmsb4(instruction);\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string cs = CPR(copy(cs_value));\n+\n+ return img::format(\"MTC2 %s, %s\", rt, cs);\n+}\n+\n+\n+std::string NMD::PRECEQ_W_PHR(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"PRECEQ.W.PHR %s, %s\", rt, rs);\n+}\n+\n+\n+std::string NMD::DMFC2(uint64 instruction)\n+{\n+ uint64 cs_value = extr_csil16il0bs5Fmsb4(instruction);\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string cs = CPR(copy(cs_value));\n+\n+ return img::format(\"DMFC2 %s, %s\", rt, cs);\n+}\n+\n+\n+std::string NMD::PRECEQU_PH_QBL(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"PRECEQU.PH.QBL %s, %s\", rt, rs);\n+}\n+\n+\n+std::string NMD::PRECEQU_PH_QBLA(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"PRECEQU.PH.QBLA %s, %s\", rt, rs);\n+}\n+\n+\n+std::string NMD::DMTC2(uint64 instruction)\n+{\n+ uint64 cs_value = extr_csil16il0bs5Fmsb4(instruction);\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string cs = CPR(copy(cs_value));\n+\n+ return img::format(\"DMTC2 %s, %s\", rt, cs);\n+}\n+\n+\n+std::string NMD::MFHC2(uint64 instruction)\n+{\n+ uint64 cs_value = extr_csil16il0bs5Fmsb4(instruction);\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string cs = CPR(copy(cs_value));\n+\n+ return img::format(\"MFHC2 %s, %s\", rt, cs);\n+}\n+\n+\n+std::string NMD::PRECEQU_PH_QBR(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"PRECEQU.PH.QBR %s, %s\", rt, rs);\n+}\n+\n+\n+std::string NMD::PRECEQU_PH_QBRA(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"PRECEQU.PH.QBRA %s, %s\", rt, rs);\n+}\n+\n+\n+std::string NMD::MTHC2(uint64 instruction)\n+{\n+ uint64 cs_value = extr_csil16il0bs5Fmsb4(instruction);\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string cs = CPR(copy(cs_value));\n+\n+ return img::format(\"MTHC2 %s, %s\", rt, cs);\n+}\n+\n+\n+std::string NMD::PRECEU_PH_QBL(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"PRECEU.PH.QBL %s, %s\", rt, rs);\n+}\n+\n+\n+std::string NMD::PRECEU_PH_QBLA(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"PRECEU.PH.QBLA %s, %s\", rt, rs);\n+}\n+\n+\n+std::string NMD::CFC2(uint64 instruction)\n+{\n+ uint64 cs_value = extr_csil16il0bs5Fmsb4(instruction);\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string cs = CPR(copy(cs_value));\n+\n+ return img::format(\"CFC2 %s, %s\", rt, cs);\n+}\n+\n+\n+std::string NMD::PRECEU_PH_QBR(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"PRECEU.PH.QBR %s, %s\", rt, rs);\n+}\n+\n+\n+std::string NMD::PRECEU_PH_QBRA(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"PRECEU.PH.QBRA %s, %s\", rt, rs);\n+}\n+\n+\n+std::string NMD::CTC2(uint64 instruction)\n+{\n+ uint64 cs_value = extr_csil16il0bs5Fmsb4(instruction);\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string cs = CPR(copy(cs_value));\n+\n+ return img::format(\"CTC2 %s, %s\", rt, cs);\n+}\n+\n+\n+std::string NMD::RADDU_W_QB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"RADDU.W.QB %s, %s\", rt, rs);\n+}\n+\n+\n+std::string NMD::TLBGP(uint64 instruction)\n+{\n+ (void)instruction;\n+\n+ return \"TLBGP \";\n+}\n+\n+\n+std::string NMD::TLBP(uint64 instruction)\n+{\n+ (void)instruction;\n+\n+ return \"TLBP \";\n+}\n+\n+\n+std::string NMD::TLBGINV(uint64 instruction)\n+{\n+ (void)instruction;\n+\n+ return \"TLBGINV \";\n+}\n+\n+\n+std::string NMD::TLBINV(uint64 instruction)\n+{\n+ (void)instruction;\n+\n+ return \"TLBINV \";\n+}\n+\n+\n+std::string NMD::TLBGR(uint64 instruction)\n+{\n+ (void)instruction;\n+\n+ return \"TLBGR \";\n+}\n+\n+\n+std::string NMD::TLBR(uint64 instruction)\n+{\n+ (void)instruction;\n+\n+ return \"TLBR \";\n+}\n+\n+\n+std::string NMD::TLBGINVF(uint64 instruction)\n+{\n+ (void)instruction;\n+\n+ return \"TLBGINVF \";\n+}\n+\n+\n+std::string NMD::TLBINVF(uint64 instruction)\n+{\n+ (void)instruction;\n+\n+ return \"TLBINVF \";\n+}\n+\n+\n+std::string NMD::TLBGWI(uint64 instruction)\n+{\n+ (void)instruction;\n+\n+ return \"TLBGWI \";\n+}\n+\n+\n+std::string NMD::TLBWI(uint64 instruction)\n+{\n+ (void)instruction;\n+\n+ return \"TLBWI \";\n+}\n+\n+\n+std::string NMD::TLBGWR(uint64 instruction)\n+{\n+ (void)instruction;\n+\n+ return \"TLBGWR \";\n+}\n+\n+\n+std::string NMD::TLBWR(uint64 instruction)\n+{\n+ (void)instruction;\n+\n+ return \"TLBWR \";\n+}\n+\n+\n+std::string NMD::DI(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DI %s\", rt);\n+}\n+\n+\n+std::string NMD::EI(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"EI %s\", rt);\n+}\n+\n+\n+std::string NMD::WAIT(uint64 instruction)\n+{\n+ uint64 code_value = extr_codeil16il0bs10Fmsb9(instruction);\n+\n+ std::string code = IMMEDIATE(copy(code_value));\n+\n+ return img::format(\"WAIT %s\", code);\n+}\n+\n+\n+std::string NMD::IRET(uint64 instruction)\n+{\n+ (void)instruction;\n+\n+ return \"IRET \";\n+}\n+\n+\n+std::string NMD::RDPGPR(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"RDPGPR %s, %s\", rt, rs);\n+}\n+\n+\n+std::string NMD::DERET(uint64 instruction)\n+{\n+ (void)instruction;\n+\n+ return \"DERET \";\n+}\n+\n+\n+std::string NMD::WRPGPR(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"WRPGPR %s, %s\", rt, rs);\n+}\n+\n+\n+std::string NMD::ERET(uint64 instruction)\n+{\n+ (void)instruction;\n+\n+ return \"ERET \";\n+}\n+\n+\n+std::string NMD::ERETNC(uint64 instruction)\n+{\n+ (void)instruction;\n+\n+ return \"ERETNC \";\n+}\n+\n+\n+std::string NMD::SHRA_QB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 sa_value = extr_sail13il0bs3Fmsb2(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string sa = IMMEDIATE(copy(sa_value));\n+\n+ return img::format(\"SHRA.QB %s, %s, %s\", rt, rs, sa);\n+}\n+\n+\n+std::string NMD::SHRA_R_QB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 sa_value = extr_sail13il0bs3Fmsb2(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string sa = IMMEDIATE(copy(sa_value));\n+\n+ return img::format(\"SHRA_R.QB %s, %s, %s\", rt, rs, sa);\n+}\n+\n+\n+std::string NMD::SHRL_PH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 sa_value = extr_sail12il0bs4Fmsb3(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string sa = IMMEDIATE(copy(sa_value));\n+\n+ return img::format(\"SHRL.PH %s, %s, %s\", rt, rs, sa);\n+}\n+\n+\n+std::string NMD::REPL_QB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil13il0bs8Fmsb7(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+\n+ return img::format(\"REPL.QB %s, %s\", rt, u);\n+}\n+\n+\n+std::string NMD::ADDIU_GP_W_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil2il2bs19Fmsb20(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+\n+ return img::format(\"ADDIU %s, $%d, %s\", rt, 28, u);\n+}\n+\n+\n+std::string NMD::LD_GP_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil3il3bs18Fmsb20(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+\n+ return img::format(\"LD %s, %s($%d)\", rt, u, 28);\n+}\n+\n+\n+std::string NMD::SD_GP_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil3il3bs18Fmsb20(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+\n+ return img::format(\"SD %s, %s($%d)\", rt, u, 28);\n+}\n+\n+\n+std::string NMD::LW_GP_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil2il2bs19Fmsb20(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+\n+ return img::format(\"LW %s, %s($%d)\", rt, u, 28);\n+}\n+\n+\n+std::string NMD::SW_GP_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil2il2bs19Fmsb20(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+\n+ return img::format(\"SW %s, %s($%d)\", rt, u, 28);\n+}\n+\n+\n+std::string NMD::LI_48_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil37il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il16bs16_il16il0bs16Tmsb31(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+\n+ return img::format(\"LI %s, %s\", rt, s);\n+}\n+\n+\n+std::string NMD::ADDIU_48_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil37il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il16bs16_il16il0bs16Tmsb31(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+\n+ return img::format(\"ADDIU %s, %s\", rt, s);\n+}\n+\n+\n+std::string NMD::ADDIU_GP48_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil37il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il16bs16_il16il0bs16Tmsb31(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+\n+ return img::format(\"ADDIU %s, $%d, %s\", rt, 28, s);\n+}\n+\n+\n+std::string NMD::ADDIUPC_48_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil37il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il16bs16_il16il0bs16Tmsb31(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = ADDRESS(encode_s_from_address(s_value), 6);\n+\n+ return img::format(\"ADDIUPC %s, %s\", rt, s);\n+}\n+\n+\n+std::string NMD::LWPC_48_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil37il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il16bs16_il16il0bs16Tmsb31(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = ADDRESS(encode_s_from_address(s_value), 6);\n+\n+ return img::format(\"LWPC %s, %s\", rt, s);\n+}\n+\n+\n+std::string NMD::SWPC_48_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil37il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il16bs16_il16il0bs16Tmsb31(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = ADDRESS(encode_s_from_address(s_value), 6);\n+\n+ return img::format(\"SWPC %s, %s\", rt, s);\n+}\n+\n+\n+std::string NMD::DADDIU_48_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil37il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il16bs16_il16il0bs16Tmsb31(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+\n+ return img::format(\"DADDIU %s, %s\", rt, s);\n+}\n+\n+\n+std::string NMD::DLUI_48_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil37il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil0il32bs32Fmsb63(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+\n+ return img::format(\"DLUI %s, %s\", rt, u);\n+}\n+\n+\n+std::string NMD::LDPC_48_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil37il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il16bs16_il16il0bs16Tmsb31(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = ADDRESS(encode_s_from_address(s_value), 6);\n+\n+ return img::format(\"LDPC %s, %s\", rt, s);\n+}\n+\n+\n+std::string NMD::SDPC_48_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil37il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il16bs16_il16il0bs16Tmsb31(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = ADDRESS(encode_s_from_address(s_value), 6);\n+\n+ return img::format(\"SDPC %s, %s\", rt, s);\n+}\n+\n+\n+std::string NMD::ORI(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil0il0bs12Fmsb11(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+\n+ return img::format(\"ORI %s, %s, %s\", rt, rs, u);\n+}\n+\n+\n+std::string NMD::XORI(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil0il0bs12Fmsb11(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+\n+ return img::format(\"XORI %s, %s, %s\", rt, rs, u);\n+}\n+\n+\n+std::string NMD::ANDI_32_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil0il0bs12Fmsb11(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+\n+ return img::format(\"ANDI %s, %s, %s\", rt, rs, u);\n+}\n+\n+\n+std::string NMD::SAVE_32_(uint64 instruction)\n+{\n+ uint64 count_value = extr_countil16il0bs4Fmsb3(instruction);\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil3il3bs9Fmsb11(instruction);\n+ uint64 gp_value = extr_gpil2il0bs1Fmsb0(instruction);\n+\n+ std::string u = IMMEDIATE(copy(u_value));\n+ return img::format(\"SAVE %s%s\", u,\n+ save_restore_list(rt_value, count_value, gp_value));\n+}\n+\n+\n+std::string NMD::RESTORE_32_(uint64 instruction)\n+{\n+ uint64 count_value = extr_countil16il0bs4Fmsb3(instruction);\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil3il3bs9Fmsb11(instruction);\n+ uint64 gp_value = extr_gpil2il0bs1Fmsb0(instruction);\n+\n+ std::string u = IMMEDIATE(copy(u_value));\n+ return img::format(\"RESTORE %s%s\", u,\n+ save_restore_list(rt_value, count_value, gp_value));\n+}\n+\n+\n+std::string NMD::RESTORE_JRC_32_(uint64 instruction)\n+{\n+ uint64 count_value = extr_countil16il0bs4Fmsb3(instruction);\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil3il3bs9Fmsb11(instruction);\n+ uint64 gp_value = extr_gpil2il0bs1Fmsb0(instruction);\n+\n+ std::string u = IMMEDIATE(copy(u_value));\n+ return img::format(\"RESTORE.JRC %s%s\", u,\n+ save_restore_list(rt_value, count_value, gp_value));\n+}\n+\n+\n+std::string NMD::SAVEF(uint64 instruction)\n+{\n+ uint64 count_value = extr_countil16il0bs4Fmsb3(instruction);\n+ uint64 u_value = extr_uil3il3bs9Fmsb11(instruction);\n+\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string count = IMMEDIATE(copy(count_value));\n+\n+ return img::format(\"SAVEF %s, %s\", u, count);\n+}\n+\n+\n+std::string NMD::RESTOREF(uint64 instruction)\n+{\n+ uint64 count_value = extr_countil16il0bs4Fmsb3(instruction);\n+ uint64 u_value = extr_uil3il3bs9Fmsb11(instruction);\n+\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string count = IMMEDIATE(copy(count_value));\n+\n+ return img::format(\"RESTOREF %s, %s\", u, count);\n+}\n+\n+\n+std::string NMD::SLTI(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil0il0bs12Fmsb11(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+\n+ return img::format(\"SLTI %s, %s, %s\", rt, rs, u);\n+}\n+\n+\n+std::string NMD::SLTIU(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil0il0bs12Fmsb11(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+\n+ return img::format(\"SLTIU %s, %s, %s\", rt, rs, u);\n+}\n+\n+\n+std::string NMD::SEQI(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil0il0bs12Fmsb11(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+\n+ return img::format(\"SEQI %s, %s, %s\", rt, rs, u);\n+}\n+\n+\n+std::string NMD::ADDIU_NEG_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil0il0bs12Fmsb11(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string u = IMMEDIATE(neg_copy(u_value));\n+\n+ return img::format(\"ADDIU %s, %s, %s\", rt, rs, u);\n+}\n+\n+\n+std::string NMD::DADDIU_U12_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil0il0bs12Fmsb11(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+\n+ return img::format(\"DADDIU %s, %s, %s\", rt, rs, u);\n+}\n+\n+\n+std::string NMD::DADDIU_NEG_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil0il0bs12Fmsb11(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string u = IMMEDIATE(neg_copy(u_value));\n+\n+ return img::format(\"DADDIU %s, %s, %s\", rt, rs, u);\n+}\n+\n+\n+std::string NMD::DROTX(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 shift_value = extr_shiftil0il0bs6Fmsb5(instruction);\n+ uint64 shiftx_value = extr_shiftxil6il0bs6Fmsb5(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string shift = IMMEDIATE(copy(shift_value));\n+ std::string shiftx = IMMEDIATE(copy(shiftx_value));\n+\n+ return img::format(\"DROTX %s, %s, %s, %s\", rt, rs, shift, shiftx);\n+}\n+\n+\n+std::string NMD::NOP_32_(uint64 instruction)\n+{\n+ (void)instruction;\n+\n+ return \"NOP \";\n+}\n+\n+\n+std::string NMD::EHB(uint64 instruction)\n+{\n+ (void)instruction;\n+\n+ return \"EHB \";\n+}\n+\n+\n+std::string NMD::PAUSE(uint64 instruction)\n+{\n+ (void)instruction;\n+\n+ return \"PAUSE \";\n+}\n+\n+\n+std::string NMD::SYNC(uint64 instruction)\n+{\n+ uint64 stype_value = extr_stypeil16il0bs5Fmsb4(instruction);\n+\n+ std::string stype = IMMEDIATE(copy(stype_value));\n+\n+ return img::format(\"SYNC %s\", stype);\n+}\n+\n+\n+std::string NMD::SLL_32_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 shift_value = extr_shiftil0il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string shift = IMMEDIATE(copy(shift_value));\n+\n+ return img::format(\"SLL %s, %s, %s\", rt, rs, shift);\n+}\n+\n+\n+std::string NMD::SRL_32_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 shift_value = extr_shiftil0il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string shift = IMMEDIATE(copy(shift_value));\n+\n+ return img::format(\"SRL %s, %s, %s\", rt, rs, shift);\n+}\n+\n+\n+std::string NMD::SRA(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 shift_value = extr_shiftil0il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string shift = IMMEDIATE(copy(shift_value));\n+\n+ return img::format(\"SRA %s, %s, %s\", rt, rs, shift);\n+}\n+\n+\n+std::string NMD::ROTR(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 shift_value = extr_shiftil0il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string shift = IMMEDIATE(copy(shift_value));\n+\n+ return img::format(\"ROTR %s, %s, %s\", rt, rs, shift);\n+}\n+\n+\n+std::string NMD::DSLL(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 shift_value = extr_shiftil0il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string shift = IMMEDIATE(copy(shift_value));\n+\n+ return img::format(\"DSLL %s, %s, %s\", rt, rs, shift);\n+}\n+\n+\n+std::string NMD::DSLL32(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 shift_value = extr_shiftil0il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string shift = IMMEDIATE(copy(shift_value));\n+\n+ return img::format(\"DSLL32 %s, %s, %s\", rt, rs, shift);\n+}\n+\n+\n+std::string NMD::DSRL(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 shift_value = extr_shiftil0il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string shift = IMMEDIATE(copy(shift_value));\n+\n+ return img::format(\"DSRL %s, %s, %s\", rt, rs, shift);\n+}\n+\n+\n+std::string NMD::DSRL32(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 shift_value = extr_shiftil0il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string shift = IMMEDIATE(copy(shift_value));\n+\n+ return img::format(\"DSRL32 %s, %s, %s\", rt, rs, shift);\n+}\n+\n+\n+std::string NMD::DSRA(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 shift_value = extr_shiftil0il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string shift = IMMEDIATE(copy(shift_value));\n+\n+ return img::format(\"DSRA %s, %s, %s\", rt, rs, shift);\n+}\n+\n+\n+std::string NMD::DSRA32(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 shift_value = extr_shiftil0il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string shift = IMMEDIATE(copy(shift_value));\n+\n+ return img::format(\"DSRA32 %s, %s, %s\", rt, rs, shift);\n+}\n+\n+\n+std::string NMD::DROTR(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 shift_value = extr_shiftil0il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string shift = IMMEDIATE(copy(shift_value));\n+\n+ return img::format(\"DROTR %s, %s, %s\", rt, rs, shift);\n+}\n+\n+\n+std::string NMD::DROTR32(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 shift_value = extr_shiftil0il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string shift = IMMEDIATE(copy(shift_value));\n+\n+ return img::format(\"DROTR32 %s, %s, %s\", rt, rs, shift);\n+}\n+\n+\n+std::string NMD::ROTX(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 shift_value = extr_shiftil0il0bs5Fmsb4(instruction);\n+ uint64 shiftx_value = extr_shiftxil7il1bs4Fmsb4(instruction);\n+ uint64 stripe_value = extr_stripeil6il0bs1Fmsb0(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string shift = IMMEDIATE(copy(shift_value));\n+ std::string shiftx = IMMEDIATE(copy(shiftx_value));\n+ std::string stripe = IMMEDIATE(copy(stripe_value));\n+\n+ return img::format(\"ROTX %s, %s, %s, %s, %s\",\n+ rt, rs, shift, shiftx, stripe);\n+}\n+\n+\n+std::string NMD::INS(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 msbd_value = extr_msbdil6il0bs5Fmsb4(instruction);\n+ uint64 lsb_value = extr_lsbil0il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string pos = IMMEDIATE(encode_lsb_from_pos_and_size(lsb_value));\n+ std::string size = IMMEDIATE(encode_lsb_from_pos_and_size(msbd_value));\n+ /* !!!!!!!!!! - no conversion function */\n+\n+ return img::format(\"INS %s, %s, %s, %s\", rt, rs, pos, size);\n+ /* hand edited */\n+}\n+\n+\n+std::string NMD::DINSU(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 msbd_value = extr_msbdil6il0bs5Fmsb4(instruction);\n+ uint64 lsb_value = extr_lsbil0il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string pos = IMMEDIATE(encode_lsb_from_pos_and_size(lsb_value));\n+ std::string size = IMMEDIATE(encode_lsb_from_pos_and_size(msbd_value));\n+ /* !!!!!!!!!! - no conversion function */\n+\n+ return img::format(\"DINSU %s, %s, %s, %s\", rt, rs, pos, size);\n+ /* hand edited */\n+}\n+\n+\n+std::string NMD::DINSM(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 msbd_value = extr_msbdil6il0bs5Fmsb4(instruction);\n+ uint64 lsb_value = extr_lsbil0il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string pos = IMMEDIATE(encode_lsb_from_pos_and_size(lsb_value));\n+ std::string size = IMMEDIATE(encode_lsb_from_pos_and_size(msbd_value));\n+ /* !!!!!!!!!! - no conversion function */\n+\n+ return img::format(\"DINSM %s, %s, %s, %s\", rt, rs, pos, size);\n+ /* hand edited */\n+}\n+\n+\n+std::string NMD::DINS(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 msbd_value = extr_msbdil6il0bs5Fmsb4(instruction);\n+ uint64 lsb_value = extr_lsbil0il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string pos = IMMEDIATE(encode_lsb_from_pos_and_size(lsb_value));\n+ std::string size = IMMEDIATE(encode_lsb_from_pos_and_size(msbd_value));\n+ /* !!!!!!!!!! - no conversion function */\n+\n+ return img::format(\"DINS %s, %s, %s, %s\", rt, rs, pos, size);\n+ /* hand edited */\n+}\n+\n+\n+std::string NMD::EXT(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 msbd_value = extr_msbdil6il0bs5Fmsb4(instruction);\n+ uint64 lsb_value = extr_lsbil0il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string lsb = IMMEDIATE(copy(lsb_value));\n+ std::string msbd = IMMEDIATE(encode_msbd_from_size(msbd_value));\n+\n+ return img::format(\"EXT %s, %s, %s, %s\", rt, rs, lsb, msbd);\n+}\n+\n+\n+std::string NMD::DEXTU(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 msbd_value = extr_msbdil6il0bs5Fmsb4(instruction);\n+ uint64 lsb_value = extr_lsbil0il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string lsb = IMMEDIATE(copy(lsb_value));\n+ std::string msbd = IMMEDIATE(encode_msbd_from_size(msbd_value));\n+\n+ return img::format(\"DEXTU %s, %s, %s, %s\", rt, rs, lsb, msbd);\n+}\n+\n+\n+std::string NMD::DEXTM(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 msbd_value = extr_msbdil6il0bs5Fmsb4(instruction);\n+ uint64 lsb_value = extr_lsbil0il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string lsb = IMMEDIATE(copy(lsb_value));\n+ std::string msbd = IMMEDIATE(encode_msbd_from_size(msbd_value));\n+\n+ return img::format(\"DEXTM %s, %s, %s, %s\", rt, rs, lsb, msbd);\n+}\n+\n+\n+std::string NMD::DEXT(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 msbd_value = extr_msbdil6il0bs5Fmsb4(instruction);\n+ uint64 lsb_value = extr_lsbil0il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string lsb = IMMEDIATE(copy(lsb_value));\n+ std::string msbd = IMMEDIATE(encode_msbd_from_size(msbd_value));\n+\n+ return img::format(\"DEXT %s, %s, %s, %s\", rt, rs, lsb, msbd);\n+}\n+\n+\n+std::string NMD::RINT_S(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"RINT.S %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::RINT_D(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"RINT.D %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::ADD_S(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"ADD.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::SELEQZ_S(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"SELEQZ.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::SELEQZ_D(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"SELEQZ.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CLASS_S(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"CLASS.S %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::CLASS_D(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"CLASS.D %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::SUB_S(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"SUB.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::SELNEZ_S(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"SELNEZ.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::SELNEZ_D(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"SELNEZ.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::MUL_S(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"MUL.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::SEL_S(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"SEL.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::SEL_D(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"SEL.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::DIV_S(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"DIV.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::ADD_D(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"ADD.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::SUB_D(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"SUB.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::MUL_D(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"MUL.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::MADDF_S(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"MADDF.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::MADDF_D(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"MADDF.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::DIV_D(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"DIV.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::MSUBF_S(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"MSUBF.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::MSUBF_D(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"MSUBF.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::MIN_S(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"MIN.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::MIN_D(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"MIN.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::MAX_S(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"MAX.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::MAX_D(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"MAX.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::MINA_S(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"MINA.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::MINA_D(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"MINA.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::MAXA_S(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"MAXA.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::MAXA_D(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"MAXA.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CVT_L_S(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"CVT.L.S %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::CVT_L_D(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"CVT.L.D %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::RSQRT_S(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"RSQRT.S %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::RSQRT_D(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"RSQRT.D %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::FLOOR_L_S(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"FLOOR.L.S %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::FLOOR_L_D(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"FLOOR.L.D %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::CVT_W_S(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"CVT.W.S %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::CVT_W_D(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"CVT.W.D %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::SQRT_S(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"SQRT.S %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::SQRT_D(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"SQRT.D %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::FLOOR_W_S(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"FLOOR.W.S %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::FLOOR_W_D(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"FLOOR.W.D %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::CFC1(uint64 instruction)\n+{\n+ uint64 cs_value = extr_csil16il0bs5Fmsb4(instruction);\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string cs = CPR(copy(cs_value));\n+\n+ return img::format(\"CFC1 %s, %s\", rt, cs);\n+}\n+\n+\n+std::string NMD::RECIP_S(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"RECIP.S %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::RECIP_D(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"RECIP.D %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::CEIL_L_S(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"CEIL.L.S %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::CEIL_L_D(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"CEIL.L.D %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::CTC1(uint64 instruction)\n+{\n+ uint64 cs_value = extr_csil16il0bs5Fmsb4(instruction);\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string cs = CPR(copy(cs_value));\n+\n+ return img::format(\"CTC1 %s, %s\", rt, cs);\n+}\n+\n+\n+std::string NMD::CEIL_W_S(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"CEIL.W.S %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::CEIL_W_D(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"CEIL.W.D %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::MFC1(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"MFC1 %s, %s\", rt, fs);\n+}\n+\n+\n+std::string NMD::CVT_S_PL(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"CVT.S.PL %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::TRUNC_L_S(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"TRUNC.L.S %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::TRUNC_L_D(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"TRUNC.L.D %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::DMFC1(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"DMFC1 %s, %s\", rt, fs);\n+}\n+\n+\n+std::string NMD::MTC1(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"MTC1 %s, %s\", rt, fs);\n+}\n+\n+\n+std::string NMD::CVT_S_PU(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"CVT.S.PU %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::TRUNC_W_S(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"TRUNC.W.S %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::TRUNC_W_D(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"TRUNC.W.D %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::DMTC1(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"DMTC1 %s, %s\", rt, fs);\n+}\n+\n+\n+std::string NMD::MFHC1(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"MFHC1 %s, %s\", rt, fs);\n+}\n+\n+\n+std::string NMD::ROUND_L_S(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"ROUND.L.S %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::ROUND_L_D(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"ROUND.L.D %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::MTHC1(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"MTHC1 %s, %s\", rt, fs);\n+}\n+\n+\n+std::string NMD::ROUND_W_S(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"ROUND.W.S %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::ROUND_W_D(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"ROUND.W.D %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::MOV_S(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"MOV.S %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::MOV_D(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"MOV.D %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::ABS_S(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"ABS.S %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::ABS_D(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"ABS.D %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::NEG_S(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"NEG.S %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::NEG_D(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"NEG.D %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::CVT_D_S(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"CVT.D.S %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::CVT_D_W(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"CVT.D.W %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::CVT_D_L(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"CVT.D.L %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::CVT_S_D(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"CVT.S.D %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::CVT_S_W(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"CVT.S.W %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::CVT_S_L(uint64 instruction)\n+{\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string fs = FPR(copy(fs_value));\n+\n+ return img::format(\"CVT.S.L %s, %s\", ft, fs);\n+}\n+\n+\n+std::string NMD::CMP_AF_S(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.AF.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_UN_S(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.UN.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_EQ_S(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.EQ.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_UEQ_S(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.UEQ.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_LT_S(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.LT.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_ULT_S(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.ULT.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_LE_S(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.LE.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_ULE_S(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.ULE.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_SAF_S(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.SAF.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_SUN_S(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.SUN.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_SEQ_S(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.SEQ.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_SUEQ_S(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.SUEQ.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_SLT_S(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.SLT.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_SULT_S(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.SULT.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_SLE_S(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.SLE.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_SULE_S(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.SULE.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_OR_S(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.OR.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_UNE_S(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.UNE.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_NE_S(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.NE.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_SOR_S(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.SOR.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_SUNE_S(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.SUNE.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_SNE_S(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.SNE.S %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_AF_D(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.AF.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_UN_D(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.UN.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_EQ_D(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.EQ.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_UEQ_D(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.UEQ.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_LT_D(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.LT.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_ULT_D(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.ULT.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_LE_D(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.LE.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_ULE_D(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.ULE.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_SAF_D(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.SAF.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_SUN_D(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.SUN.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_SEQ_D(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.SEQ.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_SUEQ_D(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.SUEQ.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_SLT_D(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.SLT.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_SULT_D(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.SULT.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_SLE_D(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.SLE.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_SULE_D(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.SULE.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_OR_D(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.OR.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_UNE_D(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.UNE.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_NE_D(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.NE.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_SOR_D(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.SOR.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_SUNE_D(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.SUNE.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::CMP_SNE_D(uint64 instruction)\n+{\n+ uint64 fd_value = extr_fdil11il0bs5Fmsb4(instruction);\n+ uint64 fs_value = extr_fsil16il0bs5Fmsb4(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string fd = FPR(copy(fd_value));\n+ std::string fs = FPR(copy(fs_value));\n+ std::string ft = FPR(copy(ft_value));\n+\n+ return img::format(\"CMP.SNE.D %s, %s, %s\", fd, fs, ft);\n+}\n+\n+\n+std::string NMD::DLSA(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 u2_value = extr_u2il9il0bs2Fmsb1(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u2 = IMMEDIATE(copy(u2_value));\n+\n+ return img::format(\"DLSA %s, %s, %s, %s\", rd, rs, rt, u2);\n+}\n+\n+\n+std::string NMD::DSLLV(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DSLLV %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::DMUL(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DMUL %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::DSRLV(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DSRLV %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::DMUH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DMUH %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::DSRAV(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DSRAV %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::DMULU(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DMULU %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::DROTRV(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DROTRV %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::DMUHU(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DMUHU %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::DADD(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DADD %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::DDIV(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DDIV %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::DADDU(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DADDU %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::DMOD(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DMOD %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::DSUB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DSUB %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::DDIVU(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DDIVU %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::DSUBU(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DSUBU %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::DMODU(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"DMODU %s, %s, %s\", rd, rs, rt);\n+}\n+\n+\n+std::string NMD::EXTD(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 shift_value = extr_shiftil6il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+ std::string shift = IMMEDIATE(copy(shift_value));\n+\n+ return img::format(\"EXTD %s, %s, %s, %s\", rd, rs, rt, shift);\n+}\n+\n+\n+std::string NMD::EXTD32(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 shift_value = extr_shiftil6il0bs5Fmsb4(instruction);\n+ uint64 rd_value = extr_rdil11il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rd = GPR(copy(rd_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+ std::string shift = IMMEDIATE(copy(shift_value));\n+\n+ return img::format(\"EXTD32 %s, %s, %s, %s\", rd, rs, rt, shift);\n+}\n+\n+\n+std::string NMD::DCLO(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"DCLO %s, %s\", rt, rs);\n+}\n+\n+\n+std::string NMD::DCLZ(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"DCLZ %s, %s\", rt, rs);\n+}\n+\n+\n+std::string NMD::LUI(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il31bs1_il2il21bs10_il12il12bs9Tmsb31(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+\n+ return img::format(\"LUI %s, %%hi(%s)\", rt, s);\n+}\n+\n+\n+std::string NMD::ALUIPC(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il31bs1_il2il21bs10_il12il12bs9Tmsb31(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = ADDRESS(encode_s_from_address(s_value), 4);\n+\n+ return img::format(\"ALUIPC %s, %%pcrel_hi(%s)\", rt, s);\n+}\n+\n+\n+std::string NMD::ADDIUPC_32_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il21bs1_il1il1bs20Tmsb21(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = ADDRESS(encode_s_from_address(s_value), 4);\n+\n+ return img::format(\"ADDIUPC %s, %s\", rt, s);\n+}\n+\n+\n+std::string NMD::LB_GP_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil0il0bs18Fmsb17(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+\n+ return img::format(\"LB %s, %s($%d)\", rt, u, 28);\n+}\n+\n+\n+std::string NMD::SB_GP_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil0il0bs18Fmsb17(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+\n+ return img::format(\"SB %s, %s($%d)\", rt, u, 28);\n+}\n+\n+\n+std::string NMD::LBU_GP_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil0il0bs18Fmsb17(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+\n+ return img::format(\"LBU %s, %s($%d)\", rt, u, 28);\n+}\n+\n+\n+std::string NMD::ADDIU_GP_B_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil0il0bs18Fmsb17(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+\n+ return img::format(\"ADDIU %s, $%d, %s\", rt, 28, u);\n+}\n+\n+\n+std::string NMD::LH_GP_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil1il1bs17Fmsb17(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+\n+ return img::format(\"LH %s, %s($%d)\", rt, u, 28);\n+}\n+\n+\n+std::string NMD::LHU_GP_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil1il1bs17Fmsb17(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+\n+ return img::format(\"LHU %s, %s($%d)\", rt, u, 28);\n+}\n+\n+\n+std::string NMD::SH_GP_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil1il1bs17Fmsb17(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+\n+ return img::format(\"SH %s, %s($%d)\", rt, u, 28);\n+}\n+\n+\n+std::string NMD::LWC1_GP_(uint64 instruction)\n+{\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil2il2bs16Fmsb17(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+\n+ return img::format(\"LWC1 %s, %s($%d)\", ft, u, 28);\n+}\n+\n+\n+std::string NMD::SWC1_GP_(uint64 instruction)\n+{\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil2il2bs16Fmsb17(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+\n+ return img::format(\"SWC1 %s, %s($%d)\", ft, u, 28);\n+}\n+\n+\n+std::string NMD::LDC1_GP_(uint64 instruction)\n+{\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil2il2bs16Fmsb17(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+\n+ return img::format(\"LDC1 %s, %s($%d)\", ft, u, 28);\n+}\n+\n+\n+std::string NMD::SDC1_GP_(uint64 instruction)\n+{\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil2il2bs16Fmsb17(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+\n+ return img::format(\"SDC1 %s, %s($%d)\", ft, u, 28);\n+}\n+\n+\n+std::string NMD::LWU_GP_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil2il2bs16Fmsb17(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+\n+ return img::format(\"LWU %s, %s($%d)\", rt, u, 28);\n+}\n+\n+\n+std::string NMD::LB_U12_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil0il0bs12Fmsb11(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"LB %s, %s(%s)\", rt, u, rs);\n+}\n+\n+\n+std::string NMD::SB_U12_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil0il0bs12Fmsb11(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SB %s, %s(%s)\", rt, u, rs);\n+}\n+\n+\n+std::string NMD::LBU_U12_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil0il0bs12Fmsb11(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"LBU %s, %s(%s)\", rt, u, rs);\n+}\n+\n+\n+std::string NMD::PREF_U12_(uint64 instruction)\n+{\n+ uint64 hint_value = extr_hintil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil0il0bs12Fmsb11(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string hint = IMMEDIATE(copy(hint_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"PREF %s, %s(%s)\", hint, u, rs);\n+}\n+\n+\n+std::string NMD::LH_U12_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil0il0bs12Fmsb11(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"LH %s, %s(%s)\", rt, u, rs);\n+}\n+\n+\n+std::string NMD::SH_U12_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil0il0bs12Fmsb11(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SH %s, %s(%s)\", rt, u, rs);\n+}\n+\n+\n+std::string NMD::LHU_U12_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil0il0bs12Fmsb11(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"LHU %s, %s(%s)\", rt, u, rs);\n+}\n+\n+\n+std::string NMD::LWU_U12_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil0il0bs12Fmsb11(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"LWU %s, %s(%s)\", rt, u, rs);\n+}\n+\n+\n+std::string NMD::LW_U12_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil0il0bs12Fmsb11(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"LW %s, %s(%s)\", rt, u, rs);\n+}\n+\n+\n+std::string NMD::SW_U12_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil0il0bs12Fmsb11(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SW %s, %s(%s)\", rt, u, rs);\n+}\n+\n+\n+std::string NMD::LWC1_U12_(uint64 instruction)\n+{\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil0il0bs12Fmsb11(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"LWC1 %s, %s(%s)\", ft, u, rs);\n+}\n+\n+\n+std::string NMD::SWC1_U12_(uint64 instruction)\n+{\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil0il0bs12Fmsb11(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SWC1 %s, %s(%s)\", ft, u, rs);\n+}\n+\n+\n+std::string NMD::LD_U12_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil0il0bs12Fmsb11(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"LD %s, %s(%s)\", rt, u, rs);\n+}\n+\n+\n+std::string NMD::SD_U12_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil0il0bs12Fmsb11(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SD %s, %s(%s)\", rt, u, rs);\n+}\n+\n+\n+std::string NMD::LDC1_U12_(uint64 instruction)\n+{\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil0il0bs12Fmsb11(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"LDC1 %s, %s(%s)\", ft, u, rs);\n+}\n+\n+\n+std::string NMD::SDC1_U12_(uint64 instruction)\n+{\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil0il0bs12Fmsb11(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SDC1 %s, %s(%s)\", ft, u, rs);\n+}\n+\n+\n+std::string NMD::LB_S9_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"LB %s, %s(%s)\", rt, s, rs);\n+}\n+\n+\n+std::string NMD::SB_S9_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SB %s, %s(%s)\", rt, s, rs);\n+}\n+\n+\n+std::string NMD::LBU_S9_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"LBU %s, %s(%s)\", rt, s, rs);\n+}\n+\n+\n+std::string NMD::SYNCI(uint64 instruction)\n+{\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SYNCI %s(%s)\", s, rs);\n+}\n+\n+\n+std::string NMD::PREF_S9_(uint64 instruction)\n+{\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 hint_value = extr_hintil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string hint = IMMEDIATE(copy(hint_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"PREF %s, %s(%s)\", hint, s, rs);\n+}\n+\n+\n+std::string NMD::LH_S9_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"LH %s, %s(%s)\", rt, s, rs);\n+}\n+\n+\n+std::string NMD::SH_S9_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SH %s, %s(%s)\", rt, s, rs);\n+}\n+\n+\n+std::string NMD::LHU_S9_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"LHU %s, %s(%s)\", rt, s, rs);\n+}\n+\n+\n+std::string NMD::LWU_S9_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"LWU %s, %s(%s)\", rt, s, rs);\n+}\n+\n+\n+std::string NMD::LW_S9_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"LW %s, %s(%s)\", rt, s, rs);\n+}\n+\n+\n+std::string NMD::SW_S9_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SW %s, %s(%s)\", rt, s, rs);\n+}\n+\n+\n+std::string NMD::LWC1_S9_(uint64 instruction)\n+{\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"LWC1 %s, %s(%s)\", ft, s, rs);\n+}\n+\n+\n+std::string NMD::SWC1_S9_(uint64 instruction)\n+{\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SWC1 %s, %s(%s)\", ft, s, rs);\n+}\n+\n+\n+std::string NMD::LD_S9_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"LD %s, %s(%s)\", rt, s, rs);\n+}\n+\n+\n+std::string NMD::SD_S9_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SD %s, %s(%s)\", rt, s, rs);\n+}\n+\n+\n+std::string NMD::LDC1_S9_(uint64 instruction)\n+{\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"LDC1 %s, %s(%s)\", ft, s, rs);\n+}\n+\n+\n+std::string NMD::SDC1_S9_(uint64 instruction)\n+{\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SDC1 %s, %s(%s)\", ft, s, rs);\n+}\n+\n+\n+std::string NMD::ASET(uint64 instruction)\n+{\n+ uint64 bit_value = extr_bitil21il0bs3Fmsb2(instruction);\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string bit = IMMEDIATE(copy(bit_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"ASET %s, %s(%s)\", bit, s, rs);\n+}\n+\n+\n+std::string NMD::ACLR(uint64 instruction)\n+{\n+ uint64 bit_value = extr_bitil21il0bs3Fmsb2(instruction);\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string bit = IMMEDIATE(copy(bit_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"ACLR %s, %s(%s)\", bit, s, rs);\n+}\n+\n+\n+std::string NMD::UALH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"UALH %s, %s(%s)\", rt, s, rs);\n+}\n+\n+\n+std::string NMD::UASH(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"UASH %s, %s(%s)\", rt, s, rs);\n+}\n+\n+\n+std::string NMD::CACHE(uint64 instruction)\n+{\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 op_value = extr_opil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string op = IMMEDIATE(copy(op_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"CACHE %s, %s(%s)\", op, s, rs);\n+}\n+\n+\n+std::string NMD::LWC2(uint64 instruction)\n+{\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 ct_value = extr_ctil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ct = CPR(copy(ct_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"LWC2 %s, %s(%s)\", ct, s, rs);\n+}\n+\n+\n+std::string NMD::SWC2(uint64 instruction)\n+{\n+ uint64 cs_value = extr_csil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string cs = CPR(copy(cs_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SWC2 %s, %s(%s)\", cs, s, rs);\n+}\n+\n+\n+std::string NMD::LL(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil2il2bs6_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"LL %s, %s(%s)\", rt, s, rs);\n+}\n+\n+\n+std::string NMD::LLWP(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ru_value = extr_ruil3il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string ru = GPR(copy(ru_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"LLWP %s, %s, (%s)\", rt, ru, rs);\n+}\n+\n+\n+std::string NMD::SC(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil2il2bs6_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SC %s, %s(%s)\", rt, s, rs);\n+}\n+\n+\n+std::string NMD::SCWP(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ru_value = extr_ruil3il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string ru = GPR(copy(ru_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SCWP %s, %s, (%s)\", rt, ru, rs);\n+}\n+\n+\n+std::string NMD::LDC2(uint64 instruction)\n+{\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 ct_value = extr_ctil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string ct = CPR(copy(ct_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"LDC2 %s, %s(%s)\", ct, s, rs);\n+}\n+\n+\n+std::string NMD::SDC2(uint64 instruction)\n+{\n+ uint64 cs_value = extr_csil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string cs = CPR(copy(cs_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SDC2 %s, %s(%s)\", cs, s, rs);\n+}\n+\n+\n+std::string NMD::LLD(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil3il3bs5_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"LLD %s, %s(%s)\", rt, s, rs);\n+}\n+\n+\n+std::string NMD::LLDP(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ru_value = extr_ruil3il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string ru = GPR(copy(ru_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"LLDP %s, %s, (%s)\", rt, ru, rs);\n+}\n+\n+\n+std::string NMD::SCD(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil3il3bs5_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SCD %s, %s(%s)\", rt, s, rs);\n+}\n+\n+\n+std::string NMD::SCDP(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ru_value = extr_ruil3il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string ru = GPR(copy(ru_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SCDP %s, %s, (%s)\", rt, ru, rs);\n+}\n+\n+\n+std::string NMD::LBE(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"LBE %s, %s(%s)\", rt, s, rs);\n+}\n+\n+\n+std::string NMD::SBE(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SBE %s, %s(%s)\", rt, s, rs);\n+}\n+\n+\n+std::string NMD::LBUE(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"LBUE %s, %s(%s)\", rt, s, rs);\n+}\n+\n+\n+std::string NMD::SYNCIE(uint64 instruction)\n+{\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SYNCIE %s(%s)\", s, rs);\n+}\n+\n+\n+std::string NMD::PREFE(uint64 instruction)\n+{\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 hint_value = extr_hintil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string hint = IMMEDIATE(copy(hint_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"PREFE %s, %s(%s)\", hint, s, rs);\n+}\n+\n+\n+std::string NMD::LHE(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"LHE %s, %s(%s)\", rt, s, rs);\n+}\n+\n+\n+std::string NMD::SHE(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SHE %s, %s(%s)\", rt, s, rs);\n+}\n+\n+\n+std::string NMD::LHUE(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"LHUE %s, %s(%s)\", rt, s, rs);\n+}\n+\n+\n+std::string NMD::CACHEE(uint64 instruction)\n+{\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 op_value = extr_opil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string op = IMMEDIATE(copy(op_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"CACHEE %s, %s(%s)\", op, s, rs);\n+}\n+\n+\n+std::string NMD::LWE(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"LWE %s, %s(%s)\", rt, s, rs);\n+}\n+\n+\n+std::string NMD::SWE(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SWE %s, %s(%s)\", rt, s, rs);\n+}\n+\n+\n+std::string NMD::LLE(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil2il2bs6_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"LLE %s, %s(%s)\", rt, s, rs);\n+}\n+\n+\n+std::string NMD::LLWPE(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ru_value = extr_ruil3il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string ru = GPR(copy(ru_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"LLWPE %s, %s, (%s)\", rt, ru, rs);\n+}\n+\n+\n+std::string NMD::SCE(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil2il2bs6_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SCE %s, %s(%s)\", rt, s, rs);\n+}\n+\n+\n+std::string NMD::SCWPE(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 ru_value = extr_ruil3il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string ru = GPR(copy(ru_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"SCWPE %s, %s, (%s)\", rt, ru, rs);\n+}\n+\n+\n+std::string NMD::LWM(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 count3_value = extr_count3il12il0bs3Fmsb2(instruction);\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string count3 = IMMEDIATE(encode_count3_from_count(count3_value));\n+\n+ return img::format(\"LWM %s, %s(%s), %s\", rt, s, rs, count3);\n+}\n+\n+\n+std::string NMD::SWM(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 count3_value = extr_count3il12il0bs3Fmsb2(instruction);\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string count3 = IMMEDIATE(encode_count3_from_count(count3_value));\n+\n+ return img::format(\"SWM %s, %s(%s), %s\", rt, s, rs, count3);\n+}\n+\n+\n+std::string NMD::UALWM(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 count3_value = extr_count3il12il0bs3Fmsb2(instruction);\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string count3 = IMMEDIATE(encode_count3_from_count(count3_value));\n+\n+ return img::format(\"UALWM %s, %s(%s), %s\", rt, s, rs, count3);\n+}\n+\n+\n+std::string NMD::UASWM(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 count3_value = extr_count3il12il0bs3Fmsb2(instruction);\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string count3 = IMMEDIATE(encode_count3_from_count(count3_value));\n+\n+ return img::format(\"UASWM %s, %s(%s), %s\", rt, s, rs, count3);\n+}\n+\n+\n+std::string NMD::LDM(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 count3_value = extr_count3il12il0bs3Fmsb2(instruction);\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string count3 = IMMEDIATE(encode_count3_from_count(count3_value));\n+\n+ return img::format(\"LDM %s, %s(%s), %s\", rt, s, rs, count3);\n+}\n+\n+\n+std::string NMD::SDM(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 count3_value = extr_count3il12il0bs3Fmsb2(instruction);\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string count3 = IMMEDIATE(encode_count3_from_count(count3_value));\n+\n+ return img::format(\"SDM %s, %s(%s), %s\", rt, s, rs, count3);\n+}\n+\n+\n+std::string NMD::UALDM(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 count3_value = extr_count3il12il0bs3Fmsb2(instruction);\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string count3 = IMMEDIATE(encode_count3_from_count(count3_value));\n+\n+ return img::format(\"UALDM %s, %s(%s), %s\", rt, s, rs, count3);\n+}\n+\n+\n+std::string NMD::UASDM(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 count3_value = extr_count3il12il0bs3Fmsb2(instruction);\n+ int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+ std::string rs = GPR(copy(rs_value));\n+ std::string count3 = IMMEDIATE(encode_count3_from_count(count3_value));\n+\n+ return img::format(\"UASDM %s, %s(%s), %s\", rt, s, rs, count3);\n+}\n+\n+\n+std::string NMD::MOVE_BALC(uint64 instruction)\n+{\n+ uint64 rd1_value = extr_rd1il24il0bs1Fmsb0(instruction);\n+ int64 s_value = extr_sil0il21bs1_il1il1bs20Tmsb21(instruction);\n+ uint64 rtz4_value = extr_rtz4il21il0bs3_il25il3bs1Fmsb3(instruction);\n+\n+ std::string rd1 = GPR(encode_rd1_from_rd(rd1_value));\n+ std::string rtz4 = GPR(encode_gpr4_zero(rtz4_value));\n+ std::string s = ADDRESS(encode_s_from_address(s_value), 4);\n+\n+ return img::format(\"MOVE.BALC %s, %s, %s\", rd1, rtz4, s);\n+}\n+\n+\n+std::string NMD::BC_32_(uint64 instruction)\n+{\n+ int64 s_value = extr_sil0il25bs1_il1il1bs24Tmsb25(instruction);\n+\n+ std::string s = ADDRESS(encode_s_from_address(s_value), 4);\n+\n+ return img::format(\"BC %s\", s);\n+}\n+\n+\n+std::string NMD::BALC_32_(uint64 instruction)\n+{\n+ int64 s_value = extr_sil0il25bs1_il1il1bs24Tmsb25(instruction);\n+\n+ std::string s = ADDRESS(encode_s_from_address(s_value), 4);\n+\n+ return img::format(\"BALC %s\", s);\n+}\n+\n+\n+std::string NMD::JALRC_32_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"JALRC %s, %s\", rt, rs);\n+}\n+\n+\n+std::string NMD::JALRC_HB(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"JALRC.HB %s, %s\", rt, rs);\n+}\n+\n+\n+std::string NMD::BRSC(uint64 instruction)\n+{\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"BRSC %s\", rs);\n+}\n+\n+\n+std::string NMD::BALRSC(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"BALRSC %s, %s\", rt, rs);\n+}\n+\n+\n+std::string NMD::BEQC_32_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il14bs1_il1il1bs13Tmsb14(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = ADDRESS(encode_s_from_address(s_value), 4);\n+\n+ return img::format(\"BEQC %s, %s, %s\", rs, rt, s);\n+}\n+\n+\n+std::string NMD::BC1EQZC(uint64 instruction)\n+{\n+ int64 s_value = extr_sil0il14bs1_il1il1bs13Tmsb14(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string s = ADDRESS(encode_s_from_address(s_value), 4);\n+\n+ return img::format(\"BC1EQZC %s, %s\", ft, s);\n+}\n+\n+\n+std::string NMD::BC1NEZC(uint64 instruction)\n+{\n+ int64 s_value = extr_sil0il14bs1_il1il1bs13Tmsb14(instruction);\n+ uint64 ft_value = extr_ftil21il0bs5Fmsb4(instruction);\n+\n+ std::string ft = FPR(copy(ft_value));\n+ std::string s = ADDRESS(encode_s_from_address(s_value), 4);\n+\n+ return img::format(\"BC1NEZC %s, %s\", ft, s);\n+}\n+\n+\n+std::string NMD::BC2EQZC(uint64 instruction)\n+{\n+ int64 s_value = extr_sil0il14bs1_il1il1bs13Tmsb14(instruction);\n+ uint64 ct_value = extr_ctil21il0bs5Fmsb4(instruction);\n+\n+ std::string ct = CPR(copy(ct_value));\n+ std::string s = ADDRESS(encode_s_from_address(s_value), 4);\n+\n+ return img::format(\"BC2EQZC %s, %s\", ct, s);\n+}\n+\n+\n+std::string NMD::BC2NEZC(uint64 instruction)\n+{\n+ int64 s_value = extr_sil0il14bs1_il1il1bs13Tmsb14(instruction);\n+ uint64 ct_value = extr_ctil21il0bs5Fmsb4(instruction);\n+\n+ std::string ct = CPR(copy(ct_value));\n+ std::string s = ADDRESS(encode_s_from_address(s_value), 4);\n+\n+ return img::format(\"BC2NEZC %s, %s\", ct, s);\n+}\n+\n+\n+std::string NMD::BPOSGE32C(uint64 instruction)\n+{\n+ int64 s_value = extr_sil0il14bs1_il1il1bs13Tmsb14(instruction);\n+\n+ std::string s = ADDRESS(encode_s_from_address(s_value), 4);\n+\n+ return img::format(\"BPOSGE32C %s\", s);\n+}\n+\n+\n+std::string NMD::BGEC(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il14bs1_il1il1bs13Tmsb14(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = ADDRESS(encode_s_from_address(s_value), 4);\n+\n+ return img::format(\"BGEC %s, %s, %s\", rs, rt, s);\n+}\n+\n+\n+std::string NMD::BGEUC(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il14bs1_il1il1bs13Tmsb14(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = ADDRESS(encode_s_from_address(s_value), 4);\n+\n+ return img::format(\"BGEUC %s, %s, %s\", rs, rt, s);\n+}\n+\n+\n+std::string NMD::BNEC_32_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il14bs1_il1il1bs13Tmsb14(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = ADDRESS(encode_s_from_address(s_value), 4);\n+\n+ return img::format(\"BNEC %s, %s, %s\", rs, rt, s);\n+}\n+\n+\n+std::string NMD::BLTC(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il14bs1_il1il1bs13Tmsb14(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = ADDRESS(encode_s_from_address(s_value), 4);\n+\n+ return img::format(\"BLTC %s, %s, %s\", rs, rt, s);\n+}\n+\n+\n+std::string NMD::BLTUC(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il14bs1_il1il1bs13Tmsb14(instruction);\n+ uint64 rs_value = extr_rsil16il0bs5Fmsb4(instruction);\n+\n+ std::string rs = GPR(copy(rs_value));\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = ADDRESS(encode_s_from_address(s_value), 4);\n+\n+ return img::format(\"BLTUC %s, %s, %s\", rs, rt, s);\n+}\n+\n+\n+std::string NMD::BEQIC(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il11bs1_il1il1bs10Tmsb11(instruction);\n+ uint64 u_value = extr_uil11il0bs7Fmsb6(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string s = ADDRESS(encode_s_from_address(s_value), 4);\n+\n+ return img::format(\"BEQIC %s, %s, %s\", rt, u, s);\n+}\n+\n+\n+std::string NMD::BBEQZC(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 bit_value = extr_bitil11il0bs6Fmsb5(instruction);\n+ int64 s_value = extr_sil0il11bs1_il1il1bs10Tmsb11(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string bit = IMMEDIATE(copy(bit_value));\n+ std::string s = ADDRESS(encode_s_from_address(s_value), 4);\n+\n+ return img::format(\"BBEQZC %s, %s, %s\", rt, bit, s);\n+}\n+\n+\n+std::string NMD::BGEIC(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il11bs1_il1il1bs10Tmsb11(instruction);\n+ uint64 u_value = extr_uil11il0bs7Fmsb6(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string s = ADDRESS(encode_s_from_address(s_value), 4);\n+\n+ return img::format(\"BGEIC %s, %s, %s\", rt, u, s);\n+}\n+\n+\n+std::string NMD::BGEIUC(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il11bs1_il1il1bs10Tmsb11(instruction);\n+ uint64 u_value = extr_uil11il0bs7Fmsb6(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string s = ADDRESS(encode_s_from_address(s_value), 4);\n+\n+ return img::format(\"BGEIUC %s, %s, %s\", rt, u, s);\n+}\n+\n+\n+std::string NMD::BNEIC(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il11bs1_il1il1bs10Tmsb11(instruction);\n+ uint64 u_value = extr_uil11il0bs7Fmsb6(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string s = ADDRESS(encode_s_from_address(s_value), 4);\n+\n+ return img::format(\"BNEIC %s, %s, %s\", rt, u, s);\n+}\n+\n+\n+std::string NMD::BBNEZC(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ uint64 bit_value = extr_bitil11il0bs6Fmsb5(instruction);\n+ int64 s_value = extr_sil0il11bs1_il1il1bs10Tmsb11(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string bit = IMMEDIATE(copy(bit_value));\n+ std::string s = ADDRESS(encode_s_from_address(s_value), 4);\n+\n+ return img::format(\"BBNEZC %s, %s, %s\", rt, bit, s);\n+}\n+\n+\n+std::string NMD::BLTIC(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il11bs1_il1il1bs10Tmsb11(instruction);\n+ uint64 u_value = extr_uil11il0bs7Fmsb6(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string s = ADDRESS(encode_s_from_address(s_value), 4);\n+\n+ return img::format(\"BLTIC %s, %s, %s\", rt, u, s);\n+}\n+\n+\n+std::string NMD::BLTIUC(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil21il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il11bs1_il1il1bs10Tmsb11(instruction);\n+ uint64 u_value = extr_uil11il0bs7Fmsb6(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string s = ADDRESS(encode_s_from_address(s_value), 4);\n+\n+ return img::format(\"BLTIUC %s, %s, %s\", rt, u, s);\n+}\n+\n+\n+std::string NMD::SYSCALL_16_(uint64 instruction)\n+{\n+ uint64 code_value = extr_codeil0il0bs2Fmsb1(instruction);\n+\n+ std::string code = IMMEDIATE(copy(code_value));\n+\n+ return img::format(\"SYSCALL %s\", code);\n+}\n+\n+\n+std::string NMD::HYPCALL_16_(uint64 instruction)\n+{\n+ uint64 code_value = extr_codeil0il0bs2Fmsb1(instruction);\n+\n+ std::string code = IMMEDIATE(copy(code_value));\n+\n+ return img::format(\"HYPCALL %s\", code);\n+}\n+\n+\n+std::string NMD::BREAK_16_(uint64 instruction)\n+{\n+ uint64 code_value = extr_codeil0il0bs3Fmsb2(instruction);\n+\n+ std::string code = IMMEDIATE(copy(code_value));\n+\n+ return img::format(\"BREAK %s\", code);\n+}\n+\n+\n+std::string NMD::SDBBP_16_(uint64 instruction)\n+{\n+ uint64 code_value = extr_codeil0il0bs3Fmsb2(instruction);\n+\n+ std::string code = IMMEDIATE(copy(code_value));\n+\n+ return img::format(\"SDBBP %s\", code);\n+}\n+\n+\n+std::string NMD::MOVE(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil5il0bs5Fmsb4(instruction);\n+ uint64 rs_value = extr_rsil0il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string rs = GPR(copy(rs_value));\n+\n+ return img::format(\"MOVE %s, %s\", rt, rs);\n+}\n+\n+\n+std::string NMD::SLL_16_(uint64 instruction)\n+{\n+ uint64 shift3_value = extr_shift3il0il0bs3Fmsb2(instruction);\n+ uint64 rt3_value = extr_rt3il7il0bs3Fmsb2(instruction);\n+ uint64 rs3_value = extr_rs3il4il0bs3Fmsb2(instruction);\n+\n+ std::string rt3 = GPR(encode_gpr3(rt3_value));\n+ std::string rs3 = GPR(encode_gpr3(rs3_value));\n+ std::string shift3 = IMMEDIATE(encode_shift3_from_shift(shift3_value));\n+\n+ return img::format(\"SLL %s, %s, %s\", rt3, rs3, shift3);\n+}\n+\n+\n+std::string NMD::SRL_16_(uint64 instruction)\n+{\n+ uint64 shift3_value = extr_shift3il0il0bs3Fmsb2(instruction);\n+ uint64 rt3_value = extr_rt3il7il0bs3Fmsb2(instruction);\n+ uint64 rs3_value = extr_rs3il4il0bs3Fmsb2(instruction);\n+\n+ std::string rt3 = GPR(encode_gpr3(rt3_value));\n+ std::string rs3 = GPR(encode_gpr3(rs3_value));\n+ std::string shift3 = IMMEDIATE(encode_shift3_from_shift(shift3_value));\n+\n+ return img::format(\"SRL %s, %s, %s\", rt3, rs3, shift3);\n+}\n+\n+\n+std::string NMD::NOT_16_(uint64 instruction)\n+{\n+ uint64 rt3_value = extr_rt3il7il0bs3Fmsb2(instruction);\n+ uint64 rs3_value = extr_rs3il4il0bs3Fmsb2(instruction);\n+\n+ std::string rt3 = GPR(encode_gpr3(rt3_value));\n+ std::string rs3 = GPR(encode_gpr3(rs3_value));\n+\n+ return img::format(\"NOT %s, %s\", rt3, rs3);\n+}\n+\n+\n+std::string NMD::XOR_16_(uint64 instruction)\n+{\n+ uint64 rt3_value = extr_rt3il7il0bs3Fmsb2(instruction);\n+ uint64 rs3_value = extr_rs3il4il0bs3Fmsb2(instruction);\n+\n+ std::string rs3 = GPR(encode_gpr3(rs3_value));\n+ std::string rt3 = GPR(encode_gpr3(rt3_value));\n+\n+ return img::format(\"XOR %s, %s\", rs3, rt3);\n+}\n+\n+\n+std::string NMD::AND_16_(uint64 instruction)\n+{\n+ uint64 rt3_value = extr_rt3il7il0bs3Fmsb2(instruction);\n+ uint64 rs3_value = extr_rs3il4il0bs3Fmsb2(instruction);\n+\n+ std::string rs3 = GPR(encode_gpr3(rs3_value));\n+ std::string rt3 = GPR(encode_gpr3(rt3_value));\n+\n+ return img::format(\"AND %s, %s\", rs3, rt3);\n+}\n+\n+\n+std::string NMD::OR_16_(uint64 instruction)\n+{\n+ uint64 rt3_value = extr_rt3il7il0bs3Fmsb2(instruction);\n+ uint64 rs3_value = extr_rs3il4il0bs3Fmsb2(instruction);\n+\n+ std::string rs3 = GPR(encode_gpr3(rs3_value));\n+ std::string rt3 = GPR(encode_gpr3(rt3_value));\n+\n+ return img::format(\"OR %s, %s\", rs3, rt3);\n+}\n+\n+\n+std::string NMD::LWXS_16_(uint64 instruction)\n+{\n+ uint64 rd3_value = extr_rd3il1il0bs3Fmsb2(instruction);\n+ uint64 rt3_value = extr_rt3il7il0bs3Fmsb2(instruction);\n+ uint64 rs3_value = extr_rs3il4il0bs3Fmsb2(instruction);\n+\n+ std::string rd3 = GPR(encode_gpr3(rd3_value));\n+ std::string rs3 = GPR(encode_gpr3(rs3_value));\n+ std::string rt3 = IMMEDIATE(encode_gpr3(rt3_value));\n+\n+ return img::format(\"LWXS %s, %s(%s)\", rd3, rs3, rt3);\n+}\n+\n+\n+std::string NMD::ADDIU_R1_SP_(uint64 instruction)\n+{\n+ uint64 u_value = extr_uil0il2bs6Fmsb7(instruction);\n+ uint64 rt3_value = extr_rt3il7il0bs3Fmsb2(instruction);\n+\n+ std::string rt3 = GPR(encode_gpr3(rt3_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+\n+ return img::format(\"ADDIU %s, $%d, %s\", rt3, 29, u);\n+}\n+\n+\n+std::string NMD::ADDIU_R2_(uint64 instruction)\n+{\n+ uint64 u_value = extr_uil0il2bs3Fmsb4(instruction);\n+ uint64 rt3_value = extr_rt3il7il0bs3Fmsb2(instruction);\n+ uint64 rs3_value = extr_rs3il4il0bs3Fmsb2(instruction);\n+\n+ std::string rt3 = GPR(encode_gpr3(rt3_value));\n+ std::string rs3 = GPR(encode_gpr3(rs3_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+\n+ return img::format(\"ADDIU %s, %s, %s\", rt3, rs3, u);\n+}\n+\n+\n+std::string NMD::NOP_16_(uint64 instruction)\n+{\n+ (void)instruction;\n+\n+ return \"NOP \";\n+}\n+\n+\n+std::string NMD::ADDIU_RS5_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil5il0bs5Fmsb4(instruction);\n+ int64 s_value = extr_sil0il0bs3_il4il3bs1Tmsb3(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string s = IMMEDIATE(copy(s_value));\n+\n+ return img::format(\"ADDIU %s, %s\", rt, s);\n+}\n+\n+\n+std::string NMD::ADDU_16_(uint64 instruction)\n+{\n+ uint64 rd3_value = extr_rd3il1il0bs3Fmsb2(instruction);\n+ uint64 rt3_value = extr_rt3il7il0bs3Fmsb2(instruction);\n+ uint64 rs3_value = extr_rs3il4il0bs3Fmsb2(instruction);\n+\n+ std::string rd3 = GPR(encode_gpr3(rd3_value));\n+ std::string rs3 = GPR(encode_gpr3(rs3_value));\n+ std::string rt3 = GPR(encode_gpr3(rt3_value));\n+\n+ return img::format(\"ADDU %s, %s, %s\", rd3, rs3, rt3);\n+}\n+\n+\n+std::string NMD::SUBU_16_(uint64 instruction)\n+{\n+ uint64 rd3_value = extr_rd3il1il0bs3Fmsb2(instruction);\n+ uint64 rt3_value = extr_rt3il7il0bs3Fmsb2(instruction);\n+ uint64 rs3_value = extr_rs3il4il0bs3Fmsb2(instruction);\n+\n+ std::string rd3 = GPR(encode_gpr3(rd3_value));\n+ std::string rs3 = GPR(encode_gpr3(rs3_value));\n+ std::string rt3 = GPR(encode_gpr3(rt3_value));\n+\n+ return img::format(\"SUBU %s, %s, %s\", rd3, rs3, rt3);\n+}\n+\n+\n+std::string NMD::LI_16_(uint64 instruction)\n+{\n+ uint64 eu_value = extr_euil0il0bs7Fmsb6(instruction);\n+ uint64 rt3_value = extr_rt3il7il0bs3Fmsb2(instruction);\n+\n+ std::string rt3 = GPR(encode_gpr3(rt3_value));\n+ std::string eu = IMMEDIATE(encode_eu_from_s_li16(eu_value));\n+\n+ return img::format(\"LI %s, %s\", rt3, eu);\n+}\n+\n+\n+std::string NMD::ANDI_16_(uint64 instruction)\n+{\n+ uint64 eu_value = extr_euil0il0bs4Fmsb3(instruction);\n+ uint64 rt3_value = extr_rt3il7il0bs3Fmsb2(instruction);\n+ uint64 rs3_value = extr_rs3il4il0bs3Fmsb2(instruction);\n+\n+ std::string rt3 = GPR(encode_gpr3(rt3_value));\n+ std::string rs3 = GPR(encode_gpr3(rs3_value));\n+ std::string eu = IMMEDIATE(encode_eu_from_u_andi16(eu_value));\n+\n+ return img::format(\"ANDI %s, %s, %s\", rt3, rs3, eu);\n+}\n+\n+\n+std::string NMD::LW_16_(uint64 instruction)\n+{\n+ uint64 u_value = extr_uil0il2bs4Fmsb5(instruction);\n+ uint64 rt3_value = extr_rt3il7il0bs3Fmsb2(instruction);\n+ uint64 rs3_value = extr_rs3il4il0bs3Fmsb2(instruction);\n+\n+ std::string rt3 = GPR(encode_gpr3(rt3_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string rs3 = GPR(encode_gpr3(rs3_value));\n+\n+ return img::format(\"LW %s, %s(%s)\", rt3, u, rs3);\n+}\n+\n+\n+std::string NMD::LW_SP_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil5il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil0il2bs5Fmsb6(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+\n+ return img::format(\"LW %s, %s($%d)\", rt, u, 29);\n+}\n+\n+\n+std::string NMD::LW_GP16_(uint64 instruction)\n+{\n+ uint64 u_value = extr_uil0il2bs7Fmsb8(instruction);\n+ uint64 rt3_value = extr_rt3il7il0bs3Fmsb2(instruction);\n+\n+ std::string rt3 = GPR(encode_gpr3(rt3_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+\n+ return img::format(\"LW %s, %s($%d)\", rt3, u, 28);\n+}\n+\n+\n+std::string NMD::LW_4X4_(uint64 instruction)\n+{\n+ uint64 rs4_value = extr_rs4il0il0bs3_il4il3bs1Fmsb3(instruction);\n+ uint64 rt4_value = extr_rt4il5il0bs3_il9il3bs1Fmsb3(instruction);\n+ uint64 u_value = extr_uil3il3bs1_il8il2bs1Fmsb3(instruction);\n+\n+ std::string rt4 = GPR(encode_gpr4(rt4_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string rs4 = GPR(encode_gpr4(rs4_value));\n+\n+ return img::format(\"LW %s, %s(%s)\", rt4, u, rs4);\n+}\n+\n+\n+std::string NMD::SW_16_(uint64 instruction)\n+{\n+ uint64 rtz3_value = extr_rtz3il7il0bs3Fmsb2(instruction);\n+ uint64 u_value = extr_uil0il2bs4Fmsb5(instruction);\n+ uint64 rs3_value = extr_rs3il4il0bs3Fmsb2(instruction);\n+\n+ std::string rtz3 = GPR(encode_gpr3_store(rtz3_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string rs3 = GPR(encode_gpr3(rs3_value));\n+\n+ return img::format(\"SW %s, %s(%s)\", rtz3, u, rs3);\n+}\n+\n+\n+std::string NMD::SW_SP_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil5il0bs5Fmsb4(instruction);\n+ uint64 u_value = extr_uil0il2bs5Fmsb6(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+\n+ return img::format(\"SW %s, %s($%d)\", rt, u, 29);\n+}\n+\n+\n+std::string NMD::SW_GP16_(uint64 instruction)\n+{\n+ uint64 rtz3_value = extr_rtz3il7il0bs3Fmsb2(instruction);\n+ uint64 u_value = extr_uil0il2bs7Fmsb8(instruction);\n+\n+ std::string rtz3 = GPR(encode_gpr3_store(rtz3_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+\n+ return img::format(\"SW %s, %s($%d)\", rtz3, u, 28);\n+}\n+\n+\n+std::string NMD::SW_4X4_(uint64 instruction)\n+{\n+ uint64 rs4_value = extr_rs4il0il0bs3_il4il3bs1Fmsb3(instruction);\n+ uint64 rtz4_value = extr_rtz4il5il0bs3_il9il3bs1Fmsb3(instruction);\n+ uint64 u_value = extr_uil3il3bs1_il8il2bs1Fmsb3(instruction);\n+\n+ std::string rtz4 = GPR(encode_gpr4_zero(rtz4_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string rs4 = GPR(encode_gpr4(rs4_value));\n+\n+ return img::format(\"SW %s, %s(%s)\", rtz4, u, rs4);\n+}\n+\n+\n+std::string NMD::BC_16_(uint64 instruction)\n+{\n+ int64 s_value = extr_sil0il10bs1_il1il1bs9Tmsb10(instruction);\n+\n+ std::string s = ADDRESS(encode_s_from_address(s_value), 2);\n+\n+ return img::format(\"BC %s\", s);\n+}\n+\n+\n+std::string NMD::BALC_16_(uint64 instruction)\n+{\n+ int64 s_value = extr_sil0il10bs1_il1il1bs9Tmsb10(instruction);\n+\n+ std::string s = ADDRESS(encode_s_from_address(s_value), 2);\n+\n+ return img::format(\"BALC %s\", s);\n+}\n+\n+\n+std::string NMD::BEQZC_16_(uint64 instruction)\n+{\n+ int64 s_value = extr_sil0il7bs1_il1il1bs6Tmsb7(instruction);\n+ uint64 rt3_value = extr_rt3il7il0bs3Fmsb2(instruction);\n+\n+ std::string rt3 = GPR(encode_gpr3(rt3_value));\n+ std::string s = ADDRESS(encode_s_from_address(s_value), 2);\n+\n+ return img::format(\"BEQZC %s, %s\", rt3, s);\n+}\n+\n+\n+std::string NMD::BNEZC_16_(uint64 instruction)\n+{\n+ int64 s_value = extr_sil0il7bs1_il1il1bs6Tmsb7(instruction);\n+ uint64 rt3_value = extr_rt3il7il0bs3Fmsb2(instruction);\n+\n+ std::string rt3 = GPR(encode_gpr3(rt3_value));\n+ std::string s = ADDRESS(encode_s_from_address(s_value), 2);\n+\n+ return img::format(\"BNEZC %s, %s\", rt3, s);\n+}\n+\n+\n+std::string NMD::JRC(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil5il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"JRC %s\", rt);\n+}\n+\n+\n+std::string NMD::JALRC_16_(uint64 instruction)\n+{\n+ uint64 rt_value = extr_rtil5il0bs5Fmsb4(instruction);\n+\n+ std::string rt = GPR(copy(rt_value));\n+\n+ return img::format(\"JALRC $%d, %s\", 31, rt);\n+}\n+\n+\n+std::string NMD::BEQC_16_(uint64 instruction)\n+{\n+ uint64 u_value = extr_uil0il1bs4Fmsb4(instruction);\n+ uint64 rt3_value = extr_rt3il7il0bs3Fmsb2(instruction);\n+ uint64 rs3_value = extr_rs3il4il0bs3Fmsb2(instruction);\n+\n+ std::string rs3 = GPR(encode_rs3_and_check_rs3_lt_rt3(rs3_value));\n+ std::string rt3 = GPR(encode_gpr3(rt3_value));\n+ std::string u = ADDRESS(encode_u_from_address(u_value), 2);\n+\n+ return img::format(\"BEQC %s, %s, %s\", rs3, rt3, u);\n+}\n+\n+\n+std::string NMD::BNEC_16_(uint64 instruction)\n+{\n+ uint64 u_value = extr_uil0il1bs4Fmsb4(instruction);\n+ uint64 rt3_value = extr_rt3il7il0bs3Fmsb2(instruction);\n+ uint64 rs3_value = extr_rs3il4il0bs3Fmsb2(instruction);\n+\n+ std::string rs3 = GPR(encode_rs3_and_check_rs3_ge_rt3(rs3_value));\n+ std::string rt3 = GPR(encode_gpr3(rt3_value));\n+ std::string u = ADDRESS(encode_u_from_address(u_value), 2);\n+\n+ return img::format(\"BNEC %s, %s, %s\", rs3, rt3, u);\n+}\n+\n+\n+std::string NMD::SAVE_16_(uint64 instruction)\n+{\n+ uint64 count_value = extr_countil0il0bs4Fmsb3(instruction);\n+ uint64 rt1_value = extr_rt1il9il0bs1Fmsb0(instruction);\n+ uint64 u_value = extr_uil4il4bs4Fmsb7(instruction);\n+\n+ std::string u = IMMEDIATE(copy(u_value));\n+ return img::format(\"SAVE %s%s\", u,\n+ save_restore_list(encode_rt1_from_rt(rt1_value), count_value, 0));\n+}\n+\n+\n+std::string NMD::RESTORE_JRC_16_(uint64 instruction)\n+{\n+ uint64 count_value = extr_countil0il0bs4Fmsb3(instruction);\n+ uint64 rt1_value = extr_rt1il9il0bs1Fmsb0(instruction);\n+ uint64 u_value = extr_uil4il4bs4Fmsb7(instruction);\n+\n+ std::string u = IMMEDIATE(copy(u_value));\n+ return img::format(\"RESTORE.JRC %s%s\", u,\n+ save_restore_list(encode_rt1_from_rt(rt1_value), count_value, 0));\n+}\n+\n+\n+std::string NMD::ADDU_4X4_(uint64 instruction)\n+{\n+ uint64 rs4_value = extr_rs4il0il0bs3_il4il3bs1Fmsb3(instruction);\n+ uint64 rt4_value = extr_rt4il5il0bs3_il9il3bs1Fmsb3(instruction);\n+\n+ std::string rs4 = GPR(encode_gpr4(rs4_value));\n+ std::string rt4 = GPR(encode_gpr4(rt4_value));\n+\n+ return img::format(\"ADDU %s, %s\", rs4, rt4);\n+}\n+\n+\n+std::string NMD::MUL_4X4_(uint64 instruction)\n+{\n+ uint64 rs4_value = extr_rs4il0il0bs3_il4il3bs1Fmsb3(instruction);\n+ uint64 rt4_value = extr_rt4il5il0bs3_il9il3bs1Fmsb3(instruction);\n+\n+ std::string rs4 = GPR(encode_gpr4(rs4_value));\n+ std::string rt4 = GPR(encode_gpr4(rt4_value));\n+\n+ return img::format(\"MUL %s, %s\", rs4, rt4);\n+}\n+\n+\n+std::string NMD::LB_16_(uint64 instruction)\n+{\n+ uint64 u_value = extr_uil0il0bs2Fmsb1(instruction);\n+ uint64 rt3_value = extr_rt3il7il0bs3Fmsb2(instruction);\n+ uint64 rs3_value = extr_rs3il4il0bs3Fmsb2(instruction);\n+\n+ std::string rt3 = GPR(encode_gpr3(rt3_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string rs3 = GPR(encode_gpr3(rs3_value));\n+\n+ return img::format(\"LB %s, %s(%s)\", rt3, u, rs3);\n+}\n+\n+\n+std::string NMD::SB_16_(uint64 instruction)\n+{\n+ uint64 rtz3_value = extr_rtz3il7il0bs3Fmsb2(instruction);\n+ uint64 u_value = extr_uil0il0bs2Fmsb1(instruction);\n+ uint64 rs3_value = extr_rs3il4il0bs3Fmsb2(instruction);\n+\n+ std::string rtz3 = GPR(encode_gpr3_store(rtz3_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string rs3 = GPR(encode_gpr3(rs3_value));\n+\n+ return img::format(\"SB %s, %s(%s)\", rtz3, u, rs3);\n+}\n+\n+\n+std::string NMD::LBU_16_(uint64 instruction)\n+{\n+ uint64 u_value = extr_uil0il0bs2Fmsb1(instruction);\n+ uint64 rt3_value = extr_rt3il7il0bs3Fmsb2(instruction);\n+ uint64 rs3_value = extr_rs3il4il0bs3Fmsb2(instruction);\n+\n+ std::string rt3 = GPR(encode_gpr3(rt3_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string rs3 = GPR(encode_gpr3(rs3_value));\n+\n+ return img::format(\"LBU %s, %s(%s)\", rt3, u, rs3);\n+}\n+\n+\n+std::string NMD::LH_16_(uint64 instruction)\n+{\n+ uint64 u_value = extr_uil1il1bs2Fmsb2(instruction);\n+ uint64 rt3_value = extr_rt3il7il0bs3Fmsb2(instruction);\n+ uint64 rs3_value = extr_rs3il4il0bs3Fmsb2(instruction);\n+\n+ std::string rt3 = GPR(encode_gpr3(rt3_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string rs3 = GPR(encode_gpr3(rs3_value));\n+\n+ return img::format(\"LH %s, %s(%s)\", rt3, u, rs3);\n+}\n+\n+\n+std::string NMD::SH_16_(uint64 instruction)\n+{\n+ uint64 rtz3_value = extr_rtz3il7il0bs3Fmsb2(instruction);\n+ uint64 u_value = extr_uil1il1bs2Fmsb2(instruction);\n+ uint64 rs3_value = extr_rs3il4il0bs3Fmsb2(instruction);\n+\n+ std::string rtz3 = GPR(encode_gpr3_store(rtz3_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string rs3 = GPR(encode_gpr3(rs3_value));\n+\n+ return img::format(\"SH %s, %s(%s)\", rtz3, u, rs3);\n+}\n+\n+\n+std::string NMD::LHU_16_(uint64 instruction)\n+{\n+ uint64 u_value = extr_uil1il1bs2Fmsb2(instruction);\n+ uint64 rt3_value = extr_rt3il7il0bs3Fmsb2(instruction);\n+ uint64 rs3_value = extr_rs3il4il0bs3Fmsb2(instruction);\n+\n+ std::string rt3 = GPR(encode_gpr3(rt3_value));\n+ std::string u = IMMEDIATE(copy(u_value));\n+ std::string rs3 = GPR(encode_gpr3(rs3_value));\n+\n+ return img::format(\"LHU %s, %s(%s)\", rt3, u, rs3);\n+}\n+\n+\n+std::string NMD::MOVEP(uint64 instruction)\n+{\n+ uint64 rsz4_value = extr_rsz4il0il0bs3_il4il3bs1Fmsb3(instruction);\n+ uint64 rtz4_value = extr_rtz4il5il0bs3_il9il3bs1Fmsb3(instruction);\n+ uint64 rd2_value = extr_rd2il3il1bs1_il8il0bs1Fmsb1(instruction);\n+\n+ std::string rd2 = GPR(encode_rd2_reg1(rd2_value));\n+ std::string re2 = GPR(encode_rd2_reg2(rd2_value));\n+ /* !!!!!!!!!! - no conversion function */\n+ std::string rsz4 = GPR(encode_gpr4_zero(rsz4_value));\n+ std::string rtz4 = GPR(encode_gpr4_zero(rtz4_value));\n+\n+ return img::format(\"MOVEP %s, %s, %s, %s\", rd2, re2, rsz4, rtz4);\n+ /* hand edited */\n+}\n+\n+\n+std::string NMD::MOVEP_REV_(uint64 instruction)\n+{\n+ uint64 rs4_value = extr_rs4il0il0bs3_il4il3bs1Fmsb3(instruction);\n+ uint64 rt4_value = extr_rt4il5il0bs3_il9il3bs1Fmsb3(instruction);\n+ uint64 rd2_value = extr_rd2il3il1bs1_il8il0bs1Fmsb1(instruction);\n+\n+ std::string rs4 = GPR(encode_gpr4(rs4_value));\n+ std::string rt4 = GPR(encode_gpr4(rt4_value));\n+ std::string rd2 = GPR(encode_rd2_reg1(rd2_value));\n+ std::string rs2 = GPR(encode_rd2_reg2(rd2_value));\n+ /* !!!!!!!!!! - no conversion function */\n+\n+ return img::format(\"MOVEP %s, %s, %s, %s\", rs4, rt4, rd2, rs2);\n+ /* hand edited */\n+}\n+\n+\n+NMD::Pool NMD::P_SYSCALL[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfffc0000, 0x00080000, &NMD::SYSCALL_32_ , 0,\n+ 0x0 }, /* SYSCALL[32] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfffc0000, 0x000c0000, &NMD::HYPCALL , 0,\n+ CP0_ | VZ_ }, /* HYPCALL */\n+};\n+\n+\n+NMD::Pool NMD::P_RI[4] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfff80000, 0x00000000, &NMD::SIGRIE , 0,\n+ 0x0 }, /* SIGRIE */\n+ { pool , P_SYSCALL , 2 , 32,\n+ 0xfff80000, 0x00080000, 0 , 0,\n+ 0x0 }, /* P.SYSCALL */\n+ { instruction , 0 , 0 , 32,\n+ 0xfff80000, 0x00100000, &NMD::BREAK_32_ , 0,\n+ 0x0 }, /* BREAK[32] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfff80000, 0x00180000, &NMD::SDBBP_32_ , 0,\n+ EJTAG_ }, /* SDBBP[32] */\n+};\n+\n+\n+NMD::Pool NMD::P_ADDIU[2] = {\n+ { pool , P_RI , 4 , 32,\n+ 0xffe00000, 0x00000000, 0 , 0,\n+ 0x0 }, /* P.RI */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc000000, 0x00000000, &NMD::ADDIU_32_ , &NMD::ADDIU_32__cond ,\n+ 0x0 }, /* ADDIU[32] */\n+};\n+\n+\n+NMD::Pool NMD::P_TRAP[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x20000000, &NMD::TEQ , 0,\n+ XMMS_ }, /* TEQ */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x20000400, &NMD::TNE , 0,\n+ XMMS_ }, /* TNE */\n+};\n+\n+\n+NMD::Pool NMD::P_CMOVE[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x20000210, &NMD::MOVZ , 0,\n+ 0x0 }, /* MOVZ */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x20000610, &NMD::MOVN , 0,\n+ 0x0 }, /* MOVN */\n+};\n+\n+\n+NMD::Pool NMD::P_D_MT_VPE[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc1f3fff, 0x20010ab0, &NMD::DMT , 0,\n+ MT_ }, /* DMT */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc1f3fff, 0x20000ab0, &NMD::DVPE , 0,\n+ MT_ }, /* DVPE */\n+};\n+\n+\n+NMD::Pool NMD::P_E_MT_VPE[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc1f3fff, 0x20010eb0, &NMD::EMT , 0,\n+ MT_ }, /* EMT */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc1f3fff, 0x20000eb0, &NMD::EVPE , 0,\n+ MT_ }, /* EVPE */\n+};\n+\n+\n+NMD::Pool NMD::_P_MT_VPE[2] = {\n+ { pool , P_D_MT_VPE , 2 , 32,\n+ 0xfc003fff, 0x20000ab0, 0 , 0,\n+ 0x0 }, /* P.D_MT_VPE */\n+ { pool , P_E_MT_VPE , 2 , 32,\n+ 0xfc003fff, 0x20000eb0, 0 , 0,\n+ 0x0 }, /* P.E_MT_VPE */\n+};\n+\n+\n+NMD::Pool NMD::P_MT_VPE[8] = {\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003bff, 0x200002b0, 0 , 0,\n+ 0x0 }, /* P.MT_VPE~*(0) */\n+ { pool , _P_MT_VPE , 2 , 32,\n+ 0xfc003bff, 0x20000ab0, 0 , 0,\n+ 0x0 }, /* _P.MT_VPE */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003bff, 0x200012b0, 0 , 0,\n+ 0x0 }, /* P.MT_VPE~*(2) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003bff, 0x20001ab0, 0 , 0,\n+ 0x0 }, /* P.MT_VPE~*(3) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003bff, 0x200022b0, 0 , 0,\n+ 0x0 }, /* P.MT_VPE~*(4) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003bff, 0x20002ab0, 0 , 0,\n+ 0x0 }, /* P.MT_VPE~*(5) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003bff, 0x200032b0, 0 , 0,\n+ 0x0 }, /* P.MT_VPE~*(6) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003bff, 0x20003ab0, 0 , 0,\n+ 0x0 }, /* P.MT_VPE~*(7) */\n+};\n+\n+\n+NMD::Pool NMD::P_DVP[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20000390, &NMD::DVP , 0,\n+ 0x0 }, /* DVP */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20000790, &NMD::EVP , 0,\n+ 0x0 }, /* EVP */\n+};\n+\n+\n+NMD::Pool NMD::P_SLTU[2] = {\n+ { pool , P_DVP , 2 , 32,\n+ 0xfc00fbff, 0x20000390, 0 , 0,\n+ 0x0 }, /* P.DVP */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000390, &NMD::SLTU , &NMD::SLTU_cond ,\n+ 0x0 }, /* SLTU */\n+};\n+\n+\n+NMD::Pool NMD::_POOL32A0[128] = {\n+ { pool , P_TRAP , 2 , 32,\n+ 0xfc0003ff, 0x20000000, 0 , 0,\n+ 0x0 }, /* P.TRAP */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000008, &NMD::SEB , 0,\n+ XMMS_ }, /* SEB */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000010, &NMD::SLLV , 0,\n+ 0x0 }, /* SLLV */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000018, &NMD::MUL_32_ , 0,\n+ 0x0 }, /* MUL[32] */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000020, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(4) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000028, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(5) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000030, &NMD::MFC0 , 0,\n+ 0x0 }, /* MFC0 */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000038, &NMD::MFHC0 , 0,\n+ CP0_ | MVH_ }, /* MFHC0 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000040, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(8) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000048, &NMD::SEH , 0,\n+ 0x0 }, /* SEH */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000050, &NMD::SRLV , 0,\n+ 0x0 }, /* SRLV */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000058, &NMD::MUH , 0,\n+ 0x0 }, /* MUH */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000060, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(12) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000068, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(13) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000070, &NMD::MTC0 , 0,\n+ CP0_ }, /* MTC0 */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000078, &NMD::MTHC0 , 0,\n+ CP0_ | MVH_ }, /* MTHC0 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000080, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(16) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000088, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(17) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000090, &NMD::SRAV , 0,\n+ 0x0 }, /* SRAV */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000098, &NMD::MULU , 0,\n+ 0x0 }, /* MULU */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200000a0, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(20) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200000a8, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(21) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200000b0, &NMD::MFGC0 , 0,\n+ CP0_ | VZ_ }, /* MFGC0 */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200000b8, &NMD::MFHGC0 , 0,\n+ CP0_ | VZ_ | MVH_ }, /* MFHGC0 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200000c0, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(24) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200000c8, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(25) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200000d0, &NMD::ROTRV , 0,\n+ 0x0 }, /* ROTRV */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200000d8, &NMD::MUHU , 0,\n+ 0x0 }, /* MUHU */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200000e0, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(28) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200000e8, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(29) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200000f0, &NMD::MTGC0 , 0,\n+ CP0_ | VZ_ }, /* MTGC0 */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200000f8, &NMD::MTHGC0 , 0,\n+ CP0_ | VZ_ | MVH_ }, /* MTHGC0 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000100, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(32) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000108, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(33) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000110, &NMD::ADD , 0,\n+ XMMS_ }, /* ADD */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000118, &NMD::DIV , 0,\n+ 0x0 }, /* DIV */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000120, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(36) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000128, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(37) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000130, &NMD::DMFC0 , 0,\n+ CP0_ | MIPS64_ }, /* DMFC0 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000138, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(39) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000140, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(40) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000148, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(41) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000150, &NMD::ADDU_32_ , 0,\n+ 0x0 }, /* ADDU[32] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000158, &NMD::MOD , 0,\n+ 0x0 }, /* MOD */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000160, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(44) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000168, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(45) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000170, &NMD::DMTC0 , 0,\n+ CP0_ | MIPS64_ }, /* DMTC0 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000178, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(47) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000180, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(48) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000188, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(49) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000190, &NMD::SUB , 0,\n+ XMMS_ }, /* SUB */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000198, &NMD::DIVU , 0,\n+ 0x0 }, /* DIVU */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200001a0, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(52) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200001a8, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(53) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200001b0, &NMD::DMFGC0 , 0,\n+ CP0_ | MIPS64_ | VZ_}, /* DMFGC0 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200001b8, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(55) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200001c0, &NMD::RDHWR , 0,\n+ XMMS_ }, /* RDHWR */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200001c8, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(57) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200001d0, &NMD::SUBU_32_ , 0,\n+ 0x0 }, /* SUBU[32] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200001d8, &NMD::MODU , 0,\n+ 0x0 }, /* MODU */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200001e0, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(60) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200001e8, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(61) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200001f0, &NMD::DMTGC0 , 0,\n+ CP0_ | MIPS64_ | VZ_}, /* DMTGC0 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200001f8, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(63) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000200, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(64) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000208, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(65) */\n+ { pool , P_CMOVE , 2 , 32,\n+ 0xfc0003ff, 0x20000210, 0 , 0,\n+ 0x0 }, /* P.CMOVE */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000218, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(67) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000220, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(68) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000228, &NMD::FORK , 0,\n+ MT_ }, /* FORK */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000230, &NMD::MFTR , 0,\n+ MT_ }, /* MFTR */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000238, &NMD::MFHTR , 0,\n+ MT_ }, /* MFHTR */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000240, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(72) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000248, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(73) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000250, &NMD::AND_32_ , 0,\n+ 0x0 }, /* AND[32] */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000258, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(75) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000260, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(76) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000268, &NMD::YIELD , 0,\n+ MT_ }, /* YIELD */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000270, &NMD::MTTR , 0,\n+ MT_ }, /* MTTR */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000278, &NMD::MTHTR , 0,\n+ MT_ }, /* MTHTR */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000280, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(80) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000288, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(81) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000290, &NMD::OR_32_ , 0,\n+ 0x0 }, /* OR[32] */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000298, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(83) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200002a0, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(84) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200002a8, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(85) */\n+ { pool , P_MT_VPE , 8 , 32,\n+ 0xfc0003ff, 0x200002b0, 0 , 0,\n+ 0x0 }, /* P.MT_VPE */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200002b8, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(87) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200002c0, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(88) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200002c8, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(89) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200002d0, &NMD::NOR , 0,\n+ 0x0 }, /* NOR */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200002d8, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(91) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200002e0, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(92) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200002e8, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(93) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200002f0, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(94) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200002f8, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(95) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000300, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(96) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000308, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(97) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000310, &NMD::XOR_32_ , 0,\n+ 0x0 }, /* XOR[32] */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000318, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(99) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000320, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(100) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000328, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(101) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000330, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(102) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000338, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(103) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000340, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(104) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000348, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(105) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000350, &NMD::SLT , 0,\n+ 0x0 }, /* SLT */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000358, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(107) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000360, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(108) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000368, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(109) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000370, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(110) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000378, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(111) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000380, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(112) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000388, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(113) */\n+ { pool , P_SLTU , 2 , 32,\n+ 0xfc0003ff, 0x20000390, 0 , 0,\n+ 0x0 }, /* P.SLTU */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000398, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(115) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200003a0, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(116) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200003a8, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(117) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200003b0, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(118) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200003b8, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(119) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200003c0, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(120) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200003c8, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(121) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200003d0, &NMD::SOV , 0,\n+ 0x0 }, /* SOV */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200003d8, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(123) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200003e0, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(124) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200003e8, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(125) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200003f0, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(126) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200003f8, 0 , 0,\n+ 0x0 }, /* _POOL32A0~*(127) */\n+};\n+\n+\n+NMD::Pool NMD::ADDQ__S__PH[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x2000000d, &NMD::ADDQ_PH , 0,\n+ DSP_ }, /* ADDQ.PH */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x2000040d, &NMD::ADDQ_S_PH , 0,\n+ DSP_ }, /* ADDQ_S.PH */\n+};\n+\n+\n+NMD::Pool NMD::MUL__S__PH[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x2000002d, &NMD::MUL_PH , 0,\n+ DSP_ }, /* MUL.PH */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x2000042d, &NMD::MUL_S_PH , 0,\n+ DSP_ }, /* MUL_S.PH */\n+};\n+\n+\n+NMD::Pool NMD::ADDQH__R__PH[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x2000004d, &NMD::ADDQH_PH , 0,\n+ DSP_ }, /* ADDQH.PH */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x2000044d, &NMD::ADDQH_R_PH , 0,\n+ DSP_ }, /* ADDQH_R.PH */\n+};\n+\n+\n+NMD::Pool NMD::ADDQH__R__W[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x2000008d, &NMD::ADDQH_W , 0,\n+ DSP_ }, /* ADDQH.W */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x2000048d, &NMD::ADDQH_R_W , 0,\n+ DSP_ }, /* ADDQH_R.W */\n+};\n+\n+\n+NMD::Pool NMD::ADDU__S__QB[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x200000cd, &NMD::ADDU_QB , 0,\n+ DSP_ }, /* ADDU.QB */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x200004cd, &NMD::ADDU_S_QB , 0,\n+ DSP_ }, /* ADDU_S.QB */\n+};\n+\n+\n+NMD::Pool NMD::ADDU__S__PH[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x2000010d, &NMD::ADDU_PH , 0,\n+ DSP_ }, /* ADDU.PH */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x2000050d, &NMD::ADDU_S_PH , 0,\n+ DSP_ }, /* ADDU_S.PH */\n+};\n+\n+\n+NMD::Pool NMD::ADDUH__R__QB[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x2000014d, &NMD::ADDUH_QB , 0,\n+ DSP_ }, /* ADDUH.QB */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x2000054d, &NMD::ADDUH_R_QB , 0,\n+ DSP_ }, /* ADDUH_R.QB */\n+};\n+\n+\n+NMD::Pool NMD::SHRAV__R__PH[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x2000018d, &NMD::SHRAV_PH , 0,\n+ DSP_ }, /* SHRAV.PH */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x2000058d, &NMD::SHRAV_R_PH , 0,\n+ DSP_ }, /* SHRAV_R.PH */\n+};\n+\n+\n+NMD::Pool NMD::SHRAV__R__QB[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x200001cd, &NMD::SHRAV_QB , 0,\n+ DSP_ }, /* SHRAV.QB */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x200005cd, &NMD::SHRAV_R_QB , 0,\n+ DSP_ }, /* SHRAV_R.QB */\n+};\n+\n+\n+NMD::Pool NMD::SUBQ__S__PH[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x2000020d, &NMD::SUBQ_PH , 0,\n+ DSP_ }, /* SUBQ.PH */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x2000060d, &NMD::SUBQ_S_PH , 0,\n+ DSP_ }, /* SUBQ_S.PH */\n+};\n+\n+\n+NMD::Pool NMD::SUBQH__R__PH[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x2000024d, &NMD::SUBQH_PH , 0,\n+ DSP_ }, /* SUBQH.PH */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x2000064d, &NMD::SUBQH_R_PH , 0,\n+ DSP_ }, /* SUBQH_R.PH */\n+};\n+\n+\n+NMD::Pool NMD::SUBQH__R__W[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x2000028d, &NMD::SUBQH_W , 0,\n+ DSP_ }, /* SUBQH.W */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x2000068d, &NMD::SUBQH_R_W , 0,\n+ DSP_ }, /* SUBQH_R.W */\n+};\n+\n+\n+NMD::Pool NMD::SUBU__S__QB[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x200002cd, &NMD::SUBU_QB , 0,\n+ DSP_ }, /* SUBU.QB */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x200006cd, &NMD::SUBU_S_QB , 0,\n+ DSP_ }, /* SUBU_S.QB */\n+};\n+\n+\n+NMD::Pool NMD::SUBU__S__PH[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x2000030d, &NMD::SUBU_PH , 0,\n+ DSP_ }, /* SUBU.PH */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x2000070d, &NMD::SUBU_S_PH , 0,\n+ DSP_ }, /* SUBU_S.PH */\n+};\n+\n+\n+NMD::Pool NMD::SHRA__R__PH[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x20000335, &NMD::SHRA_PH , 0,\n+ DSP_ }, /* SHRA.PH */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x20000735, &NMD::SHRA_R_PH , 0,\n+ DSP_ }, /* SHRA_R.PH */\n+};\n+\n+\n+NMD::Pool NMD::SUBUH__R__QB[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x2000034d, &NMD::SUBUH_QB , 0,\n+ DSP_ }, /* SUBUH.QB */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x2000074d, &NMD::SUBUH_R_QB , 0,\n+ DSP_ }, /* SUBUH_R.QB */\n+};\n+\n+\n+NMD::Pool NMD::SHLLV__S__PH[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x2000038d, &NMD::SHLLV_PH , 0,\n+ DSP_ }, /* SHLLV.PH */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x2000078d, &NMD::SHLLV_S_PH , 0,\n+ DSP_ }, /* SHLLV_S.PH */\n+};\n+\n+\n+NMD::Pool NMD::SHLL__S__PH[4] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc000fff, 0x200003b5, &NMD::SHLL_PH , 0,\n+ DSP_ }, /* SHLL.PH */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000fff, 0x200007b5, 0 , 0,\n+ 0x0 }, /* SHLL[_S].PH~*(1) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc000fff, 0x20000bb5, &NMD::SHLL_S_PH , 0,\n+ DSP_ }, /* SHLL_S.PH */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000fff, 0x20000fb5, 0 , 0,\n+ 0x0 }, /* SHLL[_S].PH~*(3) */\n+};\n+\n+\n+NMD::Pool NMD::PRECR_SRA__R__PH_W[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x200003cd, &NMD::PRECR_SRA_PH_W , 0,\n+ DSP_ }, /* PRECR_SRA.PH.W */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x200007cd, &NMD::PRECR_SRA_R_PH_W , 0,\n+ DSP_ }, /* PRECR_SRA_R.PH.W */\n+};\n+\n+\n+NMD::Pool NMD::_POOL32A5[128] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000005, &NMD::CMP_EQ_PH , 0,\n+ DSP_ }, /* CMP.EQ.PH */\n+ { pool , ADDQ__S__PH , 2 , 32,\n+ 0xfc0003ff, 0x2000000d, 0 , 0,\n+ 0x0 }, /* ADDQ[_S].PH */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000015, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(2) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x2000001d, &NMD::SHILO , 0,\n+ DSP_ }, /* SHILO */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000025, &NMD::MULEQ_S_W_PHL , 0,\n+ DSP_ }, /* MULEQ_S.W.PHL */\n+ { pool , MUL__S__PH , 2 , 32,\n+ 0xfc0003ff, 0x2000002d, 0 , 0,\n+ 0x0 }, /* MUL[_S].PH */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000035, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(6) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x2000003d, &NMD::REPL_PH , 0,\n+ DSP_ }, /* REPL.PH */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000045, &NMD::CMP_LT_PH , 0,\n+ DSP_ }, /* CMP.LT.PH */\n+ { pool , ADDQH__R__PH , 2 , 32,\n+ 0xfc0003ff, 0x2000004d, 0 , 0,\n+ 0x0 }, /* ADDQH[_R].PH */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000055, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(10) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x2000005d, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(11) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000065, &NMD::MULEQ_S_W_PHR , 0,\n+ DSP_ }, /* MULEQ_S.W.PHR */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x2000006d, &NMD::PRECR_QB_PH , 0,\n+ DSP_ }, /* PRECR.QB.PH */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000075, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(14) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x2000007d, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(15) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000085, &NMD::CMP_LE_PH , 0,\n+ DSP_ }, /* CMP.LE.PH */\n+ { pool , ADDQH__R__W , 2 , 32,\n+ 0xfc0003ff, 0x2000008d, 0 , 0,\n+ 0x0 }, /* ADDQH[_R].W */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000095, &NMD::MULEU_S_PH_QBL , 0,\n+ DSP_ }, /* MULEU_S.PH.QBL */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x2000009d, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(19) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200000a5, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(20) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200000ad, &NMD::PRECRQ_QB_PH , 0,\n+ DSP_ }, /* PRECRQ.QB.PH */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200000b5, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(22) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200000bd, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(23) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200000c5, &NMD::CMPGU_EQ_QB , 0,\n+ DSP_ }, /* CMPGU.EQ.QB */\n+ { pool , ADDU__S__QB , 2 , 32,\n+ 0xfc0003ff, 0x200000cd, 0 , 0,\n+ 0x0 }, /* ADDU[_S].QB */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200000d5, &NMD::MULEU_S_PH_QBR , 0,\n+ DSP_ }, /* MULEU_S.PH.QBR */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200000dd, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(27) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200000e5, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(28) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200000ed, &NMD::PRECRQ_PH_W , 0,\n+ DSP_ }, /* PRECRQ.PH.W */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200000f5, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(30) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200000fd, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(31) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000105, &NMD::CMPGU_LT_QB , 0,\n+ DSP_ }, /* CMPGU.LT.QB */\n+ { pool , ADDU__S__PH , 2 , 32,\n+ 0xfc0003ff, 0x2000010d, 0 , 0,\n+ 0x0 }, /* ADDU[_S].PH */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000115, &NMD::MULQ_RS_PH , 0,\n+ DSP_ }, /* MULQ_RS.PH */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x2000011d, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(35) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000125, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(36) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x2000012d, &NMD::PRECRQ_RS_PH_W , 0,\n+ DSP_ }, /* PRECRQ_RS.PH.W */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000135, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(38) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x2000013d, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(39) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000145, &NMD::CMPGU_LE_QB , 0,\n+ DSP_ }, /* CMPGU.LE.QB */\n+ { pool , ADDUH__R__QB , 2 , 32,\n+ 0xfc0003ff, 0x2000014d, 0 , 0,\n+ 0x0 }, /* ADDUH[_R].QB */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000155, &NMD::MULQ_S_PH , 0,\n+ DSP_ }, /* MULQ_S.PH */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x2000015d, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(43) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000165, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(44) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x2000016d, &NMD::PRECRQU_S_QB_PH , 0,\n+ DSP_ }, /* PRECRQU_S.QB.PH */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000175, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(46) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x2000017d, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(47) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000185, &NMD::CMPGDU_EQ_QB , 0,\n+ DSP_ }, /* CMPGDU.EQ.QB */\n+ { pool , SHRAV__R__PH , 2 , 32,\n+ 0xfc0003ff, 0x2000018d, 0 , 0,\n+ 0x0 }, /* SHRAV[_R].PH */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000195, &NMD::MULQ_RS_W , 0,\n+ DSP_ }, /* MULQ_RS.W */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x2000019d, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(51) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200001a5, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(52) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200001ad, &NMD::PACKRL_PH , 0,\n+ DSP_ }, /* PACKRL.PH */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200001b5, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(54) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200001bd, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(55) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200001c5, &NMD::CMPGDU_LT_QB , 0,\n+ DSP_ }, /* CMPGDU.LT.QB */\n+ { pool , SHRAV__R__QB , 2 , 32,\n+ 0xfc0003ff, 0x200001cd, 0 , 0,\n+ 0x0 }, /* SHRAV[_R].QB */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200001d5, &NMD::MULQ_S_W , 0,\n+ DSP_ }, /* MULQ_S.W */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200001dd, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(59) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200001e5, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(60) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200001ed, &NMD::PICK_QB , 0,\n+ DSP_ }, /* PICK.QB */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200001f5, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(62) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200001fd, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(63) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000205, &NMD::CMPGDU_LE_QB , 0,\n+ DSP_ }, /* CMPGDU.LE.QB */\n+ { pool , SUBQ__S__PH , 2 , 32,\n+ 0xfc0003ff, 0x2000020d, 0 , 0,\n+ 0x0 }, /* SUBQ[_S].PH */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000215, &NMD::APPEND , 0,\n+ DSP_ }, /* APPEND */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x2000021d, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(67) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000225, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(68) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x2000022d, &NMD::PICK_PH , 0,\n+ DSP_ }, /* PICK.PH */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000235, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(70) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x2000023d, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(71) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000245, &NMD::CMPU_EQ_QB , 0,\n+ DSP_ }, /* CMPU.EQ.QB */\n+ { pool , SUBQH__R__PH , 2 , 32,\n+ 0xfc0003ff, 0x2000024d, 0 , 0,\n+ 0x0 }, /* SUBQH[_R].PH */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000255, &NMD::PREPEND , 0,\n+ DSP_ }, /* PREPEND */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x2000025d, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(75) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000265, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(76) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x2000026d, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(77) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000275, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(78) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x2000027d, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(79) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000285, &NMD::CMPU_LT_QB , 0,\n+ DSP_ }, /* CMPU.LT.QB */\n+ { pool , SUBQH__R__W , 2 , 32,\n+ 0xfc0003ff, 0x2000028d, 0 , 0,\n+ 0x0 }, /* SUBQH[_R].W */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000295, &NMD::MODSUB , 0,\n+ DSP_ }, /* MODSUB */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x2000029d, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(83) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200002a5, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(84) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200002ad, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(85) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200002b5, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(86) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200002bd, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(87) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200002c5, &NMD::CMPU_LE_QB , 0,\n+ DSP_ }, /* CMPU.LE.QB */\n+ { pool , SUBU__S__QB , 2 , 32,\n+ 0xfc0003ff, 0x200002cd, 0 , 0,\n+ 0x0 }, /* SUBU[_S].QB */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200002d5, &NMD::SHRAV_R_W , 0,\n+ DSP_ }, /* SHRAV_R.W */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200002dd, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(91) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200002e5, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(92) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200002ed, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(93) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200002f5, &NMD::SHRA_R_W , 0,\n+ DSP_ }, /* SHRA_R.W */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200002fd, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(95) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000305, &NMD::ADDQ_S_W , 0,\n+ DSP_ }, /* ADDQ_S.W */\n+ { pool , SUBU__S__PH , 2 , 32,\n+ 0xfc0003ff, 0x2000030d, 0 , 0,\n+ 0x0 }, /* SUBU[_S].PH */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000315, &NMD::SHRLV_PH , 0,\n+ DSP_ }, /* SHRLV.PH */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x2000031d, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(99) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000325, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(100) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x2000032d, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(101) */\n+ { pool , SHRA__R__PH , 2 , 32,\n+ 0xfc0003ff, 0x20000335, 0 , 0,\n+ 0x0 }, /* SHRA[_R].PH */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x2000033d, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(103) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000345, &NMD::SUBQ_S_W , 0,\n+ DSP_ }, /* SUBQ_S.W */\n+ { pool , SUBUH__R__QB , 2 , 32,\n+ 0xfc0003ff, 0x2000034d, 0 , 0,\n+ 0x0 }, /* SUBUH[_R].QB */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000355, &NMD::SHRLV_QB , 0,\n+ DSP_ }, /* SHRLV.QB */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x2000035d, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(107) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000365, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(108) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x2000036d, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(109) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000375, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(110) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x2000037d, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(111) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000385, &NMD::ADDSC , 0,\n+ DSP_ }, /* ADDSC */\n+ { pool , SHLLV__S__PH , 2 , 32,\n+ 0xfc0003ff, 0x2000038d, 0 , 0,\n+ 0x0 }, /* SHLLV[_S].PH */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x20000395, &NMD::SHLLV_QB , 0,\n+ DSP_ }, /* SHLLV.QB */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x2000039d, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(115) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200003a5, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(116) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200003ad, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(117) */\n+ { pool , SHLL__S__PH , 4 , 32,\n+ 0xfc0003ff, 0x200003b5, 0 , 0,\n+ 0x0 }, /* SHLL[_S].PH */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200003bd, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(119) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200003c5, &NMD::ADDWC , 0,\n+ DSP_ }, /* ADDWC */\n+ { pool , PRECR_SRA__R__PH_W , 2 , 32,\n+ 0xfc0003ff, 0x200003cd, 0 , 0,\n+ 0x0 }, /* PRECR_SRA[_R].PH.W */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200003d5, &NMD::SHLLV_S_W , 0,\n+ DSP_ }, /* SHLLV_S.W */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200003dd, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(123) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200003e5, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(124) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200003ed, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(125) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200003f5, &NMD::SHLL_S_W , 0,\n+ DSP_ }, /* SHLL_S.W */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0x200003fd, 0 , 0,\n+ 0x0 }, /* _POOL32A5~*(127) */\n+};\n+\n+\n+NMD::Pool NMD::PP_LSX[16] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x20000007, &NMD::LBX , 0,\n+ 0x0 }, /* LBX */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x20000087, &NMD::SBX , 0,\n+ XMMS_ }, /* SBX */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x20000107, &NMD::LBUX , 0,\n+ 0x0 }, /* LBUX */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0007ff, 0x20000187, 0 , 0,\n+ 0x0 }, /* PP.LSX~*(3) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x20000207, &NMD::LHX , 0,\n+ 0x0 }, /* LHX */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x20000287, &NMD::SHX , 0,\n+ XMMS_ }, /* SHX */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x20000307, &NMD::LHUX , 0,\n+ 0x0 }, /* LHUX */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x20000387, &NMD::LWUX , 0,\n+ MIPS64_ }, /* LWUX */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x20000407, &NMD::LWX , 0,\n+ 0x0 }, /* LWX */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x20000487, &NMD::SWX , 0,\n+ XMMS_ }, /* SWX */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x20000507, &NMD::LWC1X , 0,\n+ CP1_ }, /* LWC1X */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x20000587, &NMD::SWC1X , 0,\n+ CP1_ }, /* SWC1X */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x20000607, &NMD::LDX , 0,\n+ MIPS64_ }, /* LDX */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x20000687, &NMD::SDX , 0,\n+ MIPS64_ }, /* SDX */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x20000707, &NMD::LDC1X , 0,\n+ CP1_ }, /* LDC1X */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x20000787, &NMD::SDC1X , 0,\n+ CP1_ }, /* SDC1X */\n+};\n+\n+\n+NMD::Pool NMD::PP_LSXS[16] = {\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0007ff, 0x20000047, 0 , 0,\n+ 0x0 }, /* PP.LSXS~*(0) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0007ff, 0x200000c7, 0 , 0,\n+ 0x0 }, /* PP.LSXS~*(1) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0007ff, 0x20000147, 0 , 0,\n+ 0x0 }, /* PP.LSXS~*(2) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0007ff, 0x200001c7, 0 , 0,\n+ 0x0 }, /* PP.LSXS~*(3) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x20000247, &NMD::LHXS , 0,\n+ 0x0 }, /* LHXS */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x200002c7, &NMD::SHXS , 0,\n+ XMMS_ }, /* SHXS */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x20000347, &NMD::LHUXS , 0,\n+ 0x0 }, /* LHUXS */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x200003c7, &NMD::LWUXS , 0,\n+ MIPS64_ }, /* LWUXS */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x20000447, &NMD::LWXS_32_ , 0,\n+ 0x0 }, /* LWXS[32] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x200004c7, &NMD::SWXS , 0,\n+ XMMS_ }, /* SWXS */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x20000547, &NMD::LWC1XS , 0,\n+ CP1_ }, /* LWC1XS */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x200005c7, &NMD::SWC1XS , 0,\n+ CP1_ }, /* SWC1XS */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x20000647, &NMD::LDXS , 0,\n+ MIPS64_ }, /* LDXS */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x200006c7, &NMD::SDXS , 0,\n+ MIPS64_ }, /* SDXS */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x20000747, &NMD::LDC1XS , 0,\n+ CP1_ }, /* LDC1XS */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0x200007c7, &NMD::SDC1XS , 0,\n+ CP1_ }, /* SDC1XS */\n+};\n+\n+\n+NMD::Pool NMD::P_LSX[2] = {\n+ { pool , PP_LSX , 16 , 32,\n+ 0xfc00007f, 0x20000007, 0 , 0,\n+ 0x0 }, /* PP.LSX */\n+ { pool , PP_LSXS , 16 , 32,\n+ 0xfc00007f, 0x20000047, 0 , 0,\n+ 0x0 }, /* PP.LSXS */\n+};\n+\n+\n+NMD::Pool NMD::POOL32Axf_1_0[4] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x2000007f, &NMD::MFHI_DSP_ , 0,\n+ DSP_ }, /* MFHI[DSP] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x2000107f, &NMD::MFLO_DSP_ , 0,\n+ DSP_ }, /* MFLO[DSP] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x2000207f, &NMD::MTHI_DSP_ , 0,\n+ DSP_ }, /* MTHI[DSP] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x2000307f, &NMD::MTLO_DSP_ , 0,\n+ DSP_ }, /* MTLO[DSP] */\n+};\n+\n+\n+NMD::Pool NMD::POOL32Axf_1_1[4] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x2000027f, &NMD::MTHLIP , 0,\n+ DSP_ }, /* MTHLIP */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x2000127f, &NMD::SHILOV , 0,\n+ DSP_ }, /* SHILOV */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0x2000227f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_1_1~*(2) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0x2000327f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_1_1~*(3) */\n+};\n+\n+\n+NMD::Pool NMD::POOL32Axf_1_3[4] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x2000067f, &NMD::RDDSP , 0,\n+ DSP_ }, /* RDDSP */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x2000167f, &NMD::WRDSP , 0,\n+ DSP_ }, /* WRDSP */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x2000267f, &NMD::EXTP , 0,\n+ DSP_ }, /* EXTP */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x2000367f, &NMD::EXTPDP , 0,\n+ DSP_ }, /* EXTPDP */\n+};\n+\n+\n+NMD::Pool NMD::POOL32Axf_1_4[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc001fff, 0x2000087f, &NMD::SHLL_QB , 0,\n+ DSP_ }, /* SHLL.QB */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc001fff, 0x2000187f, &NMD::SHRL_QB , 0,\n+ DSP_ }, /* SHRL.QB */\n+};\n+\n+\n+NMD::Pool NMD::MAQ_S_A__W_PHR[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x20000a7f, &NMD::MAQ_S_W_PHR , 0,\n+ DSP_ }, /* MAQ_S.W.PHR */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x20002a7f, &NMD::MAQ_SA_W_PHR , 0,\n+ DSP_ }, /* MAQ_SA.W.PHR */\n+};\n+\n+\n+NMD::Pool NMD::MAQ_S_A__W_PHL[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x20001a7f, &NMD::MAQ_S_W_PHL , 0,\n+ DSP_ }, /* MAQ_S.W.PHL */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x20003a7f, &NMD::MAQ_SA_W_PHL , 0,\n+ DSP_ }, /* MAQ_SA.W.PHL */\n+};\n+\n+\n+NMD::Pool NMD::POOL32Axf_1_5[2] = {\n+ { pool , MAQ_S_A__W_PHR , 2 , 32,\n+ 0xfc001fff, 0x20000a7f, 0 , 0,\n+ 0x0 }, /* MAQ_S[A].W.PHR */\n+ { pool , MAQ_S_A__W_PHL , 2 , 32,\n+ 0xfc001fff, 0x20001a7f, 0 , 0,\n+ 0x0 }, /* MAQ_S[A].W.PHL */\n+};\n+\n+\n+NMD::Pool NMD::POOL32Axf_1_7[4] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x20000e7f, &NMD::EXTR_W , 0,\n+ DSP_ }, /* EXTR.W */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x20001e7f, &NMD::EXTR_R_W , 0,\n+ DSP_ }, /* EXTR_R.W */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x20002e7f, &NMD::EXTR_RS_W , 0,\n+ DSP_ }, /* EXTR_RS.W */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x20003e7f, &NMD::EXTR_S_H , 0,\n+ DSP_ }, /* EXTR_S.H */\n+};\n+\n+\n+NMD::Pool NMD::POOL32Axf_1[8] = {\n+ { pool , POOL32Axf_1_0 , 4 , 32,\n+ 0xfc000fff, 0x2000007f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_1_0 */\n+ { pool , POOL32Axf_1_1 , 4 , 32,\n+ 0xfc000fff, 0x2000027f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_1_1 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000fff, 0x2000047f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_1~*(2) */\n+ { pool , POOL32Axf_1_3 , 4 , 32,\n+ 0xfc000fff, 0x2000067f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_1_3 */\n+ { pool , POOL32Axf_1_4 , 2 , 32,\n+ 0xfc000fff, 0x2000087f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_1_4 */\n+ { pool , POOL32Axf_1_5 , 2 , 32,\n+ 0xfc000fff, 0x20000a7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_1_5 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000fff, 0x20000c7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_1~*(6) */\n+ { pool , POOL32Axf_1_7 , 4 , 32,\n+ 0xfc000fff, 0x20000e7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_1_7 */\n+};\n+\n+\n+NMD::Pool NMD::POOL32Axf_2_DSP__0_7[8] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x200000bf, &NMD::DPA_W_PH , 0,\n+ DSP_ }, /* DPA.W.PH */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x200002bf, &NMD::DPAQ_S_W_PH , 0,\n+ DSP_ }, /* DPAQ_S.W.PH */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x200004bf, &NMD::DPS_W_PH , 0,\n+ DSP_ }, /* DPS.W.PH */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x200006bf, &NMD::DPSQ_S_W_PH , 0,\n+ DSP_ }, /* DPSQ_S.W.PH */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0x200008bf, 0 , 0,\n+ 0x0 }, /* POOL32Axf_2(DSP)_0_7~*(4) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x20000abf, &NMD::MADD_DSP_ , 0,\n+ DSP_ }, /* MADD[DSP] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x20000cbf, &NMD::MULT_DSP_ , 0,\n+ DSP_ }, /* MULT[DSP] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x20000ebf, &NMD::EXTRV_W , 0,\n+ DSP_ }, /* EXTRV.W */\n+};\n+\n+\n+NMD::Pool NMD::POOL32Axf_2_DSP__8_15[8] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x200010bf, &NMD::DPAX_W_PH , 0,\n+ DSP_ }, /* DPAX.W.PH */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x200012bf, &NMD::DPAQ_SA_L_W , 0,\n+ DSP_ }, /* DPAQ_SA.L.W */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x200014bf, &NMD::DPSX_W_PH , 0,\n+ DSP_ }, /* DPSX.W.PH */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x200016bf, &NMD::DPSQ_SA_L_W , 0,\n+ DSP_ }, /* DPSQ_SA.L.W */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0x200018bf, 0 , 0,\n+ 0x0 }, /* POOL32Axf_2(DSP)_8_15~*(4) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x20001abf, &NMD::MADDU_DSP_ , 0,\n+ DSP_ }, /* MADDU[DSP] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x20001cbf, &NMD::MULTU_DSP_ , 0,\n+ DSP_ }, /* MULTU[DSP] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x20001ebf, &NMD::EXTRV_R_W , 0,\n+ DSP_ }, /* EXTRV_R.W */\n+};\n+\n+\n+NMD::Pool NMD::POOL32Axf_2_DSP__16_23[8] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x200020bf, &NMD::DPAU_H_QBL , 0,\n+ DSP_ }, /* DPAU.H.QBL */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x200022bf, &NMD::DPAQX_S_W_PH , 0,\n+ DSP_ }, /* DPAQX_S.W.PH */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x200024bf, &NMD::DPSU_H_QBL , 0,\n+ DSP_ }, /* DPSU.H.QBL */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x200026bf, &NMD::DPSQX_S_W_PH , 0,\n+ DSP_ }, /* DPSQX_S.W.PH */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x200028bf, &NMD::EXTPV , 0,\n+ DSP_ }, /* EXTPV */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x20002abf, &NMD::MSUB_DSP_ , 0,\n+ DSP_ }, /* MSUB[DSP] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x20002cbf, &NMD::MULSA_W_PH , 0,\n+ DSP_ }, /* MULSA.W.PH */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x20002ebf, &NMD::EXTRV_RS_W , 0,\n+ DSP_ }, /* EXTRV_RS.W */\n+};\n+\n+\n+NMD::Pool NMD::POOL32Axf_2_DSP__24_31[8] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x200030bf, &NMD::DPAU_H_QBR , 0,\n+ DSP_ }, /* DPAU.H.QBR */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x200032bf, &NMD::DPAQX_SA_W_PH , 0,\n+ DSP_ }, /* DPAQX_SA.W.PH */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x200034bf, &NMD::DPSU_H_QBR , 0,\n+ DSP_ }, /* DPSU.H.QBR */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x200036bf, &NMD::DPSQX_SA_W_PH , 0,\n+ DSP_ }, /* DPSQX_SA.W.PH */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x200038bf, &NMD::EXTPDPV , 0,\n+ DSP_ }, /* EXTPDPV */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x20003abf, &NMD::MSUBU_DSP_ , 0,\n+ DSP_ }, /* MSUBU[DSP] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x20003cbf, &NMD::MULSAQ_S_W_PH , 0,\n+ DSP_ }, /* MULSAQ_S.W.PH */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0x20003ebf, &NMD::EXTRV_S_H , 0,\n+ DSP_ }, /* EXTRV_S.H */\n+};\n+\n+\n+NMD::Pool NMD::POOL32Axf_2[4] = {\n+ { pool , POOL32Axf_2_DSP__0_7, 8 , 32,\n+ 0xfc0031ff, 0x200000bf, 0 , 0,\n+ 0x0 }, /* POOL32Axf_2(DSP)_0_7 */\n+ { pool , POOL32Axf_2_DSP__8_15, 8 , 32,\n+ 0xfc0031ff, 0x200010bf, 0 , 0,\n+ 0x0 }, /* POOL32Axf_2(DSP)_8_15 */\n+ { pool , POOL32Axf_2_DSP__16_23, 8 , 32,\n+ 0xfc0031ff, 0x200020bf, 0 , 0,\n+ 0x0 }, /* POOL32Axf_2(DSP)_16_23 */\n+ { pool , POOL32Axf_2_DSP__24_31, 8 , 32,\n+ 0xfc0031ff, 0x200030bf, 0 , 0,\n+ 0x0 }, /* POOL32Axf_2(DSP)_24_31 */\n+};\n+\n+\n+NMD::Pool NMD::POOL32Axf_4[128] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000013f, &NMD::ABSQ_S_QB , 0,\n+ DSP_ }, /* ABSQ_S.QB */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000033f, &NMD::REPLV_PH , 0,\n+ DSP_ }, /* REPLV.PH */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000053f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(2) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000073f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(3) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000093f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(4) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20000b3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(5) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20000d3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(6) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20000f3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(7) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000113f, &NMD::ABSQ_S_PH , 0,\n+ DSP_ }, /* ABSQ_S.PH */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000133f, &NMD::REPLV_QB , 0,\n+ DSP_ }, /* REPLV.QB */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000153f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(10) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000173f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(11) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000193f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(12) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20001b3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(13) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20001d3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(14) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20001f3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(15) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000213f, &NMD::ABSQ_S_W , 0,\n+ DSP_ }, /* ABSQ_S.W */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000233f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(17) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000253f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(18) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000273f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(19) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000293f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(20) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20002b3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(21) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20002d3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(22) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20002f3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(23) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000313f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(24) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000333f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(25) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000353f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(26) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000373f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(27) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000393f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(28) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20003b3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(29) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20003d3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(30) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20003f3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(31) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000413f, &NMD::INSV , 0,\n+ DSP_ }, /* INSV */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000433f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(33) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000453f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(34) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000473f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(35) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000493f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(36) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20004b3f, &NMD::CLO , 0,\n+ XMMS_ }, /* CLO */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20004d3f, &NMD::MFC2 , 0,\n+ CP2_ }, /* MFC2 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20004f3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(39) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000513f, &NMD::PRECEQ_W_PHL , 0,\n+ DSP_ }, /* PRECEQ.W.PHL */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000533f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(41) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000553f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(42) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000573f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(43) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000593f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(44) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20005b3f, &NMD::CLZ , 0,\n+ XMMS_ }, /* CLZ */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20005d3f, &NMD::MTC2 , 0,\n+ CP2_ }, /* MTC2 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20005f3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(47) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000613f, &NMD::PRECEQ_W_PHR , 0,\n+ DSP_ }, /* PRECEQ.W.PHR */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000633f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(49) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000653f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(50) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000673f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(51) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000693f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(52) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20006b3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(53) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20006d3f, &NMD::DMFC2 , 0,\n+ CP2_ }, /* DMFC2 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20006f3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(55) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000713f, &NMD::PRECEQU_PH_QBL , 0,\n+ DSP_ }, /* PRECEQU.PH.QBL */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000733f, &NMD::PRECEQU_PH_QBLA , 0,\n+ DSP_ }, /* PRECEQU.PH.QBLA */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000753f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(58) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000773f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(59) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000793f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(60) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20007b3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(61) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20007d3f, &NMD::DMTC2 , 0,\n+ CP2_ }, /* DMTC2 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20007f3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(63) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000813f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(64) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000833f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(65) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000853f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(66) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000873f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(67) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000893f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(68) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20008b3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(69) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20008d3f, &NMD::MFHC2 , 0,\n+ CP2_ }, /* MFHC2 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20008f3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(71) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000913f, &NMD::PRECEQU_PH_QBR , 0,\n+ DSP_ }, /* PRECEQU.PH.QBR */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000933f, &NMD::PRECEQU_PH_QBRA , 0,\n+ DSP_ }, /* PRECEQU.PH.QBRA */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000953f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(74) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000973f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(75) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000993f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(76) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20009b3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(77) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20009d3f, &NMD::MTHC2 , 0,\n+ CP2_ }, /* MTHC2 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20009f3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(79) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000a13f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(80) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000a33f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(81) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000a53f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(82) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000a73f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(83) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000a93f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(84) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000ab3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(85) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000ad3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(86) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000af3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(87) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000b13f, &NMD::PRECEU_PH_QBL , 0,\n+ DSP_ }, /* PRECEU.PH.QBL */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000b33f, &NMD::PRECEU_PH_QBLA , 0,\n+ DSP_ }, /* PRECEU.PH.QBLA */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000b53f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(90) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000b73f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(91) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000b93f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(92) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000bb3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(93) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000bd3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(94) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000bf3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(95) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000c13f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(96) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000c33f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(97) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000c53f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(98) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000c73f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(99) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000c93f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(100) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000cb3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(101) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000cd3f, &NMD::CFC2 , 0,\n+ CP2_ }, /* CFC2 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000cf3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(103) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000d13f, &NMD::PRECEU_PH_QBR , 0,\n+ DSP_ }, /* PRECEU.PH.QBR */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000d33f, &NMD::PRECEU_PH_QBRA , 0,\n+ DSP_ }, /* PRECEU.PH.QBRA */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000d53f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(106) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000d73f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(107) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000d93f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(108) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000db3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(109) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000dd3f, &NMD::CTC2 , 0,\n+ CP2_ }, /* CTC2 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000df3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(111) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000e13f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(112) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000e33f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(113) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000e53f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(114) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000e73f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(115) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000e93f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(116) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000eb3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(117) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000ed3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(118) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000ef3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(119) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000f13f, &NMD::RADDU_W_QB , 0,\n+ DSP_ }, /* RADDU.W.QB */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000f33f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(121) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000f53f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(122) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000f73f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(123) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000f93f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(124) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000fb3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(125) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000fd3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(126) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000ff3f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4~*(127) */\n+};\n+\n+\n+NMD::Pool NMD::POOL32Axf_5_group0[32] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000017f, &NMD::TLBGP , 0,\n+ CP0_ | VZ_ | TLB_ }, /* TLBGP */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000037f, &NMD::TLBP , 0,\n+ CP0_ | TLB_ }, /* TLBP */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000057f, &NMD::TLBGINV , 0,\n+ CP0_ | VZ_ | TLB_ | TLBINV_}, /* TLBGINV */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000077f, &NMD::TLBINV , 0,\n+ CP0_ | TLB_ | TLBINV_}, /* TLBINV */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000097f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group0~*(4) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20000b7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group0~*(5) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20000d7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group0~*(6) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20000f7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group0~*(7) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000117f, &NMD::TLBGR , 0,\n+ CP0_ | VZ_ | TLB_ }, /* TLBGR */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000137f, &NMD::TLBR , 0,\n+ CP0_ | TLB_ }, /* TLBR */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000157f, &NMD::TLBGINVF , 0,\n+ CP0_ | VZ_ | TLB_ | TLBINV_}, /* TLBGINVF */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000177f, &NMD::TLBINVF , 0,\n+ CP0_ | TLB_ | TLBINV_}, /* TLBINVF */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000197f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group0~*(12) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20001b7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group0~*(13) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20001d7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group0~*(14) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20001f7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group0~*(15) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000217f, &NMD::TLBGWI , 0,\n+ CP0_ | VZ_ | TLB_ }, /* TLBGWI */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000237f, &NMD::TLBWI , 0,\n+ CP0_ | TLB_ }, /* TLBWI */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000257f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group0~*(18) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000277f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group0~*(19) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000297f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group0~*(20) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20002b7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group0~*(21) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20002d7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group0~*(22) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20002f7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group0~*(23) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000317f, &NMD::TLBGWR , 0,\n+ CP0_ | VZ_ | TLB_ }, /* TLBGWR */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000337f, &NMD::TLBWR , 0,\n+ CP0_ | TLB_ }, /* TLBWR */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000357f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group0~*(26) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000377f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group0~*(27) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000397f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group0~*(28) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20003b7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group0~*(29) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20003d7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group0~*(30) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20003f7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group0~*(31) */\n+};\n+\n+\n+NMD::Pool NMD::POOL32Axf_5_group1[32] = {\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000417f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group1~*(0) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000437f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group1~*(1) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000457f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group1~*(2) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000477f, &NMD::DI , 0,\n+ 0x0 }, /* DI */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000497f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group1~*(4) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20004b7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group1~*(5) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20004d7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group1~*(6) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20004f7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group1~*(7) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000517f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group1~*(8) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000537f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group1~*(9) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000557f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group1~*(10) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000577f, &NMD::EI , 0,\n+ 0x0 }, /* EI */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000597f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group1~*(12) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20005b7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group1~*(13) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20005d7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group1~*(14) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20005f7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group1~*(15) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000617f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group1~*(16) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000637f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group1~*(17) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000657f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group1~*(18) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000677f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group1~*(19) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000697f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group1~*(20) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20006b7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group1~*(21) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20006d7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group1~*(22) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20006f7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group1~*(23) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000717f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group1~*(24) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000737f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group1~*(25) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000757f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group1~*(26) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000777f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group1~*(27) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000797f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group1~*(28) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20007b7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group1~*(29) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20007d7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group1~*(30) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x20007f7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group1~*(31) */\n+};\n+\n+\n+NMD::Pool NMD::ERETx[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc01ffff, 0x2000f37f, &NMD::ERET , 0,\n+ 0x0 }, /* ERET */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc01ffff, 0x2001f37f, &NMD::ERETNC , 0,\n+ 0x0 }, /* ERETNC */\n+};\n+\n+\n+NMD::Pool NMD::POOL32Axf_5_group3[32] = {\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000c17f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group3~*(0) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000c37f, &NMD::WAIT , 0,\n+ 0x0 }, /* WAIT */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000c57f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group3~*(2) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000c77f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group3~*(3) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000c97f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group3~*(4) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000cb7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group3~*(5) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000cd7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group3~*(6) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000cf7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group3~*(7) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000d17f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group3~*(8) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000d37f, &NMD::IRET , 0,\n+ MCU_ }, /* IRET */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000d57f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group3~*(10) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000d77f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group3~*(11) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000d97f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group3~*(12) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000db7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group3~*(13) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000dd7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group3~*(14) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000df7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group3~*(15) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000e17f, &NMD::RDPGPR , 0,\n+ CP0_ }, /* RDPGPR */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000e37f, &NMD::DERET , 0,\n+ EJTAG_ }, /* DERET */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000e57f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group3~*(18) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000e77f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group3~*(19) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000e97f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group3~*(20) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000eb7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group3~*(21) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000ed7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group3~*(22) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000ef7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group3~*(23) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000f17f, &NMD::WRPGPR , 0,\n+ CP0_ }, /* WRPGPR */\n+ { pool , ERETx , 2 , 32,\n+ 0xfc00ffff, 0x2000f37f, 0 , 0,\n+ 0x0 }, /* ERETx */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000f57f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group3~*(26) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000f77f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group3~*(27) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000f97f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group3~*(28) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000fb7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group3~*(29) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000fd7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group3~*(30) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0x2000ff7f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group3~*(31) */\n+};\n+\n+\n+NMD::Pool NMD::POOL32Axf_5[4] = {\n+ { pool , POOL32Axf_5_group0 , 32 , 32,\n+ 0xfc00c1ff, 0x2000017f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group0 */\n+ { pool , POOL32Axf_5_group1 , 32 , 32,\n+ 0xfc00c1ff, 0x2000417f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group1 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00c1ff, 0x2000817f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5~*(2) */\n+ { pool , POOL32Axf_5_group3 , 32 , 32,\n+ 0xfc00c1ff, 0x2000c17f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5_group3 */\n+};\n+\n+\n+NMD::Pool NMD::SHRA__R__QB[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc001fff, 0x200001ff, &NMD::SHRA_QB , 0,\n+ DSP_ }, /* SHRA.QB */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc001fff, 0x200011ff, &NMD::SHRA_R_QB , 0,\n+ DSP_ }, /* SHRA_R.QB */\n+};\n+\n+\n+NMD::Pool NMD::POOL32Axf_7[8] = {\n+ { pool , SHRA__R__QB , 2 , 32,\n+ 0xfc000fff, 0x200001ff, 0 , 0,\n+ 0x0 }, /* SHRA[_R].QB */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc000fff, 0x200003ff, &NMD::SHRL_PH , 0,\n+ DSP_ }, /* SHRL.PH */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc000fff, 0x200005ff, &NMD::REPL_QB , 0,\n+ DSP_ }, /* REPL.QB */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000fff, 0x200007ff, 0 , 0,\n+ 0x0 }, /* POOL32Axf_7~*(3) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000fff, 0x200009ff, 0 , 0,\n+ 0x0 }, /* POOL32Axf_7~*(4) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000fff, 0x20000bff, 0 , 0,\n+ 0x0 }, /* POOL32Axf_7~*(5) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000fff, 0x20000dff, 0 , 0,\n+ 0x0 }, /* POOL32Axf_7~*(6) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000fff, 0x20000fff, 0 , 0,\n+ 0x0 }, /* POOL32Axf_7~*(7) */\n+};\n+\n+\n+NMD::Pool NMD::POOL32Axf[8] = {\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0x2000003f, 0 , 0,\n+ 0x0 }, /* POOL32Axf~*(0) */\n+ { pool , POOL32Axf_1 , 8 , 32,\n+ 0xfc0001ff, 0x2000007f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_1 */\n+ { pool , POOL32Axf_2 , 4 , 32,\n+ 0xfc0001ff, 0x200000bf, 0 , 0,\n+ 0x0 }, /* POOL32Axf_2 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0x200000ff, 0 , 0,\n+ 0x0 }, /* POOL32Axf~*(3) */\n+ { pool , POOL32Axf_4 , 128 , 32,\n+ 0xfc0001ff, 0x2000013f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_4 */\n+ { pool , POOL32Axf_5 , 4 , 32,\n+ 0xfc0001ff, 0x2000017f, 0 , 0,\n+ 0x0 }, /* POOL32Axf_5 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0x200001bf, 0 , 0,\n+ 0x0 }, /* POOL32Axf~*(6) */\n+ { pool , POOL32Axf_7 , 8 , 32,\n+ 0xfc0001ff, 0x200001ff, 0 , 0,\n+ 0x0 }, /* POOL32Axf_7 */\n+};\n+\n+\n+NMD::Pool NMD::_POOL32A7[8] = {\n+ { pool , P_LSX , 2 , 32,\n+ 0xfc00003f, 0x20000007, 0 , 0,\n+ 0x0 }, /* P.LSX */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00003f, 0x2000000f, &NMD::LSA , 0,\n+ 0x0 }, /* LSA */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00003f, 0x20000017, 0 , 0,\n+ 0x0 }, /* _POOL32A7~*(2) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00003f, 0x2000001f, &NMD::EXTW , 0,\n+ 0x0 }, /* EXTW */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00003f, 0x20000027, 0 , 0,\n+ 0x0 }, /* _POOL32A7~*(4) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00003f, 0x2000002f, 0 , 0,\n+ 0x0 }, /* _POOL32A7~*(5) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00003f, 0x20000037, 0 , 0,\n+ 0x0 }, /* _POOL32A7~*(6) */\n+ { pool , POOL32Axf , 8 , 32,\n+ 0xfc00003f, 0x2000003f, 0 , 0,\n+ 0x0 }, /* POOL32Axf */\n+};\n+\n+\n+NMD::Pool NMD::P32A[8] = {\n+ { pool , _POOL32A0 , 128 , 32,\n+ 0xfc000007, 0x20000000, 0 , 0,\n+ 0x0 }, /* _POOL32A0 */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc000007, 0x20000001, &NMD::SPECIAL2 , 0,\n+ UDI_ }, /* SPECIAL2 */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc000007, 0x20000002, &NMD::COP2_1 , 0,\n+ CP2_ }, /* COP2_1 */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc000007, 0x20000003, &NMD::UDI , 0,\n+ UDI_ }, /* UDI */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000007, 0x20000004, 0 , 0,\n+ 0x0 }, /* P32A~*(4) */\n+ { pool , _POOL32A5 , 128 , 32,\n+ 0xfc000007, 0x20000005, 0 , 0,\n+ 0x0 }, /* _POOL32A5 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000007, 0x20000006, 0 , 0,\n+ 0x0 }, /* P32A~*(6) */\n+ { pool , _POOL32A7 , 8 , 32,\n+ 0xfc000007, 0x20000007, 0 , 0,\n+ 0x0 }, /* _POOL32A7 */\n+};\n+\n+\n+NMD::Pool NMD::P_GP_D[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc000007, 0x40000001, &NMD::LD_GP_ , 0,\n+ MIPS64_ }, /* LD[GP] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc000007, 0x40000005, &NMD::SD_GP_ , 0,\n+ MIPS64_ }, /* SD[GP] */\n+};\n+\n+\n+NMD::Pool NMD::P_GP_W[4] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc000003, 0x40000000, &NMD::ADDIU_GP_W_ , 0,\n+ 0x0 }, /* ADDIU[GP.W] */\n+ { pool , P_GP_D , 2 , 32,\n+ 0xfc000003, 0x40000001, 0 , 0,\n+ 0x0 }, /* P.GP.D */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc000003, 0x40000002, &NMD::LW_GP_ , 0,\n+ 0x0 }, /* LW[GP] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc000003, 0x40000003, &NMD::SW_GP_ , 0,\n+ 0x0 }, /* SW[GP] */\n+};\n+\n+\n+NMD::Pool NMD::POOL48I[32] = {\n+ { instruction , 0 , 0 , 48,\n+ 0xfc1f00000000ull, 0x600000000000ull, &NMD::LI_48_ , 0,\n+ XMMS_ }, /* LI[48] */\n+ { instruction , 0 , 0 , 48,\n+ 0xfc1f00000000ull, 0x600100000000ull, &NMD::ADDIU_48_ , 0,\n+ XMMS_ }, /* ADDIU[48] */\n+ { instruction , 0 , 0 , 48,\n+ 0xfc1f00000000ull, 0x600200000000ull, &NMD::ADDIU_GP48_ , 0,\n+ XMMS_ }, /* ADDIU[GP48] */\n+ { instruction , 0 , 0 , 48,\n+ 0xfc1f00000000ull, 0x600300000000ull, &NMD::ADDIUPC_48_ , 0,\n+ XMMS_ }, /* ADDIUPC[48] */\n+ { reserved_block , 0 , 0 , 48,\n+ 0xfc1f00000000ull, 0x600400000000ull, 0 , 0,\n+ 0x0 }, /* POOL48I~*(4) */\n+ { reserved_block , 0 , 0 , 48,\n+ 0xfc1f00000000ull, 0x600500000000ull, 0 , 0,\n+ 0x0 }, /* POOL48I~*(5) */\n+ { reserved_block , 0 , 0 , 48,\n+ 0xfc1f00000000ull, 0x600600000000ull, 0 , 0,\n+ 0x0 }, /* POOL48I~*(6) */\n+ { reserved_block , 0 , 0 , 48,\n+ 0xfc1f00000000ull, 0x600700000000ull, 0 , 0,\n+ 0x0 }, /* POOL48I~*(7) */\n+ { reserved_block , 0 , 0 , 48,\n+ 0xfc1f00000000ull, 0x600800000000ull, 0 , 0,\n+ 0x0 }, /* POOL48I~*(8) */\n+ { reserved_block , 0 , 0 , 48,\n+ 0xfc1f00000000ull, 0x600900000000ull, 0 , 0,\n+ 0x0 }, /* POOL48I~*(9) */\n+ { reserved_block , 0 , 0 , 48,\n+ 0xfc1f00000000ull, 0x600a00000000ull, 0 , 0,\n+ 0x0 }, /* POOL48I~*(10) */\n+ { instruction , 0 , 0 , 48,\n+ 0xfc1f00000000ull, 0x600b00000000ull, &NMD::LWPC_48_ , 0,\n+ XMMS_ }, /* LWPC[48] */\n+ { reserved_block , 0 , 0 , 48,\n+ 0xfc1f00000000ull, 0x600c00000000ull, 0 , 0,\n+ 0x0 }, /* POOL48I~*(12) */\n+ { reserved_block , 0 , 0 , 48,\n+ 0xfc1f00000000ull, 0x600d00000000ull, 0 , 0,\n+ 0x0 }, /* POOL48I~*(13) */\n+ { reserved_block , 0 , 0 , 48,\n+ 0xfc1f00000000ull, 0x600e00000000ull, 0 , 0,\n+ 0x0 }, /* POOL48I~*(14) */\n+ { instruction , 0 , 0 , 48,\n+ 0xfc1f00000000ull, 0x600f00000000ull, &NMD::SWPC_48_ , 0,\n+ XMMS_ }, /* SWPC[48] */\n+ { reserved_block , 0 , 0 , 48,\n+ 0xfc1f00000000ull, 0x601000000000ull, 0 , 0,\n+ 0x0 }, /* POOL48I~*(16) */\n+ { instruction , 0 , 0 , 48,\n+ 0xfc1f00000000ull, 0x601100000000ull, &NMD::DADDIU_48_ , 0,\n+ MIPS64_ }, /* DADDIU[48] */\n+ { reserved_block , 0 , 0 , 48,\n+ 0xfc1f00000000ull, 0x601200000000ull, 0 , 0,\n+ 0x0 }, /* POOL48I~*(18) */\n+ { reserved_block , 0 , 0 , 48,\n+ 0xfc1f00000000ull, 0x601300000000ull, 0 , 0,\n+ 0x0 }, /* POOL48I~*(19) */\n+ { instruction , 0 , 0 , 48,\n+ 0xfc1f00000000ull, 0x601400000000ull, &NMD::DLUI_48_ , 0,\n+ MIPS64_ }, /* DLUI[48] */\n+ { reserved_block , 0 , 0 , 48,\n+ 0xfc1f00000000ull, 0x601500000000ull, 0 , 0,\n+ 0x0 }, /* POOL48I~*(21) */\n+ { reserved_block , 0 , 0 , 48,\n+ 0xfc1f00000000ull, 0x601600000000ull, 0 , 0,\n+ 0x0 }, /* POOL48I~*(22) */\n+ { reserved_block , 0 , 0 , 48,\n+ 0xfc1f00000000ull, 0x601700000000ull, 0 , 0,\n+ 0x0 }, /* POOL48I~*(23) */\n+ { reserved_block , 0 , 0 , 48,\n+ 0xfc1f00000000ull, 0x601800000000ull, 0 , 0,\n+ 0x0 }, /* POOL48I~*(24) */\n+ { reserved_block , 0 , 0 , 48,\n+ 0xfc1f00000000ull, 0x601900000000ull, 0 , 0,\n+ 0x0 }, /* POOL48I~*(25) */\n+ { reserved_block , 0 , 0 , 48,\n+ 0xfc1f00000000ull, 0x601a00000000ull, 0 , 0,\n+ 0x0 }, /* POOL48I~*(26) */\n+ { instruction , 0 , 0 , 48,\n+ 0xfc1f00000000ull, 0x601b00000000ull, &NMD::LDPC_48_ , 0,\n+ MIPS64_ }, /* LDPC[48] */\n+ { reserved_block , 0 , 0 , 48,\n+ 0xfc1f00000000ull, 0x601c00000000ull, 0 , 0,\n+ 0x0 }, /* POOL48I~*(28) */\n+ { reserved_block , 0 , 0 , 48,\n+ 0xfc1f00000000ull, 0x601d00000000ull, 0 , 0,\n+ 0x0 }, /* POOL48I~*(29) */\n+ { reserved_block , 0 , 0 , 48,\n+ 0xfc1f00000000ull, 0x601e00000000ull, 0 , 0,\n+ 0x0 }, /* POOL48I~*(30) */\n+ { instruction , 0 , 0 , 48,\n+ 0xfc1f00000000ull, 0x601f00000000ull, &NMD::SDPC_48_ , 0,\n+ MIPS64_ }, /* SDPC[48] */\n+};\n+\n+\n+NMD::Pool NMD::PP_SR[4] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc10f003, 0x80003000, &NMD::SAVE_32_ , 0,\n+ 0x0 }, /* SAVE[32] */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc10f003, 0x80003001, 0 , 0,\n+ 0x0 }, /* PP.SR~*(1) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc10f003, 0x80003002, &NMD::RESTORE_32_ , 0,\n+ 0x0 }, /* RESTORE[32] */\n+ { return_instruction , 0 , 0 , 32,\n+ 0xfc10f003, 0x80003003, &NMD::RESTORE_JRC_32_ , 0,\n+ 0x0 }, /* RESTORE.JRC[32] */\n+};\n+\n+\n+NMD::Pool NMD::P_SR_F[8] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc10f007, 0x80103000, &NMD::SAVEF , 0,\n+ CP1_ }, /* SAVEF */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc10f007, 0x80103001, &NMD::RESTOREF , 0,\n+ CP1_ }, /* RESTOREF */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc10f007, 0x80103002, 0 , 0,\n+ 0x0 }, /* P.SR.F~*(2) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc10f007, 0x80103003, 0 , 0,\n+ 0x0 }, /* P.SR.F~*(3) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc10f007, 0x80103004, 0 , 0,\n+ 0x0 }, /* P.SR.F~*(4) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc10f007, 0x80103005, 0 , 0,\n+ 0x0 }, /* P.SR.F~*(5) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc10f007, 0x80103006, 0 , 0,\n+ 0x0 }, /* P.SR.F~*(6) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc10f007, 0x80103007, 0 , 0,\n+ 0x0 }, /* P.SR.F~*(7) */\n+};\n+\n+\n+NMD::Pool NMD::P_SR[2] = {\n+ { pool , PP_SR , 4 , 32,\n+ 0xfc10f000, 0x80003000, 0 , 0,\n+ 0x0 }, /* PP.SR */\n+ { pool , P_SR_F , 8 , 32,\n+ 0xfc10f000, 0x80103000, 0 , 0,\n+ 0x0 }, /* P.SR.F */\n+};\n+\n+\n+NMD::Pool NMD::P_SLL[5] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xffe0f1ff, 0x8000c000, &NMD::NOP_32_ , 0,\n+ 0x0 }, /* NOP[32] */\n+ { instruction , 0 , 0 , 32,\n+ 0xffe0f1ff, 0x8000c003, &NMD::EHB , 0,\n+ 0x0 }, /* EHB */\n+ { instruction , 0 , 0 , 32,\n+ 0xffe0f1ff, 0x8000c005, &NMD::PAUSE , 0,\n+ 0x0 }, /* PAUSE */\n+ { instruction , 0 , 0 , 32,\n+ 0xffe0f1ff, 0x8000c006, &NMD::SYNC , 0,\n+ 0x0 }, /* SYNC */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f1e0, 0x8000c000, &NMD::SLL_32_ , 0,\n+ 0x0 }, /* SLL[32] */\n+};\n+\n+\n+NMD::Pool NMD::P_SHIFT[16] = {\n+ { pool , P_SLL , 5 , 32,\n+ 0xfc00f1e0, 0x8000c000, 0 , 0,\n+ 0x0 }, /* P.SLL */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00f1e0, 0x8000c020, 0 , 0,\n+ 0x0 }, /* P.SHIFT~*(1) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f1e0, 0x8000c040, &NMD::SRL_32_ , 0,\n+ 0x0 }, /* SRL[32] */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00f1e0, 0x8000c060, 0 , 0,\n+ 0x0 }, /* P.SHIFT~*(3) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f1e0, 0x8000c080, &NMD::SRA , 0,\n+ 0x0 }, /* SRA */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00f1e0, 0x8000c0a0, 0 , 0,\n+ 0x0 }, /* P.SHIFT~*(5) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f1e0, 0x8000c0c0, &NMD::ROTR , 0,\n+ 0x0 }, /* ROTR */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00f1e0, 0x8000c0e0, 0 , 0,\n+ 0x0 }, /* P.SHIFT~*(7) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f1e0, 0x8000c100, &NMD::DSLL , 0,\n+ MIPS64_ }, /* DSLL */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f1e0, 0x8000c120, &NMD::DSLL32 , 0,\n+ MIPS64_ }, /* DSLL32 */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f1e0, 0x8000c140, &NMD::DSRL , 0,\n+ MIPS64_ }, /* DSRL */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f1e0, 0x8000c160, &NMD::DSRL32 , 0,\n+ MIPS64_ }, /* DSRL32 */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f1e0, 0x8000c180, &NMD::DSRA , 0,\n+ MIPS64_ }, /* DSRA */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f1e0, 0x8000c1a0, &NMD::DSRA32 , 0,\n+ MIPS64_ }, /* DSRA32 */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f1e0, 0x8000c1c0, &NMD::DROTR , 0,\n+ MIPS64_ }, /* DROTR */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f1e0, 0x8000c1e0, &NMD::DROTR32 , 0,\n+ MIPS64_ }, /* DROTR32 */\n+};\n+\n+\n+NMD::Pool NMD::P_ROTX[4] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f820, 0x8000d000, &NMD::ROTX , 0,\n+ XMMS_ }, /* ROTX */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00f820, 0x8000d020, 0 , 0,\n+ 0x0 }, /* P.ROTX~*(1) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00f820, 0x8000d800, 0 , 0,\n+ 0x0 }, /* P.ROTX~*(2) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00f820, 0x8000d820, 0 , 0,\n+ 0x0 }, /* P.ROTX~*(3) */\n+};\n+\n+\n+NMD::Pool NMD::P_INS[4] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f820, 0x8000e000, &NMD::INS , 0,\n+ XMMS_ }, /* INS */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f820, 0x8000e020, &NMD::DINSU , 0,\n+ MIPS64_ }, /* DINSU */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f820, 0x8000e800, &NMD::DINSM , 0,\n+ MIPS64_ }, /* DINSM */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f820, 0x8000e820, &NMD::DINS , 0,\n+ MIPS64_ }, /* DINS */\n+};\n+\n+\n+NMD::Pool NMD::P_EXT[4] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f820, 0x8000f000, &NMD::EXT , 0,\n+ XMMS_ }, /* EXT */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f820, 0x8000f020, &NMD::DEXTU , 0,\n+ MIPS64_ }, /* DEXTU */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f820, 0x8000f800, &NMD::DEXTM , 0,\n+ MIPS64_ }, /* DEXTM */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f820, 0x8000f820, &NMD::DEXT , 0,\n+ MIPS64_ }, /* DEXT */\n+};\n+\n+\n+NMD::Pool NMD::P_U12[16] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f000, 0x80000000, &NMD::ORI , 0,\n+ 0x0 }, /* ORI */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f000, 0x80001000, &NMD::XORI , 0,\n+ 0x0 }, /* XORI */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f000, 0x80002000, &NMD::ANDI_32_ , 0,\n+ 0x0 }, /* ANDI[32] */\n+ { pool , P_SR , 2 , 32,\n+ 0xfc00f000, 0x80003000, 0 , 0,\n+ 0x0 }, /* P.SR */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f000, 0x80004000, &NMD::SLTI , 0,\n+ 0x0 }, /* SLTI */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f000, 0x80005000, &NMD::SLTIU , 0,\n+ 0x0 }, /* SLTIU */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f000, 0x80006000, &NMD::SEQI , 0,\n+ 0x0 }, /* SEQI */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00f000, 0x80007000, 0 , 0,\n+ 0x0 }, /* P.U12~*(7) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f000, 0x80008000, &NMD::ADDIU_NEG_ , 0,\n+ 0x0 }, /* ADDIU[NEG] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f000, 0x80009000, &NMD::DADDIU_U12_ , 0,\n+ MIPS64_ }, /* DADDIU[U12] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f000, 0x8000a000, &NMD::DADDIU_NEG_ , 0,\n+ MIPS64_ }, /* DADDIU[NEG] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f000, 0x8000b000, &NMD::DROTX , 0,\n+ MIPS64_ }, /* DROTX */\n+ { pool , P_SHIFT , 16 , 32,\n+ 0xfc00f000, 0x8000c000, 0 , 0,\n+ 0x0 }, /* P.SHIFT */\n+ { pool , P_ROTX , 4 , 32,\n+ 0xfc00f000, 0x8000d000, 0 , 0,\n+ 0x0 }, /* P.ROTX */\n+ { pool , P_INS , 4 , 32,\n+ 0xfc00f000, 0x8000e000, 0 , 0,\n+ 0x0 }, /* P.INS */\n+ { pool , P_EXT , 4 , 32,\n+ 0xfc00f000, 0x8000f000, 0 , 0,\n+ 0x0 }, /* P.EXT */\n+};\n+\n+\n+NMD::Pool NMD::RINT_fmt[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0xa0000020, &NMD::RINT_S , 0,\n+ CP1_ }, /* RINT.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0xa0000220, &NMD::RINT_D , 0,\n+ CP1_ }, /* RINT.D */\n+};\n+\n+\n+NMD::Pool NMD::ADD_fmt0[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0xa0000030, &NMD::ADD_S , 0,\n+ CP1_ }, /* ADD.S */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0xa0000230, 0 , 0,\n+ CP1_ }, /* ADD.fmt0~*(1) */\n+};\n+\n+\n+NMD::Pool NMD::SELEQZ_fmt[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0xa0000038, &NMD::SELEQZ_S , 0,\n+ CP1_ }, /* SELEQZ.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0xa0000238, &NMD::SELEQZ_D , 0,\n+ CP1_ }, /* SELEQZ.D */\n+};\n+\n+\n+NMD::Pool NMD::CLASS_fmt[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0xa0000060, &NMD::CLASS_S , 0,\n+ CP1_ }, /* CLASS.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0xa0000260, &NMD::CLASS_D , 0,\n+ CP1_ }, /* CLASS.D */\n+};\n+\n+\n+NMD::Pool NMD::SUB_fmt0[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0xa0000070, &NMD::SUB_S , 0,\n+ CP1_ }, /* SUB.S */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0xa0000270, 0 , 0,\n+ CP1_ }, /* SUB.fmt0~*(1) */\n+};\n+\n+\n+NMD::Pool NMD::SELNEZ_fmt[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0xa0000078, &NMD::SELNEZ_S , 0,\n+ CP1_ }, /* SELNEZ.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0xa0000278, &NMD::SELNEZ_D , 0,\n+ CP1_ }, /* SELNEZ.D */\n+};\n+\n+\n+NMD::Pool NMD::MUL_fmt0[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0xa00000b0, &NMD::MUL_S , 0,\n+ CP1_ }, /* MUL.S */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0xa00002b0, 0 , 0,\n+ CP1_ }, /* MUL.fmt0~*(1) */\n+};\n+\n+\n+NMD::Pool NMD::SEL_fmt[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0xa00000b8, &NMD::SEL_S , 0,\n+ CP1_ }, /* SEL.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0xa00002b8, &NMD::SEL_D , 0,\n+ CP1_ }, /* SEL.D */\n+};\n+\n+\n+NMD::Pool NMD::DIV_fmt0[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0xa00000f0, &NMD::DIV_S , 0,\n+ CP1_ }, /* DIV.S */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0xa00002f0, 0 , 0,\n+ CP1_ }, /* DIV.fmt0~*(1) */\n+};\n+\n+\n+NMD::Pool NMD::ADD_fmt1[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0xa0000130, &NMD::ADD_D , 0,\n+ CP1_ }, /* ADD.D */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0xa0000330, 0 , 0,\n+ CP1_ }, /* ADD.fmt1~*(1) */\n+};\n+\n+\n+NMD::Pool NMD::SUB_fmt1[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0xa0000170, &NMD::SUB_D , 0,\n+ CP1_ }, /* SUB.D */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0xa0000370, 0 , 0,\n+ CP1_ }, /* SUB.fmt1~*(1) */\n+};\n+\n+\n+NMD::Pool NMD::MUL_fmt1[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0xa00001b0, &NMD::MUL_D , 0,\n+ CP1_ }, /* MUL.D */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0xa00003b0, 0 , 0,\n+ CP1_ }, /* MUL.fmt1~*(1) */\n+};\n+\n+\n+NMD::Pool NMD::MADDF_fmt[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0xa00001b8, &NMD::MADDF_S , 0,\n+ CP1_ }, /* MADDF.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0xa00003b8, &NMD::MADDF_D , 0,\n+ CP1_ }, /* MADDF.D */\n+};\n+\n+\n+NMD::Pool NMD::DIV_fmt1[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0xa00001f0, &NMD::DIV_D , 0,\n+ CP1_ }, /* DIV.D */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0003ff, 0xa00003f0, 0 , 0,\n+ CP1_ }, /* DIV.fmt1~*(1) */\n+};\n+\n+\n+NMD::Pool NMD::MSUBF_fmt[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0xa00001f8, &NMD::MSUBF_S , 0,\n+ CP1_ }, /* MSUBF.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0003ff, 0xa00003f8, &NMD::MSUBF_D , 0,\n+ CP1_ }, /* MSUBF.D */\n+};\n+\n+\n+NMD::Pool NMD::POOL32F_0[64] = {\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa0000000, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(0) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa0000008, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(1) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa0000010, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(2) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa0000018, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(3) */\n+ { pool , RINT_fmt , 2 , 32,\n+ 0xfc0001ff, 0xa0000020, 0 , 0,\n+ CP1_ }, /* RINT.fmt */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa0000028, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(5) */\n+ { pool , ADD_fmt0 , 2 , 32,\n+ 0xfc0001ff, 0xa0000030, 0 , 0,\n+ CP1_ }, /* ADD.fmt0 */\n+ { pool , SELEQZ_fmt , 2 , 32,\n+ 0xfc0001ff, 0xa0000038, 0 , 0,\n+ CP1_ }, /* SELEQZ.fmt */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa0000040, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(8) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa0000048, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(9) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa0000050, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(10) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa0000058, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(11) */\n+ { pool , CLASS_fmt , 2 , 32,\n+ 0xfc0001ff, 0xa0000060, 0 , 0,\n+ CP1_ }, /* CLASS.fmt */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa0000068, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(13) */\n+ { pool , SUB_fmt0 , 2 , 32,\n+ 0xfc0001ff, 0xa0000070, 0 , 0,\n+ CP1_ }, /* SUB.fmt0 */\n+ { pool , SELNEZ_fmt , 2 , 32,\n+ 0xfc0001ff, 0xa0000078, 0 , 0,\n+ CP1_ }, /* SELNEZ.fmt */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa0000080, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(16) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa0000088, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(17) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa0000090, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(18) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa0000098, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(19) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa00000a0, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(20) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa00000a8, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(21) */\n+ { pool , MUL_fmt0 , 2 , 32,\n+ 0xfc0001ff, 0xa00000b0, 0 , 0,\n+ CP1_ }, /* MUL.fmt0 */\n+ { pool , SEL_fmt , 2 , 32,\n+ 0xfc0001ff, 0xa00000b8, 0 , 0,\n+ CP1_ }, /* SEL.fmt */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa00000c0, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(24) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa00000c8, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(25) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa00000d0, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(26) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa00000d8, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(27) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa00000e0, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(28) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa00000e8, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(29) */\n+ { pool , DIV_fmt0 , 2 , 32,\n+ 0xfc0001ff, 0xa00000f0, 0 , 0,\n+ CP1_ }, /* DIV.fmt0 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa00000f8, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(31) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa0000100, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(32) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa0000108, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(33) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa0000110, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(34) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa0000118, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(35) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa0000120, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(36) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa0000128, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(37) */\n+ { pool , ADD_fmt1 , 2 , 32,\n+ 0xfc0001ff, 0xa0000130, 0 , 0,\n+ CP1_ }, /* ADD.fmt1 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa0000138, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(39) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa0000140, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(40) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa0000148, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(41) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa0000150, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(42) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa0000158, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(43) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa0000160, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(44) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa0000168, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(45) */\n+ { pool , SUB_fmt1 , 2 , 32,\n+ 0xfc0001ff, 0xa0000170, 0 , 0,\n+ CP1_ }, /* SUB.fmt1 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa0000178, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(47) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa0000180, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(48) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa0000188, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(49) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa0000190, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(50) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa0000198, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(51) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa00001a0, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(52) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa00001a8, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(53) */\n+ { pool , MUL_fmt1 , 2 , 32,\n+ 0xfc0001ff, 0xa00001b0, 0 , 0,\n+ CP1_ }, /* MUL.fmt1 */\n+ { pool , MADDF_fmt , 2 , 32,\n+ 0xfc0001ff, 0xa00001b8, 0 , 0,\n+ CP1_ }, /* MADDF.fmt */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa00001c0, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(56) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa00001c8, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(57) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa00001d0, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(58) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa00001d8, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(59) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa00001e0, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(60) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xa00001e8, 0 , 0,\n+ CP1_ }, /* POOL32F_0~*(61) */\n+ { pool , DIV_fmt1 , 2 , 32,\n+ 0xfc0001ff, 0xa00001f0, 0 , 0,\n+ CP1_ }, /* DIV.fmt1 */\n+ { pool , MSUBF_fmt , 2 , 32,\n+ 0xfc0001ff, 0xa00001f8, 0 , 0,\n+ CP1_ }, /* MSUBF.fmt */\n+};\n+\n+\n+NMD::Pool NMD::MIN_fmt[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00023f, 0xa0000003, &NMD::MIN_S , 0,\n+ CP1_ }, /* MIN.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00023f, 0xa0000203, &NMD::MIN_D , 0,\n+ CP1_ }, /* MIN.D */\n+};\n+\n+\n+NMD::Pool NMD::MAX_fmt[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00023f, 0xa000000b, &NMD::MAX_S , 0,\n+ CP1_ }, /* MAX.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00023f, 0xa000020b, &NMD::MAX_D , 0,\n+ CP1_ }, /* MAX.D */\n+};\n+\n+\n+NMD::Pool NMD::MINA_fmt[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00023f, 0xa0000023, &NMD::MINA_S , 0,\n+ CP1_ }, /* MINA.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00023f, 0xa0000223, &NMD::MINA_D , 0,\n+ CP1_ }, /* MINA.D */\n+};\n+\n+\n+NMD::Pool NMD::MAXA_fmt[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00023f, 0xa000002b, &NMD::MAXA_S , 0,\n+ CP1_ }, /* MAXA.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00023f, 0xa000022b, &NMD::MAXA_D , 0,\n+ CP1_ }, /* MAXA.D */\n+};\n+\n+\n+NMD::Pool NMD::CVT_L_fmt[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa000013b, &NMD::CVT_L_S , 0,\n+ CP1_ }, /* CVT.L.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa000413b, &NMD::CVT_L_D , 0,\n+ CP1_ }, /* CVT.L.D */\n+};\n+\n+\n+NMD::Pool NMD::RSQRT_fmt[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa000023b, &NMD::RSQRT_S , 0,\n+ CP1_ }, /* RSQRT.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa000423b, &NMD::RSQRT_D , 0,\n+ CP1_ }, /* RSQRT.D */\n+};\n+\n+\n+NMD::Pool NMD::FLOOR_L_fmt[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa000033b, &NMD::FLOOR_L_S , 0,\n+ CP1_ }, /* FLOOR.L.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa000433b, &NMD::FLOOR_L_D , 0,\n+ CP1_ }, /* FLOOR.L.D */\n+};\n+\n+\n+NMD::Pool NMD::CVT_W_fmt[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa000093b, &NMD::CVT_W_S , 0,\n+ CP1_ }, /* CVT.W.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa000493b, &NMD::CVT_W_D , 0,\n+ CP1_ }, /* CVT.W.D */\n+};\n+\n+\n+NMD::Pool NMD::SQRT_fmt[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa0000a3b, &NMD::SQRT_S , 0,\n+ CP1_ }, /* SQRT.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa0004a3b, &NMD::SQRT_D , 0,\n+ CP1_ }, /* SQRT.D */\n+};\n+\n+\n+NMD::Pool NMD::FLOOR_W_fmt[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa0000b3b, &NMD::FLOOR_W_S , 0,\n+ CP1_ }, /* FLOOR.W.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa0004b3b, &NMD::FLOOR_W_D , 0,\n+ CP1_ }, /* FLOOR.W.D */\n+};\n+\n+\n+NMD::Pool NMD::RECIP_fmt[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa000123b, &NMD::RECIP_S , 0,\n+ CP1_ }, /* RECIP.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa000523b, &NMD::RECIP_D , 0,\n+ CP1_ }, /* RECIP.D */\n+};\n+\n+\n+NMD::Pool NMD::CEIL_L_fmt[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa000133b, &NMD::CEIL_L_S , 0,\n+ CP1_ }, /* CEIL.L.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa000533b, &NMD::CEIL_L_D , 0,\n+ CP1_ }, /* CEIL.L.D */\n+};\n+\n+\n+NMD::Pool NMD::CEIL_W_fmt[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa0001b3b, &NMD::CEIL_W_S , 0,\n+ CP1_ }, /* CEIL.W.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa0005b3b, &NMD::CEIL_W_D , 0,\n+ CP1_ }, /* CEIL.W.D */\n+};\n+\n+\n+NMD::Pool NMD::TRUNC_L_fmt[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa000233b, &NMD::TRUNC_L_S , 0,\n+ CP1_ }, /* TRUNC.L.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa000633b, &NMD::TRUNC_L_D , 0,\n+ CP1_ }, /* TRUNC.L.D */\n+};\n+\n+\n+NMD::Pool NMD::TRUNC_W_fmt[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa0002b3b, &NMD::TRUNC_W_S , 0,\n+ CP1_ }, /* TRUNC.W.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa0006b3b, &NMD::TRUNC_W_D , 0,\n+ CP1_ }, /* TRUNC.W.D */\n+};\n+\n+\n+NMD::Pool NMD::ROUND_L_fmt[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa000333b, &NMD::ROUND_L_S , 0,\n+ CP1_ }, /* ROUND.L.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa000733b, &NMD::ROUND_L_D , 0,\n+ CP1_ }, /* ROUND.L.D */\n+};\n+\n+\n+NMD::Pool NMD::ROUND_W_fmt[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa0003b3b, &NMD::ROUND_W_S , 0,\n+ CP1_ }, /* ROUND.W.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa0007b3b, &NMD::ROUND_W_D , 0,\n+ CP1_ }, /* ROUND.W.D */\n+};\n+\n+\n+NMD::Pool NMD::POOL32Fxf_0[64] = {\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa000003b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(0) */\n+ { pool , CVT_L_fmt , 2 , 32,\n+ 0xfc003fff, 0xa000013b, 0 , 0,\n+ CP1_ }, /* CVT.L.fmt */\n+ { pool , RSQRT_fmt , 2 , 32,\n+ 0xfc003fff, 0xa000023b, 0 , 0,\n+ CP1_ }, /* RSQRT.fmt */\n+ { pool , FLOOR_L_fmt , 2 , 32,\n+ 0xfc003fff, 0xa000033b, 0 , 0,\n+ CP1_ }, /* FLOOR.L.fmt */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa000043b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(4) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa000053b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(5) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa000063b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(6) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa000073b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(7) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa000083b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(8) */\n+ { pool , CVT_W_fmt , 2 , 32,\n+ 0xfc003fff, 0xa000093b, 0 , 0,\n+ CP1_ }, /* CVT.W.fmt */\n+ { pool , SQRT_fmt , 2 , 32,\n+ 0xfc003fff, 0xa0000a3b, 0 , 0,\n+ CP1_ }, /* SQRT.fmt */\n+ { pool , FLOOR_W_fmt , 2 , 32,\n+ 0xfc003fff, 0xa0000b3b, 0 , 0,\n+ CP1_ }, /* FLOOR.W.fmt */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa0000c3b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(12) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa0000d3b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(13) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa0000e3b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(14) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa0000f3b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(15) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0xa000103b, &NMD::CFC1 , 0,\n+ CP1_ }, /* CFC1 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa000113b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(17) */\n+ { pool , RECIP_fmt , 2 , 32,\n+ 0xfc003fff, 0xa000123b, 0 , 0,\n+ CP1_ }, /* RECIP.fmt */\n+ { pool , CEIL_L_fmt , 2 , 32,\n+ 0xfc003fff, 0xa000133b, 0 , 0,\n+ CP1_ }, /* CEIL.L.fmt */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa000143b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(20) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa000153b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(21) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa000163b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(22) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa000173b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(23) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0xa000183b, &NMD::CTC1 , 0,\n+ CP1_ }, /* CTC1 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa000193b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(25) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa0001a3b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(26) */\n+ { pool , CEIL_W_fmt , 2 , 32,\n+ 0xfc003fff, 0xa0001b3b, 0 , 0,\n+ CP1_ }, /* CEIL.W.fmt */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa0001c3b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(28) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa0001d3b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(29) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa0001e3b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(30) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa0001f3b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(31) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0xa000203b, &NMD::MFC1 , 0,\n+ CP1_ }, /* MFC1 */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0xa000213b, &NMD::CVT_S_PL , 0,\n+ CP1_ }, /* CVT.S.PL */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa000223b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(34) */\n+ { pool , TRUNC_L_fmt , 2 , 32,\n+ 0xfc003fff, 0xa000233b, 0 , 0,\n+ CP1_ }, /* TRUNC.L.fmt */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0xa000243b, &NMD::DMFC1 , 0,\n+ CP1_ | MIPS64_ }, /* DMFC1 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa000253b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(37) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa000263b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(38) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa000273b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(39) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0xa000283b, &NMD::MTC1 , 0,\n+ CP1_ }, /* MTC1 */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0xa000293b, &NMD::CVT_S_PU , 0,\n+ CP1_ }, /* CVT.S.PU */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa0002a3b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(42) */\n+ { pool , TRUNC_W_fmt , 2 , 32,\n+ 0xfc003fff, 0xa0002b3b, 0 , 0,\n+ CP1_ }, /* TRUNC.W.fmt */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0xa0002c3b, &NMD::DMTC1 , 0,\n+ CP1_ | MIPS64_ }, /* DMTC1 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa0002d3b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(45) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa0002e3b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(46) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa0002f3b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(47) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0xa000303b, &NMD::MFHC1 , 0,\n+ CP1_ }, /* MFHC1 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa000313b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(49) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa000323b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(50) */\n+ { pool , ROUND_L_fmt , 2 , 32,\n+ 0xfc003fff, 0xa000333b, 0 , 0,\n+ CP1_ }, /* ROUND.L.fmt */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa000343b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(52) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa000353b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(53) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa000363b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(54) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa000373b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(55) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc003fff, 0xa000383b, &NMD::MTHC1 , 0,\n+ CP1_ }, /* MTHC1 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa000393b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(57) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa0003a3b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(58) */\n+ { pool , ROUND_W_fmt , 2 , 32,\n+ 0xfc003fff, 0xa0003b3b, 0 , 0,\n+ CP1_ }, /* ROUND.W.fmt */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa0003c3b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(60) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa0003d3b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(61) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa0003e3b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(62) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc003fff, 0xa0003f3b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0~*(63) */\n+};\n+\n+\n+NMD::Pool NMD::MOV_fmt[4] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa000007b, &NMD::MOV_S , 0,\n+ CP1_ }, /* MOV.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa000207b, &NMD::MOV_D , 0,\n+ CP1_ }, /* MOV.D */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007fff, 0xa000407b, 0 , 0,\n+ CP1_ }, /* MOV.fmt~*(2) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007fff, 0xa000607b, 0 , 0,\n+ CP1_ }, /* MOV.fmt~*(3) */\n+};\n+\n+\n+NMD::Pool NMD::ABS_fmt[4] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa000037b, &NMD::ABS_S , 0,\n+ CP1_ }, /* ABS.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa000237b, &NMD::ABS_D , 0,\n+ CP1_ }, /* ABS.D */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007fff, 0xa000437b, 0 , 0,\n+ CP1_ }, /* ABS.fmt~*(2) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007fff, 0xa000637b, 0 , 0,\n+ CP1_ }, /* ABS.fmt~*(3) */\n+};\n+\n+\n+NMD::Pool NMD::NEG_fmt[4] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa0000b7b, &NMD::NEG_S , 0,\n+ CP1_ }, /* NEG.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa0002b7b, &NMD::NEG_D , 0,\n+ CP1_ }, /* NEG.D */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007fff, 0xa0004b7b, 0 , 0,\n+ CP1_ }, /* NEG.fmt~*(2) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007fff, 0xa0006b7b, 0 , 0,\n+ CP1_ }, /* NEG.fmt~*(3) */\n+};\n+\n+\n+NMD::Pool NMD::CVT_D_fmt[4] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa000137b, &NMD::CVT_D_S , 0,\n+ CP1_ }, /* CVT.D.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa000337b, &NMD::CVT_D_W , 0,\n+ CP1_ }, /* CVT.D.W */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa000537b, &NMD::CVT_D_L , 0,\n+ CP1_ }, /* CVT.D.L */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007fff, 0xa000737b, 0 , 0,\n+ CP1_ }, /* CVT.D.fmt~*(3) */\n+};\n+\n+\n+NMD::Pool NMD::CVT_S_fmt[4] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa0001b7b, &NMD::CVT_S_D , 0,\n+ CP1_ }, /* CVT.S.D */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa0003b7b, &NMD::CVT_S_W , 0,\n+ CP1_ }, /* CVT.S.W */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007fff, 0xa0005b7b, &NMD::CVT_S_L , 0,\n+ CP1_ }, /* CVT.S.L */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007fff, 0xa0007b7b, 0 , 0,\n+ CP1_ }, /* CVT.S.fmt~*(3) */\n+};\n+\n+\n+NMD::Pool NMD::POOL32Fxf_1[32] = {\n+ { pool , MOV_fmt , 4 , 32,\n+ 0xfc001fff, 0xa000007b, 0 , 0,\n+ CP1_ }, /* MOV.fmt */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc001fff, 0xa000017b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_1~*(1) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc001fff, 0xa000027b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_1~*(2) */\n+ { pool , ABS_fmt , 4 , 32,\n+ 0xfc001fff, 0xa000037b, 0 , 0,\n+ CP1_ }, /* ABS.fmt */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc001fff, 0xa000047b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_1~*(4) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc001fff, 0xa000057b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_1~*(5) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc001fff, 0xa000067b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_1~*(6) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc001fff, 0xa000077b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_1~*(7) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc001fff, 0xa000087b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_1~*(8) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc001fff, 0xa000097b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_1~*(9) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc001fff, 0xa0000a7b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_1~*(10) */\n+ { pool , NEG_fmt , 4 , 32,\n+ 0xfc001fff, 0xa0000b7b, 0 , 0,\n+ CP1_ }, /* NEG.fmt */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc001fff, 0xa0000c7b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_1~*(12) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc001fff, 0xa0000d7b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_1~*(13) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc001fff, 0xa0000e7b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_1~*(14) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc001fff, 0xa0000f7b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_1~*(15) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc001fff, 0xa000107b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_1~*(16) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc001fff, 0xa000117b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_1~*(17) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc001fff, 0xa000127b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_1~*(18) */\n+ { pool , CVT_D_fmt , 4 , 32,\n+ 0xfc001fff, 0xa000137b, 0 , 0,\n+ CP1_ }, /* CVT.D.fmt */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc001fff, 0xa000147b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_1~*(20) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc001fff, 0xa000157b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_1~*(21) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc001fff, 0xa000167b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_1~*(22) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc001fff, 0xa000177b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_1~*(23) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc001fff, 0xa000187b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_1~*(24) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc001fff, 0xa000197b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_1~*(25) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc001fff, 0xa0001a7b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_1~*(26) */\n+ { pool , CVT_S_fmt , 4 , 32,\n+ 0xfc001fff, 0xa0001b7b, 0 , 0,\n+ CP1_ }, /* CVT.S.fmt */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc001fff, 0xa0001c7b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_1~*(28) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc001fff, 0xa0001d7b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_1~*(29) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc001fff, 0xa0001e7b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_1~*(30) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc001fff, 0xa0001f7b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_1~*(31) */\n+};\n+\n+\n+NMD::Pool NMD::POOL32Fxf[4] = {\n+ { pool , POOL32Fxf_0 , 64 , 32,\n+ 0xfc0000ff, 0xa000003b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_0 */\n+ { pool , POOL32Fxf_1 , 32 , 32,\n+ 0xfc0000ff, 0xa000007b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf_1 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0000ff, 0xa00000bb, 0 , 0,\n+ CP1_ }, /* POOL32Fxf~*(2) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0000ff, 0xa00000fb, 0 , 0,\n+ CP1_ }, /* POOL32Fxf~*(3) */\n+};\n+\n+\n+NMD::Pool NMD::POOL32F_3[8] = {\n+ { pool , MIN_fmt , 2 , 32,\n+ 0xfc00003f, 0xa0000003, 0 , 0,\n+ CP1_ }, /* MIN.fmt */\n+ { pool , MAX_fmt , 2 , 32,\n+ 0xfc00003f, 0xa000000b, 0 , 0,\n+ CP1_ }, /* MAX.fmt */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00003f, 0xa0000013, 0 , 0,\n+ CP1_ }, /* POOL32F_3~*(2) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00003f, 0xa000001b, 0 , 0,\n+ CP1_ }, /* POOL32F_3~*(3) */\n+ { pool , MINA_fmt , 2 , 32,\n+ 0xfc00003f, 0xa0000023, 0 , 0,\n+ CP1_ }, /* MINA.fmt */\n+ { pool , MAXA_fmt , 2 , 32,\n+ 0xfc00003f, 0xa000002b, 0 , 0,\n+ CP1_ }, /* MAXA.fmt */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00003f, 0xa0000033, 0 , 0,\n+ CP1_ }, /* POOL32F_3~*(6) */\n+ { pool , POOL32Fxf , 4 , 32,\n+ 0xfc00003f, 0xa000003b, 0 , 0,\n+ CP1_ }, /* POOL32Fxf */\n+};\n+\n+\n+NMD::Pool NMD::CMP_condn_S[32] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000005, &NMD::CMP_AF_S , 0,\n+ CP1_ }, /* CMP.AF.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000045, &NMD::CMP_UN_S , 0,\n+ CP1_ }, /* CMP.UN.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000085, &NMD::CMP_EQ_S , 0,\n+ CP1_ }, /* CMP.EQ.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa00000c5, &NMD::CMP_UEQ_S , 0,\n+ CP1_ }, /* CMP.UEQ.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000105, &NMD::CMP_LT_S , 0,\n+ CP1_ }, /* CMP.LT.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000145, &NMD::CMP_ULT_S , 0,\n+ CP1_ }, /* CMP.ULT.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000185, &NMD::CMP_LE_S , 0,\n+ CP1_ }, /* CMP.LE.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa00001c5, &NMD::CMP_ULE_S , 0,\n+ CP1_ }, /* CMP.ULE.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000205, &NMD::CMP_SAF_S , 0,\n+ CP1_ }, /* CMP.SAF.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000245, &NMD::CMP_SUN_S , 0,\n+ CP1_ }, /* CMP.SUN.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000285, &NMD::CMP_SEQ_S , 0,\n+ CP1_ }, /* CMP.SEQ.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa00002c5, &NMD::CMP_SUEQ_S , 0,\n+ CP1_ }, /* CMP.SUEQ.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000305, &NMD::CMP_SLT_S , 0,\n+ CP1_ }, /* CMP.SLT.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000345, &NMD::CMP_SULT_S , 0,\n+ CP1_ }, /* CMP.SULT.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000385, &NMD::CMP_SLE_S , 0,\n+ CP1_ }, /* CMP.SLE.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa00003c5, &NMD::CMP_SULE_S , 0,\n+ CP1_ }, /* CMP.SULE.S */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000405, 0 , 0,\n+ CP1_ }, /* CMP.condn.S~*(16) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000445, &NMD::CMP_OR_S , 0,\n+ CP1_ }, /* CMP.OR.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000485, &NMD::CMP_UNE_S , 0,\n+ CP1_ }, /* CMP.UNE.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa00004c5, &NMD::CMP_NE_S , 0,\n+ CP1_ }, /* CMP.NE.S */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000505, 0 , 0,\n+ CP1_ }, /* CMP.condn.S~*(20) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000545, 0 , 0,\n+ CP1_ }, /* CMP.condn.S~*(21) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000585, 0 , 0,\n+ CP1_ }, /* CMP.condn.S~*(22) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa00005c5, 0 , 0,\n+ CP1_ }, /* CMP.condn.S~*(23) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000605, 0 , 0,\n+ CP1_ }, /* CMP.condn.S~*(24) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000645, &NMD::CMP_SOR_S , 0,\n+ CP1_ }, /* CMP.SOR.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000685, &NMD::CMP_SUNE_S , 0,\n+ CP1_ }, /* CMP.SUNE.S */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa00006c5, &NMD::CMP_SNE_S , 0,\n+ CP1_ }, /* CMP.SNE.S */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000705, 0 , 0,\n+ CP1_ }, /* CMP.condn.S~*(28) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000745, 0 , 0,\n+ CP1_ }, /* CMP.condn.S~*(29) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000785, 0 , 0,\n+ CP1_ }, /* CMP.condn.S~*(30) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa00007c5, 0 , 0,\n+ CP1_ }, /* CMP.condn.S~*(31) */\n+};\n+\n+\n+NMD::Pool NMD::CMP_condn_D[32] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000015, &NMD::CMP_AF_D , 0,\n+ CP1_ }, /* CMP.AF.D */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000055, &NMD::CMP_UN_D , 0,\n+ CP1_ }, /* CMP.UN.D */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000095, &NMD::CMP_EQ_D , 0,\n+ CP1_ }, /* CMP.EQ.D */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa00000d5, &NMD::CMP_UEQ_D , 0,\n+ CP1_ }, /* CMP.UEQ.D */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000115, &NMD::CMP_LT_D , 0,\n+ CP1_ }, /* CMP.LT.D */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000155, &NMD::CMP_ULT_D , 0,\n+ CP1_ }, /* CMP.ULT.D */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000195, &NMD::CMP_LE_D , 0,\n+ CP1_ }, /* CMP.LE.D */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa00001d5, &NMD::CMP_ULE_D , 0,\n+ CP1_ }, /* CMP.ULE.D */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000215, &NMD::CMP_SAF_D , 0,\n+ CP1_ }, /* CMP.SAF.D */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000255, &NMD::CMP_SUN_D , 0,\n+ CP1_ }, /* CMP.SUN.D */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000295, &NMD::CMP_SEQ_D , 0,\n+ CP1_ }, /* CMP.SEQ.D */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa00002d5, &NMD::CMP_SUEQ_D , 0,\n+ CP1_ }, /* CMP.SUEQ.D */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000315, &NMD::CMP_SLT_D , 0,\n+ CP1_ }, /* CMP.SLT.D */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000355, &NMD::CMP_SULT_D , 0,\n+ CP1_ }, /* CMP.SULT.D */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000395, &NMD::CMP_SLE_D , 0,\n+ CP1_ }, /* CMP.SLE.D */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa00003d5, &NMD::CMP_SULE_D , 0,\n+ CP1_ }, /* CMP.SULE.D */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000415, 0 , 0,\n+ CP1_ }, /* CMP.condn.D~*(16) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000455, &NMD::CMP_OR_D , 0,\n+ CP1_ }, /* CMP.OR.D */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000495, &NMD::CMP_UNE_D , 0,\n+ CP1_ }, /* CMP.UNE.D */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa00004d5, &NMD::CMP_NE_D , 0,\n+ CP1_ }, /* CMP.NE.D */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000515, 0 , 0,\n+ CP1_ }, /* CMP.condn.D~*(20) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000555, 0 , 0,\n+ CP1_ }, /* CMP.condn.D~*(21) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000595, 0 , 0,\n+ CP1_ }, /* CMP.condn.D~*(22) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa00005d5, 0 , 0,\n+ CP1_ }, /* CMP.condn.D~*(23) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000615, 0 , 0,\n+ CP1_ }, /* CMP.condn.D~*(24) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000655, &NMD::CMP_SOR_D , 0,\n+ CP1_ }, /* CMP.SOR.D */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000695, &NMD::CMP_SUNE_D , 0,\n+ CP1_ }, /* CMP.SUNE.D */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa00006d5, &NMD::CMP_SNE_D , 0,\n+ CP1_ }, /* CMP.SNE.D */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000715, 0 , 0,\n+ CP1_ }, /* CMP.condn.D~*(28) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000755, 0 , 0,\n+ CP1_ }, /* CMP.condn.D~*(29) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa0000795, 0 , 0,\n+ CP1_ }, /* CMP.condn.D~*(30) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0007ff, 0xa00007d5, 0 , 0,\n+ CP1_ }, /* CMP.condn.D~*(31) */\n+};\n+\n+\n+NMD::Pool NMD::POOL32F_5[8] = {\n+ { pool , CMP_condn_S , 32 , 32,\n+ 0xfc00003f, 0xa0000005, 0 , 0,\n+ CP1_ }, /* CMP.condn.S */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00003f, 0xa000000d, 0 , 0,\n+ CP1_ }, /* POOL32F_5~*(1) */\n+ { pool , CMP_condn_D , 32 , 32,\n+ 0xfc00003f, 0xa0000015, 0 , 0,\n+ CP1_ }, /* CMP.condn.D */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00003f, 0xa000001d, 0 , 0,\n+ CP1_ }, /* POOL32F_5~*(3) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00003f, 0xa0000025, 0 , 0,\n+ CP1_ }, /* POOL32F_5~*(4) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00003f, 0xa000002d, 0 , 0,\n+ CP1_ }, /* POOL32F_5~*(5) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00003f, 0xa0000035, 0 , 0,\n+ CP1_ }, /* POOL32F_5~*(6) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00003f, 0xa000003d, 0 , 0,\n+ CP1_ }, /* POOL32F_5~*(7) */\n+};\n+\n+\n+NMD::Pool NMD::POOL32F[8] = {\n+ { pool , POOL32F_0 , 64 , 32,\n+ 0xfc000007, 0xa0000000, 0 , 0,\n+ CP1_ }, /* POOL32F_0 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000007, 0xa0000001, 0 , 0,\n+ CP1_ }, /* POOL32F~*(1) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000007, 0xa0000002, 0 , 0,\n+ CP1_ }, /* POOL32F~*(2) */\n+ { pool , POOL32F_3 , 8 , 32,\n+ 0xfc000007, 0xa0000003, 0 , 0,\n+ CP1_ }, /* POOL32F_3 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000007, 0xa0000004, 0 , 0,\n+ CP1_ }, /* POOL32F~*(4) */\n+ { pool , POOL32F_5 , 8 , 32,\n+ 0xfc000007, 0xa0000005, 0 , 0,\n+ CP1_ }, /* POOL32F_5 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000007, 0xa0000006, 0 , 0,\n+ CP1_ }, /* POOL32F~*(6) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000007, 0xa0000007, 0 , 0,\n+ CP1_ }, /* POOL32F~*(7) */\n+};\n+\n+\n+NMD::Pool NMD::POOL32S_0[64] = {\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000000, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(0) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000008, &NMD::DLSA , 0,\n+ MIPS64_ }, /* DLSA */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000010, &NMD::DSLLV , 0,\n+ MIPS64_ }, /* DSLLV */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000018, &NMD::DMUL , 0,\n+ MIPS64_ }, /* DMUL */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000020, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(4) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000028, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(5) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000030, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(6) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000038, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(7) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000040, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(8) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000048, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(9) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000050, &NMD::DSRLV , 0,\n+ MIPS64_ }, /* DSRLV */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000058, &NMD::DMUH , 0,\n+ MIPS64_ }, /* DMUH */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000060, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(12) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000068, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(13) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000070, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(14) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000078, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(15) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000080, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(16) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000088, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(17) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000090, &NMD::DSRAV , 0,\n+ MIPS64_ }, /* DSRAV */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000098, &NMD::DMULU , 0,\n+ MIPS64_ }, /* DMULU */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc00000a0, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(20) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc00000a8, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(21) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc00000b0, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(22) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc00000b8, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(23) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc00000c0, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(24) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc00000c8, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(25) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc00000d0, &NMD::DROTRV , 0,\n+ MIPS64_ }, /* DROTRV */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc00000d8, &NMD::DMUHU , 0,\n+ MIPS64_ }, /* DMUHU */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc00000e0, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(28) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc00000e8, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(29) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc00000f0, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(30) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc00000f8, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(31) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000100, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(32) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000108, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(33) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000110, &NMD::DADD , 0,\n+ MIPS64_ }, /* DADD */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000118, &NMD::DDIV , 0,\n+ MIPS64_ }, /* DDIV */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000120, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(36) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000128, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(37) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000130, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(38) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000138, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(39) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000140, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(40) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000148, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(41) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000150, &NMD::DADDU , 0,\n+ MIPS64_ }, /* DADDU */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000158, &NMD::DMOD , 0,\n+ MIPS64_ }, /* DMOD */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000160, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(44) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000168, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(45) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000170, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(46) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000178, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(47) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000180, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(48) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000188, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(49) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000190, &NMD::DSUB , 0,\n+ MIPS64_ }, /* DSUB */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc0000198, &NMD::DDIVU , 0,\n+ MIPS64_ }, /* DDIVU */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc00001a0, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(52) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc00001a8, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(53) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc00001b0, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(54) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc00001b8, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(55) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc00001c0, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(56) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc00001c8, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(57) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc00001d0, &NMD::DSUBU , 0,\n+ MIPS64_ }, /* DSUBU */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc00001d8, &NMD::DMODU , 0,\n+ MIPS64_ }, /* DMODU */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc00001e0, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(60) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc00001e8, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(61) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc00001f0, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(62) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc00001f8, 0 , 0,\n+ 0x0 }, /* POOL32S_0~*(63) */\n+};\n+\n+\n+NMD::Pool NMD::POOL32Sxf_4[128] = {\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000013c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(0) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000033c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(1) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000053c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(2) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000073c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(3) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000093c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(4) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc0000b3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(5) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc0000d3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(6) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc0000f3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(7) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000113c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(8) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000133c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(9) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000153c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(10) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000173c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(11) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000193c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(12) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc0001b3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(13) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc0001d3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(14) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc0001f3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(15) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000213c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(16) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000233c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(17) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000253c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(18) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000273c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(19) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000293c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(20) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc0002b3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(21) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc0002d3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(22) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc0002f3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(23) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000313c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(24) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000333c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(25) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000353c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(26) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000373c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(27) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000393c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(28) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc0003b3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(29) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc0003d3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(30) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc0003f3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(31) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000413c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(32) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000433c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(33) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000453c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(34) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000473c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(35) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000493c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(36) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc0004b3c, &NMD::DCLO , 0,\n+ MIPS64_ }, /* DCLO */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc0004d3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(38) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc0004f3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(39) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000513c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(40) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000533c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(41) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000553c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(42) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000573c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(43) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000593c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(44) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc0005b3c, &NMD::DCLZ , 0,\n+ MIPS64_ }, /* DCLZ */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc0005d3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(46) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc0005f3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(47) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000613c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(48) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000633c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(49) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000653c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(50) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000673c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(51) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000693c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(52) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc0006b3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(53) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc0006d3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(54) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc0006f3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(55) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000713c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(56) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000733c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(57) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000753c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(58) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000773c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(59) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000793c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(60) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc0007b3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(61) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc0007d3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(62) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc0007f3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(63) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000813c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(64) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000833c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(65) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000853c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(66) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000873c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(67) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000893c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(68) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc0008b3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(69) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc0008d3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(70) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc0008f3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(71) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000913c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(72) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000933c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(73) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000953c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(74) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000973c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(75) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000993c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(76) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc0009b3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(77) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc0009d3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(78) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc0009f3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(79) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000a13c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(80) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000a33c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(81) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000a53c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(82) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000a73c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(83) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000a93c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(84) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000ab3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(85) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000ad3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(86) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000af3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(87) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000b13c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(88) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000b33c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(89) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000b53c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(90) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000b73c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(91) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000b93c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(92) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000bb3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(93) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000bd3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(94) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000bf3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(95) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000c13c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(96) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000c33c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(97) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000c53c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(98) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000c73c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(99) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000c93c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(100) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000cb3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(101) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000cd3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(102) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000cf3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(103) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000d13c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(104) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000d33c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(105) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000d53c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(106) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000d73c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(107) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000d93c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(108) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000db3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(109) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000dd3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(110) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000df3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(111) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000e13c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(112) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000e33c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(113) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000e53c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(114) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000e73c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(115) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000e93c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(116) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000eb3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(117) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000ed3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(118) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000ef3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(119) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000f13c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(120) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000f33c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(121) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000f53c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(122) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000f73c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(123) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000f93c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(124) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000fb3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(125) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000fd3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(126) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00ffff, 0xc000ff3c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4~*(127) */\n+};\n+\n+\n+NMD::Pool NMD::POOL32Sxf[8] = {\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc000003c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf~*(0) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc000007c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf~*(1) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc00000bc, 0 , 0,\n+ 0x0 }, /* POOL32Sxf~*(2) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc00000fc, 0 , 0,\n+ 0x0 }, /* POOL32Sxf~*(3) */\n+ { pool , POOL32Sxf_4 , 128 , 32,\n+ 0xfc0001ff, 0xc000013c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf_4 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc000017c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf~*(5) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc00001bc, 0 , 0,\n+ 0x0 }, /* POOL32Sxf~*(6) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc0001ff, 0xc00001fc, 0 , 0,\n+ 0x0 }, /* POOL32Sxf~*(7) */\n+};\n+\n+\n+NMD::Pool NMD::POOL32S_4[8] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00003f, 0xc0000004, &NMD::EXTD , 0,\n+ MIPS64_ }, /* EXTD */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00003f, 0xc000000c, &NMD::EXTD32 , 0,\n+ MIPS64_ }, /* EXTD32 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00003f, 0xc0000014, 0 , 0,\n+ 0x0 }, /* POOL32S_4~*(2) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00003f, 0xc000001c, 0 , 0,\n+ 0x0 }, /* POOL32S_4~*(3) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00003f, 0xc0000024, 0 , 0,\n+ 0x0 }, /* POOL32S_4~*(4) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00003f, 0xc000002c, 0 , 0,\n+ 0x0 }, /* POOL32S_4~*(5) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00003f, 0xc0000034, 0 , 0,\n+ 0x0 }, /* POOL32S_4~*(6) */\n+ { pool , POOL32Sxf , 8 , 32,\n+ 0xfc00003f, 0xc000003c, 0 , 0,\n+ 0x0 }, /* POOL32Sxf */\n+};\n+\n+\n+NMD::Pool NMD::POOL32S[8] = {\n+ { pool , POOL32S_0 , 64 , 32,\n+ 0xfc000007, 0xc0000000, 0 , 0,\n+ 0x0 }, /* POOL32S_0 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000007, 0xc0000001, 0 , 0,\n+ 0x0 }, /* POOL32S~*(1) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000007, 0xc0000002, 0 , 0,\n+ 0x0 }, /* POOL32S~*(2) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000007, 0xc0000003, 0 , 0,\n+ 0x0 }, /* POOL32S~*(3) */\n+ { pool , POOL32S_4 , 8 , 32,\n+ 0xfc000007, 0xc0000004, 0 , 0,\n+ 0x0 }, /* POOL32S_4 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000007, 0xc0000005, 0 , 0,\n+ 0x0 }, /* POOL32S~*(5) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000007, 0xc0000006, 0 , 0,\n+ 0x0 }, /* POOL32S~*(6) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000007, 0xc0000007, 0 , 0,\n+ 0x0 }, /* POOL32S~*(7) */\n+};\n+\n+\n+NMD::Pool NMD::P_LUI[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc000002, 0xe0000000, &NMD::LUI , 0,\n+ 0x0 }, /* LUI */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc000002, 0xe0000002, &NMD::ALUIPC , 0,\n+ 0x0 }, /* ALUIPC */\n+};\n+\n+\n+NMD::Pool NMD::P_GP_LH[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc1c0001, 0x44100000, &NMD::LH_GP_ , 0,\n+ 0x0 }, /* LH[GP] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc1c0001, 0x44100001, &NMD::LHU_GP_ , 0,\n+ 0x0 }, /* LHU[GP] */\n+};\n+\n+\n+NMD::Pool NMD::P_GP_SH[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc1c0001, 0x44140000, &NMD::SH_GP_ , 0,\n+ 0x0 }, /* SH[GP] */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc1c0001, 0x44140001, 0 , 0,\n+ 0x0 }, /* P.GP.SH~*(1) */\n+};\n+\n+\n+NMD::Pool NMD::P_GP_CP1[4] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc1c0003, 0x44180000, &NMD::LWC1_GP_ , 0,\n+ CP1_ }, /* LWC1[GP] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc1c0003, 0x44180001, &NMD::SWC1_GP_ , 0,\n+ CP1_ }, /* SWC1[GP] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc1c0003, 0x44180002, &NMD::LDC1_GP_ , 0,\n+ CP1_ }, /* LDC1[GP] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc1c0003, 0x44180003, &NMD::SDC1_GP_ , 0,\n+ CP1_ }, /* SDC1[GP] */\n+};\n+\n+\n+NMD::Pool NMD::P_GP_M64[4] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc1c0003, 0x441c0000, &NMD::LWU_GP_ , 0,\n+ MIPS64_ }, /* LWU[GP] */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc1c0003, 0x441c0001, 0 , 0,\n+ 0x0 }, /* P.GP.M64~*(1) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc1c0003, 0x441c0002, 0 , 0,\n+ 0x0 }, /* P.GP.M64~*(2) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc1c0003, 0x441c0003, 0 , 0,\n+ 0x0 }, /* P.GP.M64~*(3) */\n+};\n+\n+\n+NMD::Pool NMD::P_GP_BH[8] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc1c0000, 0x44000000, &NMD::LB_GP_ , 0,\n+ 0x0 }, /* LB[GP] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc1c0000, 0x44040000, &NMD::SB_GP_ , 0,\n+ 0x0 }, /* SB[GP] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc1c0000, 0x44080000, &NMD::LBU_GP_ , 0,\n+ 0x0 }, /* LBU[GP] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc1c0000, 0x440c0000, &NMD::ADDIU_GP_B_ , 0,\n+ 0x0 }, /* ADDIU[GP.B] */\n+ { pool , P_GP_LH , 2 , 32,\n+ 0xfc1c0000, 0x44100000, 0 , 0,\n+ 0x0 }, /* P.GP.LH */\n+ { pool , P_GP_SH , 2 , 32,\n+ 0xfc1c0000, 0x44140000, 0 , 0,\n+ 0x0 }, /* P.GP.SH */\n+ { pool , P_GP_CP1 , 4 , 32,\n+ 0xfc1c0000, 0x44180000, 0 , 0,\n+ 0x0 }, /* P.GP.CP1 */\n+ { pool , P_GP_M64 , 4 , 32,\n+ 0xfc1c0000, 0x441c0000, 0 , 0,\n+ 0x0 }, /* P.GP.M64 */\n+};\n+\n+\n+NMD::Pool NMD::P_LS_U12[16] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f000, 0x84000000, &NMD::LB_U12_ , 0,\n+ 0x0 }, /* LB[U12] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f000, 0x84001000, &NMD::SB_U12_ , 0,\n+ 0x0 }, /* SB[U12] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f000, 0x84002000, &NMD::LBU_U12_ , 0,\n+ 0x0 }, /* LBU[U12] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f000, 0x84003000, &NMD::PREF_U12_ , 0,\n+ 0x0 }, /* PREF[U12] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f000, 0x84004000, &NMD::LH_U12_ , 0,\n+ 0x0 }, /* LH[U12] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f000, 0x84005000, &NMD::SH_U12_ , 0,\n+ 0x0 }, /* SH[U12] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f000, 0x84006000, &NMD::LHU_U12_ , 0,\n+ 0x0 }, /* LHU[U12] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f000, 0x84007000, &NMD::LWU_U12_ , 0,\n+ MIPS64_ }, /* LWU[U12] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f000, 0x84008000, &NMD::LW_U12_ , 0,\n+ 0x0 }, /* LW[U12] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f000, 0x84009000, &NMD::SW_U12_ , 0,\n+ 0x0 }, /* SW[U12] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f000, 0x8400a000, &NMD::LWC1_U12_ , 0,\n+ CP1_ }, /* LWC1[U12] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f000, 0x8400b000, &NMD::SWC1_U12_ , 0,\n+ CP1_ }, /* SWC1[U12] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f000, 0x8400c000, &NMD::LD_U12_ , 0,\n+ MIPS64_ }, /* LD[U12] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f000, 0x8400d000, &NMD::SD_U12_ , 0,\n+ MIPS64_ }, /* SD[U12] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f000, 0x8400e000, &NMD::LDC1_U12_ , 0,\n+ CP1_ }, /* LDC1[U12] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc00f000, 0x8400f000, &NMD::SDC1_U12_ , 0,\n+ CP1_ }, /* SDC1[U12] */\n+};\n+\n+\n+NMD::Pool NMD::P_PREF_S9_[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xffe07f00, 0xa7e01800, &NMD::SYNCI , 0,\n+ 0x0 }, /* SYNCI */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4001800, &NMD::PREF_S9_ , &NMD::PREF_S9__cond ,\n+ 0x0 }, /* PREF[S9] */\n+};\n+\n+\n+NMD::Pool NMD::P_LS_S0[16] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4000000, &NMD::LB_S9_ , 0,\n+ 0x0 }, /* LB[S9] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4000800, &NMD::SB_S9_ , 0,\n+ 0x0 }, /* SB[S9] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4001000, &NMD::LBU_S9_ , 0,\n+ 0x0 }, /* LBU[S9] */\n+ { pool , P_PREF_S9_ , 2 , 32,\n+ 0xfc007f00, 0xa4001800, 0 , 0,\n+ 0x0 }, /* P.PREF[S9] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4002000, &NMD::LH_S9_ , 0,\n+ 0x0 }, /* LH[S9] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4002800, &NMD::SH_S9_ , 0,\n+ 0x0 }, /* SH[S9] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4003000, &NMD::LHU_S9_ , 0,\n+ 0x0 }, /* LHU[S9] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4003800, &NMD::LWU_S9_ , 0,\n+ MIPS64_ }, /* LWU[S9] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4004000, &NMD::LW_S9_ , 0,\n+ 0x0 }, /* LW[S9] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4004800, &NMD::SW_S9_ , 0,\n+ 0x0 }, /* SW[S9] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4005000, &NMD::LWC1_S9_ , 0,\n+ CP1_ }, /* LWC1[S9] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4005800, &NMD::SWC1_S9_ , 0,\n+ CP1_ }, /* SWC1[S9] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4006000, &NMD::LD_S9_ , 0,\n+ MIPS64_ }, /* LD[S9] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4006800, &NMD::SD_S9_ , 0,\n+ MIPS64_ }, /* SD[S9] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4007000, &NMD::LDC1_S9_ , 0,\n+ CP1_ }, /* LDC1[S9] */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4007800, &NMD::SDC1_S9_ , 0,\n+ CP1_ }, /* SDC1[S9] */\n+};\n+\n+\n+NMD::Pool NMD::ASET_ACLR[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfe007f00, 0xa4001100, &NMD::ASET , 0,\n+ MCU_ }, /* ASET */\n+ { instruction , 0 , 0 , 32,\n+ 0xfe007f00, 0xa6001100, &NMD::ACLR , 0,\n+ MCU_ }, /* ACLR */\n+};\n+\n+\n+NMD::Pool NMD::P_LL[4] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f03, 0xa4005100, &NMD::LL , 0,\n+ 0x0 }, /* LL */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f03, 0xa4005101, &NMD::LLWP , 0,\n+ XNP_ }, /* LLWP */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007f03, 0xa4005102, 0 , 0,\n+ 0x0 }, /* P.LL~*(2) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007f03, 0xa4005103, 0 , 0,\n+ 0x0 }, /* P.LL~*(3) */\n+};\n+\n+\n+NMD::Pool NMD::P_SC[4] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f03, 0xa4005900, &NMD::SC , 0,\n+ 0x0 }, /* SC */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f03, 0xa4005901, &NMD::SCWP , 0,\n+ XNP_ }, /* SCWP */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007f03, 0xa4005902, 0 , 0,\n+ 0x0 }, /* P.SC~*(2) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007f03, 0xa4005903, 0 , 0,\n+ 0x0 }, /* P.SC~*(3) */\n+};\n+\n+\n+NMD::Pool NMD::P_LLD[8] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f07, 0xa4007100, &NMD::LLD , 0,\n+ MIPS64_ }, /* LLD */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f07, 0xa4007101, &NMD::LLDP , 0,\n+ MIPS64_ }, /* LLDP */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007f07, 0xa4007102, 0 , 0,\n+ 0x0 }, /* P.LLD~*(2) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007f07, 0xa4007103, 0 , 0,\n+ 0x0 }, /* P.LLD~*(3) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007f07, 0xa4007104, 0 , 0,\n+ 0x0 }, /* P.LLD~*(4) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007f07, 0xa4007105, 0 , 0,\n+ 0x0 }, /* P.LLD~*(5) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007f07, 0xa4007106, 0 , 0,\n+ 0x0 }, /* P.LLD~*(6) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007f07, 0xa4007107, 0 , 0,\n+ 0x0 }, /* P.LLD~*(7) */\n+};\n+\n+\n+NMD::Pool NMD::P_SCD[8] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f07, 0xa4007900, &NMD::SCD , 0,\n+ MIPS64_ }, /* SCD */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f07, 0xa4007901, &NMD::SCDP , 0,\n+ MIPS64_ }, /* SCDP */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007f07, 0xa4007902, 0 , 0,\n+ 0x0 }, /* P.SCD~*(2) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007f07, 0xa4007903, 0 , 0,\n+ 0x0 }, /* P.SCD~*(3) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007f07, 0xa4007904, 0 , 0,\n+ 0x0 }, /* P.SCD~*(4) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007f07, 0xa4007905, 0 , 0,\n+ 0x0 }, /* P.SCD~*(5) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007f07, 0xa4007906, 0 , 0,\n+ 0x0 }, /* P.SCD~*(6) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007f07, 0xa4007907, 0 , 0,\n+ 0x0 }, /* P.SCD~*(7) */\n+};\n+\n+\n+NMD::Pool NMD::P_LS_S1[16] = {\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4000100, 0 , 0,\n+ 0x0 }, /* P.LS.S1~*(0) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4000900, 0 , 0,\n+ 0x0 }, /* P.LS.S1~*(1) */\n+ { pool , ASET_ACLR , 2 , 32,\n+ 0xfc007f00, 0xa4001100, 0 , 0,\n+ 0x0 }, /* ASET_ACLR */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4001900, 0 , 0,\n+ 0x0 }, /* P.LS.S1~*(3) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4002100, &NMD::UALH , 0,\n+ XMMS_ }, /* UALH */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4002900, &NMD::UASH , 0,\n+ XMMS_ }, /* UASH */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4003100, 0 , 0,\n+ 0x0 }, /* P.LS.S1~*(6) */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4003900, &NMD::CACHE , 0,\n+ CP0_ }, /* CACHE */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4004100, &NMD::LWC2 , 0,\n+ CP2_ }, /* LWC2 */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4004900, &NMD::SWC2 , 0,\n+ CP2_ }, /* SWC2 */\n+ { pool , P_LL , 4 , 32,\n+ 0xfc007f00, 0xa4005100, 0 , 0,\n+ 0x0 }, /* P.LL */\n+ { pool , P_SC , 4 , 32,\n+ 0xfc007f00, 0xa4005900, 0 , 0,\n+ 0x0 }, /* P.SC */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4006100, &NMD::LDC2 , 0,\n+ CP2_ }, /* LDC2 */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4006900, &NMD::SDC2 , 0,\n+ CP2_ }, /* SDC2 */\n+ { pool , P_LLD , 8 , 32,\n+ 0xfc007f00, 0xa4007100, 0 , 0,\n+ 0x0 }, /* P.LLD */\n+ { pool , P_SCD , 8 , 32,\n+ 0xfc007f00, 0xa4007900, 0 , 0,\n+ 0x0 }, /* P.SCD */\n+};\n+\n+\n+NMD::Pool NMD::P_PREFE[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xffe07f00, 0xa7e01a00, &NMD::SYNCIE , 0,\n+ CP0_ | EVA_ }, /* SYNCIE */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4001a00, &NMD::PREFE , &NMD::PREFE_cond ,\n+ CP0_ | EVA_ }, /* PREFE */\n+};\n+\n+\n+NMD::Pool NMD::P_LLE[4] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f03, 0xa4005200, &NMD::LLE , 0,\n+ CP0_ | EVA_ }, /* LLE */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f03, 0xa4005201, &NMD::LLWPE , 0,\n+ CP0_ | EVA_ }, /* LLWPE */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007f03, 0xa4005202, 0 , 0,\n+ 0x0 }, /* P.LLE~*(2) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007f03, 0xa4005203, 0 , 0,\n+ 0x0 }, /* P.LLE~*(3) */\n+};\n+\n+\n+NMD::Pool NMD::P_SCE[4] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f03, 0xa4005a00, &NMD::SCE , 0,\n+ CP0_ | EVA_ }, /* SCE */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f03, 0xa4005a01, &NMD::SCWPE , 0,\n+ CP0_ | EVA_ }, /* SCWPE */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007f03, 0xa4005a02, 0 , 0,\n+ 0x0 }, /* P.SCE~*(2) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007f03, 0xa4005a03, 0 , 0,\n+ 0x0 }, /* P.SCE~*(3) */\n+};\n+\n+\n+NMD::Pool NMD::P_LS_E0[16] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4000200, &NMD::LBE , 0,\n+ CP0_ | EVA_ }, /* LBE */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4000a00, &NMD::SBE , 0,\n+ CP0_ | EVA_ }, /* SBE */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4001200, &NMD::LBUE , 0,\n+ CP0_ | EVA_ }, /* LBUE */\n+ { pool , P_PREFE , 2 , 32,\n+ 0xfc007f00, 0xa4001a00, 0 , 0,\n+ 0x0 }, /* P.PREFE */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4002200, &NMD::LHE , 0,\n+ CP0_ | EVA_ }, /* LHE */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4002a00, &NMD::SHE , 0,\n+ CP0_ | EVA_ }, /* SHE */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4003200, &NMD::LHUE , 0,\n+ CP0_ | EVA_ }, /* LHUE */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4003a00, &NMD::CACHEE , 0,\n+ CP0_ | EVA_ }, /* CACHEE */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4004200, &NMD::LWE , 0,\n+ CP0_ | EVA_ }, /* LWE */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4004a00, &NMD::SWE , 0,\n+ CP0_ | EVA_ }, /* SWE */\n+ { pool , P_LLE , 4 , 32,\n+ 0xfc007f00, 0xa4005200, 0 , 0,\n+ 0x0 }, /* P.LLE */\n+ { pool , P_SCE , 4 , 32,\n+ 0xfc007f00, 0xa4005a00, 0 , 0,\n+ 0x0 }, /* P.SCE */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4006200, 0 , 0,\n+ 0x0 }, /* P.LS.E0~*(12) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4006a00, 0 , 0,\n+ 0x0 }, /* P.LS.E0~*(13) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4007200, 0 , 0,\n+ 0x0 }, /* P.LS.E0~*(14) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc007f00, 0xa4007a00, 0 , 0,\n+ 0x0 }, /* P.LS.E0~*(15) */\n+};\n+\n+\n+NMD::Pool NMD::P_LS_WM[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc000f00, 0xa4000400, &NMD::LWM , 0,\n+ XMMS_ }, /* LWM */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc000f00, 0xa4000c00, &NMD::SWM , 0,\n+ XMMS_ }, /* SWM */\n+};\n+\n+\n+NMD::Pool NMD::P_LS_UAWM[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc000f00, 0xa4000500, &NMD::UALWM , 0,\n+ XMMS_ }, /* UALWM */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc000f00, 0xa4000d00, &NMD::UASWM , 0,\n+ XMMS_ }, /* UASWM */\n+};\n+\n+\n+NMD::Pool NMD::P_LS_DM[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc000f00, 0xa4000600, &NMD::LDM , 0,\n+ MIPS64_ }, /* LDM */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc000f00, 0xa4000e00, &NMD::SDM , 0,\n+ MIPS64_ }, /* SDM */\n+};\n+\n+\n+NMD::Pool NMD::P_LS_UADM[2] = {\n+ { instruction , 0 , 0 , 32,\n+ 0xfc000f00, 0xa4000700, &NMD::UALDM , 0,\n+ MIPS64_ }, /* UALDM */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc000f00, 0xa4000f00, &NMD::UASDM , 0,\n+ MIPS64_ }, /* UASDM */\n+};\n+\n+\n+NMD::Pool NMD::P_LS_S9[8] = {\n+ { pool , P_LS_S0 , 16 , 32,\n+ 0xfc000700, 0xa4000000, 0 , 0,\n+ 0x0 }, /* P.LS.S0 */\n+ { pool , P_LS_S1 , 16 , 32,\n+ 0xfc000700, 0xa4000100, 0 , 0,\n+ 0x0 }, /* P.LS.S1 */\n+ { pool , P_LS_E0 , 16 , 32,\n+ 0xfc000700, 0xa4000200, 0 , 0,\n+ 0x0 }, /* P.LS.E0 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000700, 0xa4000300, 0 , 0,\n+ 0x0 }, /* P.LS.S9~*(3) */\n+ { pool , P_LS_WM , 2 , 32,\n+ 0xfc000700, 0xa4000400, 0 , 0,\n+ 0x0 }, /* P.LS.WM */\n+ { pool , P_LS_UAWM , 2 , 32,\n+ 0xfc000700, 0xa4000500, 0 , 0,\n+ 0x0 }, /* P.LS.UAWM */\n+ { pool , P_LS_DM , 2 , 32,\n+ 0xfc000700, 0xa4000600, 0 , 0,\n+ 0x0 }, /* P.LS.DM */\n+ { pool , P_LS_UADM , 2 , 32,\n+ 0xfc000700, 0xa4000700, 0 , 0,\n+ 0x0 }, /* P.LS.UADM */\n+};\n+\n+\n+NMD::Pool NMD::P_BAL[2] = {\n+ { branch_instruction , 0 , 0 , 32,\n+ 0xfe000000, 0x28000000, &NMD::BC_32_ , 0,\n+ 0x0 }, /* BC[32] */\n+ { call_instruction , 0 , 0 , 32,\n+ 0xfe000000, 0x2a000000, &NMD::BALC_32_ , 0,\n+ 0x0 }, /* BALC[32] */\n+};\n+\n+\n+NMD::Pool NMD::P_BALRSC[2] = {\n+ { branch_instruction , 0 , 0 , 32,\n+ 0xffe0f000, 0x48008000, &NMD::BRSC , 0,\n+ 0x0 }, /* BRSC */\n+ { call_instruction , 0 , 0 , 32,\n+ 0xfc00f000, 0x48008000, &NMD::BALRSC , &NMD::BALRSC_cond ,\n+ 0x0 }, /* BALRSC */\n+};\n+\n+\n+NMD::Pool NMD::P_J[16] = {\n+ { call_instruction , 0 , 0 , 32,\n+ 0xfc00f000, 0x48000000, &NMD::JALRC_32_ , 0,\n+ 0x0 }, /* JALRC[32] */\n+ { call_instruction , 0 , 0 , 32,\n+ 0xfc00f000, 0x48001000, &NMD::JALRC_HB , 0,\n+ 0x0 }, /* JALRC.HB */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00f000, 0x48002000, 0 , 0,\n+ 0x0 }, /* P.J~*(2) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00f000, 0x48003000, 0 , 0,\n+ 0x0 }, /* P.J~*(3) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00f000, 0x48004000, 0 , 0,\n+ 0x0 }, /* P.J~*(4) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00f000, 0x48005000, 0 , 0,\n+ 0x0 }, /* P.J~*(5) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00f000, 0x48006000, 0 , 0,\n+ 0x0 }, /* P.J~*(6) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00f000, 0x48007000, 0 , 0,\n+ 0x0 }, /* P.J~*(7) */\n+ { pool , P_BALRSC , 2 , 32,\n+ 0xfc00f000, 0x48008000, 0 , 0,\n+ 0x0 }, /* P.BALRSC */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00f000, 0x48009000, 0 , 0,\n+ 0x0 }, /* P.J~*(9) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00f000, 0x4800a000, 0 , 0,\n+ 0x0 }, /* P.J~*(10) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00f000, 0x4800b000, 0 , 0,\n+ 0x0 }, /* P.J~*(11) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00f000, 0x4800c000, 0 , 0,\n+ 0x0 }, /* P.J~*(12) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00f000, 0x4800d000, 0 , 0,\n+ 0x0 }, /* P.J~*(13) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00f000, 0x4800e000, 0 , 0,\n+ 0x0 }, /* P.J~*(14) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00f000, 0x4800f000, 0 , 0,\n+ 0x0 }, /* P.J~*(15) */\n+};\n+\n+\n+NMD::Pool NMD::P_BR3A[32] = {\n+ { branch_instruction , 0 , 0 , 32,\n+ 0xfc1fc000, 0x88004000, &NMD::BC1EQZC , 0,\n+ CP1_ }, /* BC1EQZC */\n+ { branch_instruction , 0 , 0 , 32,\n+ 0xfc1fc000, 0x88014000, &NMD::BC1NEZC , 0,\n+ CP1_ }, /* BC1NEZC */\n+ { branch_instruction , 0 , 0 , 32,\n+ 0xfc1fc000, 0x88024000, &NMD::BC2EQZC , 0,\n+ CP2_ }, /* BC2EQZC */\n+ { branch_instruction , 0 , 0 , 32,\n+ 0xfc1fc000, 0x88034000, &NMD::BC2NEZC , 0,\n+ CP2_ }, /* BC2NEZC */\n+ { branch_instruction , 0 , 0 , 32,\n+ 0xfc1fc000, 0x88044000, &NMD::BPOSGE32C , 0,\n+ DSP_ }, /* BPOSGE32C */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc1fc000, 0x88054000, 0 , 0,\n+ 0x0 }, /* P.BR3A~*(5) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc1fc000, 0x88064000, 0 , 0,\n+ 0x0 }, /* P.BR3A~*(6) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc1fc000, 0x88074000, 0 , 0,\n+ 0x0 }, /* P.BR3A~*(7) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc1fc000, 0x88084000, 0 , 0,\n+ 0x0 }, /* P.BR3A~*(8) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc1fc000, 0x88094000, 0 , 0,\n+ 0x0 }, /* P.BR3A~*(9) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc1fc000, 0x880a4000, 0 , 0,\n+ 0x0 }, /* P.BR3A~*(10) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc1fc000, 0x880b4000, 0 , 0,\n+ 0x0 }, /* P.BR3A~*(11) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc1fc000, 0x880c4000, 0 , 0,\n+ 0x0 }, /* P.BR3A~*(12) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc1fc000, 0x880d4000, 0 , 0,\n+ 0x0 }, /* P.BR3A~*(13) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc1fc000, 0x880e4000, 0 , 0,\n+ 0x0 }, /* P.BR3A~*(14) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc1fc000, 0x880f4000, 0 , 0,\n+ 0x0 }, /* P.BR3A~*(15) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc1fc000, 0x88104000, 0 , 0,\n+ 0x0 }, /* P.BR3A~*(16) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc1fc000, 0x88114000, 0 , 0,\n+ 0x0 }, /* P.BR3A~*(17) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc1fc000, 0x88124000, 0 , 0,\n+ 0x0 }, /* P.BR3A~*(18) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc1fc000, 0x88134000, 0 , 0,\n+ 0x0 }, /* P.BR3A~*(19) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc1fc000, 0x88144000, 0 , 0,\n+ 0x0 }, /* P.BR3A~*(20) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc1fc000, 0x88154000, 0 , 0,\n+ 0x0 }, /* P.BR3A~*(21) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc1fc000, 0x88164000, 0 , 0,\n+ 0x0 }, /* P.BR3A~*(22) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc1fc000, 0x88174000, 0 , 0,\n+ 0x0 }, /* P.BR3A~*(23) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc1fc000, 0x88184000, 0 , 0,\n+ 0x0 }, /* P.BR3A~*(24) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc1fc000, 0x88194000, 0 , 0,\n+ 0x0 }, /* P.BR3A~*(25) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc1fc000, 0x881a4000, 0 , 0,\n+ 0x0 }, /* P.BR3A~*(26) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc1fc000, 0x881b4000, 0 , 0,\n+ 0x0 }, /* P.BR3A~*(27) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc1fc000, 0x881c4000, 0 , 0,\n+ 0x0 }, /* P.BR3A~*(28) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc1fc000, 0x881d4000, 0 , 0,\n+ 0x0 }, /* P.BR3A~*(29) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc1fc000, 0x881e4000, 0 , 0,\n+ 0x0 }, /* P.BR3A~*(30) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc1fc000, 0x881f4000, 0 , 0,\n+ 0x0 }, /* P.BR3A~*(31) */\n+};\n+\n+\n+NMD::Pool NMD::P_BR1[4] = {\n+ { branch_instruction , 0 , 0 , 32,\n+ 0xfc00c000, 0x88000000, &NMD::BEQC_32_ , 0,\n+ 0x0 }, /* BEQC[32] */\n+ { pool , P_BR3A , 32 , 32,\n+ 0xfc00c000, 0x88004000, 0 , 0,\n+ 0x0 }, /* P.BR3A */\n+ { branch_instruction , 0 , 0 , 32,\n+ 0xfc00c000, 0x88008000, &NMD::BGEC , 0,\n+ 0x0 }, /* BGEC */\n+ { branch_instruction , 0 , 0 , 32,\n+ 0xfc00c000, 0x8800c000, &NMD::BGEUC , 0,\n+ 0x0 }, /* BGEUC */\n+};\n+\n+\n+NMD::Pool NMD::P_BR2[4] = {\n+ { branch_instruction , 0 , 0 , 32,\n+ 0xfc00c000, 0xa8000000, &NMD::BNEC_32_ , 0,\n+ 0x0 }, /* BNEC[32] */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc00c000, 0xa8004000, 0 , 0,\n+ 0x0 }, /* P.BR2~*(1) */\n+ { branch_instruction , 0 , 0 , 32,\n+ 0xfc00c000, 0xa8008000, &NMD::BLTC , 0,\n+ 0x0 }, /* BLTC */\n+ { branch_instruction , 0 , 0 , 32,\n+ 0xfc00c000, 0xa800c000, &NMD::BLTUC , 0,\n+ 0x0 }, /* BLTUC */\n+};\n+\n+\n+NMD::Pool NMD::P_BRI[8] = {\n+ { branch_instruction , 0 , 0 , 32,\n+ 0xfc1c0000, 0xc8000000, &NMD::BEQIC , 0,\n+ 0x0 }, /* BEQIC */\n+ { branch_instruction , 0 , 0 , 32,\n+ 0xfc1c0000, 0xc8040000, &NMD::BBEQZC , 0,\n+ XMMS_ }, /* BBEQZC */\n+ { branch_instruction , 0 , 0 , 32,\n+ 0xfc1c0000, 0xc8080000, &NMD::BGEIC , 0,\n+ 0x0 }, /* BGEIC */\n+ { branch_instruction , 0 , 0 , 32,\n+ 0xfc1c0000, 0xc80c0000, &NMD::BGEIUC , 0,\n+ 0x0 }, /* BGEIUC */\n+ { branch_instruction , 0 , 0 , 32,\n+ 0xfc1c0000, 0xc8100000, &NMD::BNEIC , 0,\n+ 0x0 }, /* BNEIC */\n+ { branch_instruction , 0 , 0 , 32,\n+ 0xfc1c0000, 0xc8140000, &NMD::BBNEZC , 0,\n+ XMMS_ }, /* BBNEZC */\n+ { branch_instruction , 0 , 0 , 32,\n+ 0xfc1c0000, 0xc8180000, &NMD::BLTIC , 0,\n+ 0x0 }, /* BLTIC */\n+ { branch_instruction , 0 , 0 , 32,\n+ 0xfc1c0000, 0xc81c0000, &NMD::BLTIUC , 0,\n+ 0x0 }, /* BLTIUC */\n+};\n+\n+\n+NMD::Pool NMD::P32[32] = {\n+ { pool , P_ADDIU , 2 , 32,\n+ 0xfc000000, 0x00000000, 0 , 0,\n+ 0x0 }, /* P.ADDIU */\n+ { pool , P32A , 8 , 32,\n+ 0xfc000000, 0x20000000, 0 , 0,\n+ 0x0 }, /* P32A */\n+ { pool , P_GP_W , 4 , 32,\n+ 0xfc000000, 0x40000000, 0 , 0,\n+ 0x0 }, /* P.GP.W */\n+ { pool , POOL48I , 32 , 48,\n+ 0xfc0000000000ull, 0x600000000000ull, 0 , 0,\n+ 0x0 }, /* POOL48I */\n+ { pool , P_U12 , 16 , 32,\n+ 0xfc000000, 0x80000000, 0 , 0,\n+ 0x0 }, /* P.U12 */\n+ { pool , POOL32F , 8 , 32,\n+ 0xfc000000, 0xa0000000, 0 , 0,\n+ CP1_ }, /* POOL32F */\n+ { pool , POOL32S , 8 , 32,\n+ 0xfc000000, 0xc0000000, 0 , 0,\n+ 0x0 }, /* POOL32S */\n+ { pool , P_LUI , 2 , 32,\n+ 0xfc000000, 0xe0000000, 0 , 0,\n+ 0x0 }, /* P.LUI */\n+ { instruction , 0 , 0 , 32,\n+ 0xfc000000, 0x04000000, &NMD::ADDIUPC_32_ , 0,\n+ 0x0 }, /* ADDIUPC[32] */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000000, 0x24000000, 0 , 0,\n+ 0x0 }, /* P32~*(5) */\n+ { pool , P_GP_BH , 8 , 32,\n+ 0xfc000000, 0x44000000, 0 , 0,\n+ 0x0 }, /* P.GP.BH */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000000, 0x64000000, 0 , 0,\n+ 0x0 }, /* P32~*(13) */\n+ { pool , P_LS_U12 , 16 , 32,\n+ 0xfc000000, 0x84000000, 0 , 0,\n+ 0x0 }, /* P.LS.U12 */\n+ { pool , P_LS_S9 , 8 , 32,\n+ 0xfc000000, 0xa4000000, 0 , 0,\n+ 0x0 }, /* P.LS.S9 */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000000, 0xc4000000, 0 , 0,\n+ 0x0 }, /* P32~*(25) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000000, 0xe4000000, 0 , 0,\n+ 0x0 }, /* P32~*(29) */\n+ { call_instruction , 0 , 0 , 32,\n+ 0xfc000000, 0x08000000, &NMD::MOVE_BALC , 0,\n+ XMMS_ }, /* MOVE.BALC */\n+ { pool , P_BAL , 2 , 32,\n+ 0xfc000000, 0x28000000, 0 , 0,\n+ 0x0 }, /* P.BAL */\n+ { pool , P_J , 16 , 32,\n+ 0xfc000000, 0x48000000, 0 , 0,\n+ 0x0 }, /* P.J */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000000, 0x68000000, 0 , 0,\n+ 0x0 }, /* P32~*(14) */\n+ { pool , P_BR1 , 4 , 32,\n+ 0xfc000000, 0x88000000, 0 , 0,\n+ 0x0 }, /* P.BR1 */\n+ { pool , P_BR2 , 4 , 32,\n+ 0xfc000000, 0xa8000000, 0 , 0,\n+ 0x0 }, /* P.BR2 */\n+ { pool , P_BRI , 8 , 32,\n+ 0xfc000000, 0xc8000000, 0 , 0,\n+ 0x0 }, /* P.BRI */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000000, 0xe8000000, 0 , 0,\n+ 0x0 }, /* P32~*(30) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000000, 0x0c000000, 0 , 0,\n+ 0x0 }, /* P32~*(3) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000000, 0x2c000000, 0 , 0,\n+ 0x0 }, /* P32~*(7) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000000, 0x4c000000, 0 , 0,\n+ 0x0 }, /* P32~*(11) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000000, 0x6c000000, 0 , 0,\n+ 0x0 }, /* P32~*(15) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000000, 0x8c000000, 0 , 0,\n+ 0x0 }, /* P32~*(19) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000000, 0xac000000, 0 , 0,\n+ 0x0 }, /* P32~*(23) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000000, 0xcc000000, 0 , 0,\n+ 0x0 }, /* P32~*(27) */\n+ { reserved_block , 0 , 0 , 32,\n+ 0xfc000000, 0xec000000, 0 , 0,\n+ 0x0 }, /* P32~*(31) */\n+};\n+\n+\n+NMD::Pool NMD::P16_SYSCALL[2] = {\n+ { instruction , 0 , 0 , 16,\n+ 0xfffc , 0x1008 , &NMD::SYSCALL_16_ , 0,\n+ 0x0 }, /* SYSCALL[16] */\n+ { instruction , 0 , 0 , 16,\n+ 0xfffc , 0x100c , &NMD::HYPCALL_16_ , 0,\n+ CP0_ | VZ_ }, /* HYPCALL[16] */\n+};\n+\n+\n+NMD::Pool NMD::P16_RI[4] = {\n+ { reserved_block , 0 , 0 , 16,\n+ 0xfff8 , 0x1000 , 0 , 0,\n+ 0x0 }, /* P16.RI~*(0) */\n+ { pool , P16_SYSCALL , 2 , 16,\n+ 0xfff8 , 0x1008 , 0 , 0,\n+ 0x0 }, /* P16.SYSCALL */\n+ { instruction , 0 , 0 , 16,\n+ 0xfff8 , 0x1010 , &NMD::BREAK_16_ , 0,\n+ 0x0 }, /* BREAK[16] */\n+ { instruction , 0 , 0 , 16,\n+ 0xfff8 , 0x1018 , &NMD::SDBBP_16_ , 0,\n+ EJTAG_ }, /* SDBBP[16] */\n+};\n+\n+\n+NMD::Pool NMD::P16_MV[2] = {\n+ { pool , P16_RI , 4 , 16,\n+ 0xffe0 , 0x1000 , 0 , 0,\n+ 0x0 }, /* P16.RI */\n+ { instruction , 0 , 0 , 16,\n+ 0xfc00 , 0x1000 , &NMD::MOVE , &NMD::MOVE_cond ,\n+ 0x0 }, /* MOVE */\n+};\n+\n+\n+NMD::Pool NMD::P16_SHIFT[2] = {\n+ { instruction , 0 , 0 , 16,\n+ 0xfc08 , 0x3000 , &NMD::SLL_16_ , 0,\n+ 0x0 }, /* SLL[16] */\n+ { instruction , 0 , 0 , 16,\n+ 0xfc08 , 0x3008 , &NMD::SRL_16_ , 0,\n+ 0x0 }, /* SRL[16] */\n+};\n+\n+\n+NMD::Pool NMD::POOL16C_00[4] = {\n+ { instruction , 0 , 0 , 16,\n+ 0xfc0f , 0x5000 , &NMD::NOT_16_ , 0,\n+ 0x0 }, /* NOT[16] */\n+ { instruction , 0 , 0 , 16,\n+ 0xfc0f , 0x5004 , &NMD::XOR_16_ , 0,\n+ 0x0 }, /* XOR[16] */\n+ { instruction , 0 , 0 , 16,\n+ 0xfc0f , 0x5008 , &NMD::AND_16_ , 0,\n+ 0x0 }, /* AND[16] */\n+ { instruction , 0 , 0 , 16,\n+ 0xfc0f , 0x500c , &NMD::OR_16_ , 0,\n+ 0x0 }, /* OR[16] */\n+};\n+\n+\n+NMD::Pool NMD::POOL16C_0[2] = {\n+ { pool , POOL16C_00 , 4 , 16,\n+ 0xfc03 , 0x5000 , 0 , 0,\n+ 0x0 }, /* POOL16C_00 */\n+ { reserved_block , 0 , 0 , 16,\n+ 0xfc03 , 0x5002 , 0 , 0,\n+ 0x0 }, /* POOL16C_0~*(1) */\n+};\n+\n+\n+NMD::Pool NMD::P16C[2] = {\n+ { pool , POOL16C_0 , 2 , 16,\n+ 0xfc01 , 0x5000 , 0 , 0,\n+ 0x0 }, /* POOL16C_0 */\n+ { instruction , 0 , 0 , 16,\n+ 0xfc01 , 0x5001 , &NMD::LWXS_16_ , 0,\n+ 0x0 }, /* LWXS[16] */\n+};\n+\n+\n+NMD::Pool NMD::P16_A1[2] = {\n+ { reserved_block , 0 , 0 , 16,\n+ 0xfc40 , 0x7000 , 0 , 0,\n+ 0x0 }, /* P16.A1~*(0) */\n+ { instruction , 0 , 0 , 16,\n+ 0xfc40 , 0x7040 , &NMD::ADDIU_R1_SP_ , 0,\n+ 0x0 }, /* ADDIU[R1.SP] */\n+};\n+\n+\n+NMD::Pool NMD::P_ADDIU_RS5_[2] = {\n+ { instruction , 0 , 0 , 16,\n+ 0xffe8 , 0x9008 , &NMD::NOP_16_ , 0,\n+ 0x0 }, /* NOP[16] */\n+ { instruction , 0 , 0 , 16,\n+ 0xfc08 , 0x9008 , &NMD::ADDIU_RS5_ , &NMD::ADDIU_RS5__cond ,\n+ 0x0 }, /* ADDIU[RS5] */\n+};\n+\n+\n+NMD::Pool NMD::P16_A2[2] = {\n+ { instruction , 0 , 0 , 16,\n+ 0xfc08 , 0x9000 , &NMD::ADDIU_R2_ , 0,\n+ 0x0 }, /* ADDIU[R2] */\n+ { pool , P_ADDIU_RS5_ , 2 , 16,\n+ 0xfc08 , 0x9008 , 0 , 0,\n+ 0x0 }, /* P.ADDIU[RS5] */\n+};\n+\n+\n+NMD::Pool NMD::P16_ADDU[2] = {\n+ { instruction , 0 , 0 , 16,\n+ 0xfc01 , 0xb000 , &NMD::ADDU_16_ , 0,\n+ 0x0 }, /* ADDU[16] */\n+ { instruction , 0 , 0 , 16,\n+ 0xfc01 , 0xb001 , &NMD::SUBU_16_ , 0,\n+ 0x0 }, /* SUBU[16] */\n+};\n+\n+\n+NMD::Pool NMD::P16_JRC[2] = {\n+ { branch_instruction , 0 , 0 , 16,\n+ 0xfc1f , 0xd800 , &NMD::JRC , 0,\n+ 0x0 }, /* JRC */\n+ { call_instruction , 0 , 0 , 16,\n+ 0xfc1f , 0xd810 , &NMD::JALRC_16_ , 0,\n+ 0x0 }, /* JALRC[16] */\n+};\n+\n+\n+NMD::Pool NMD::P16_BR1[2] = {\n+ { branch_instruction , 0 , 0 , 16,\n+ 0xfc00 , 0xd800 , &NMD::BEQC_16_ , &NMD::BEQC_16__cond ,\n+ XMMS_ }, /* BEQC[16] */\n+ { branch_instruction , 0 , 0 , 16,\n+ 0xfc00 , 0xd800 , &NMD::BNEC_16_ , &NMD::BNEC_16__cond ,\n+ XMMS_ }, /* BNEC[16] */\n+};\n+\n+\n+NMD::Pool NMD::P16_BR[2] = {\n+ { pool , P16_JRC , 2 , 16,\n+ 0xfc0f , 0xd800 , 0 , 0,\n+ 0x0 }, /* P16.JRC */\n+ { pool , P16_BR1 , 2 , 16,\n+ 0xfc00 , 0xd800 , 0 , &NMD::P16_BR1_cond ,\n+ 0x0 }, /* P16.BR1 */\n+};\n+\n+\n+NMD::Pool NMD::P16_SR[2] = {\n+ { instruction , 0 , 0 , 16,\n+ 0xfd00 , 0x1c00 , &NMD::SAVE_16_ , 0,\n+ 0x0 }, /* SAVE[16] */\n+ { return_instruction , 0 , 0 , 16,\n+ 0xfd00 , 0x1d00 , &NMD::RESTORE_JRC_16_ , 0,\n+ 0x0 }, /* RESTORE.JRC[16] */\n+};\n+\n+\n+NMD::Pool NMD::P16_4X4[4] = {\n+ { instruction , 0 , 0 , 16,\n+ 0xfd08 , 0x3c00 , &NMD::ADDU_4X4_ , 0,\n+ XMMS_ }, /* ADDU[4X4] */\n+ { instruction , 0 , 0 , 16,\n+ 0xfd08 , 0x3c08 , &NMD::MUL_4X4_ , 0,\n+ XMMS_ }, /* MUL[4X4] */\n+ { reserved_block , 0 , 0 , 16,\n+ 0xfd08 , 0x3d00 , 0 , 0,\n+ 0x0 }, /* P16.4X4~*(2) */\n+ { reserved_block , 0 , 0 , 16,\n+ 0xfd08 , 0x3d08 , 0 , 0,\n+ 0x0 }, /* P16.4X4~*(3) */\n+};\n+\n+\n+NMD::Pool NMD::P16_LB[4] = {\n+ { instruction , 0 , 0 , 16,\n+ 0xfc0c , 0x5c00 , &NMD::LB_16_ , 0,\n+ 0x0 }, /* LB[16] */\n+ { instruction , 0 , 0 , 16,\n+ 0xfc0c , 0x5c04 , &NMD::SB_16_ , 0,\n+ 0x0 }, /* SB[16] */\n+ { instruction , 0 , 0 , 16,\n+ 0xfc0c , 0x5c08 , &NMD::LBU_16_ , 0,\n+ 0x0 }, /* LBU[16] */\n+ { reserved_block , 0 , 0 , 16,\n+ 0xfc0c , 0x5c0c , 0 , 0,\n+ 0x0 }, /* P16.LB~*(3) */\n+};\n+\n+\n+NMD::Pool NMD::P16_LH[4] = {\n+ { instruction , 0 , 0 , 16,\n+ 0xfc09 , 0x7c00 , &NMD::LH_16_ , 0,\n+ 0x0 }, /* LH[16] */\n+ { instruction , 0 , 0 , 16,\n+ 0xfc09 , 0x7c01 , &NMD::SH_16_ , 0,\n+ 0x0 }, /* SH[16] */\n+ { instruction , 0 , 0 , 16,\n+ 0xfc09 , 0x7c08 , &NMD::LHU_16_ , 0,\n+ 0x0 }, /* LHU[16] */\n+ { reserved_block , 0 , 0 , 16,\n+ 0xfc09 , 0x7c09 , 0 , 0,\n+ 0x0 }, /* P16.LH~*(3) */\n+};\n+\n+\n+NMD::Pool NMD::P16[32] = {\n+ { pool , P16_MV , 2 , 16,\n+ 0xfc00 , 0x1000 , 0 , 0,\n+ 0x0 }, /* P16.MV */\n+ { pool , P16_SHIFT , 2 , 16,\n+ 0xfc00 , 0x3000 , 0 , 0,\n+ 0x0 }, /* P16.SHIFT */\n+ { pool , P16C , 2 , 16,\n+ 0xfc00 , 0x5000 , 0 , 0,\n+ 0x0 }, /* P16C */\n+ { pool , P16_A1 , 2 , 16,\n+ 0xfc00 , 0x7000 , 0 , 0,\n+ 0x0 }, /* P16.A1 */\n+ { pool , P16_A2 , 2 , 16,\n+ 0xfc00 , 0x9000 , 0 , 0,\n+ 0x0 }, /* P16.A2 */\n+ { pool , P16_ADDU , 2 , 16,\n+ 0xfc00 , 0xb000 , 0 , 0,\n+ 0x0 }, /* P16.ADDU */\n+ { instruction , 0 , 0 , 16,\n+ 0xfc00 , 0xd000 , &NMD::LI_16_ , 0,\n+ 0x0 }, /* LI[16] */\n+ { instruction , 0 , 0 , 16,\n+ 0xfc00 , 0xf000 , &NMD::ANDI_16_ , 0,\n+ 0x0 }, /* ANDI[16] */\n+ { instruction , 0 , 0 , 16,\n+ 0xfc00 , 0x1400 , &NMD::LW_16_ , 0,\n+ 0x0 }, /* LW[16] */\n+ { instruction , 0 , 0 , 16,\n+ 0xfc00 , 0x3400 , &NMD::LW_SP_ , 0,\n+ 0x0 }, /* LW[SP] */\n+ { instruction , 0 , 0 , 16,\n+ 0xfc00 , 0x5400 , &NMD::LW_GP16_ , 0,\n+ 0x0 }, /* LW[GP16] */\n+ { instruction , 0 , 0 , 16,\n+ 0xfc00 , 0x7400 , &NMD::LW_4X4_ , 0,\n+ XMMS_ }, /* LW[4X4] */\n+ { instruction , 0 , 0 , 16,\n+ 0xfc00 , 0x9400 , &NMD::SW_16_ , 0,\n+ 0x0 }, /* SW[16] */\n+ { instruction , 0 , 0 , 16,\n+ 0xfc00 , 0xb400 , &NMD::SW_SP_ , 0,\n+ 0x0 }, /* SW[SP] */\n+ { instruction , 0 , 0 , 16,\n+ 0xfc00 , 0xd400 , &NMD::SW_GP16_ , 0,\n+ 0x0 }, /* SW[GP16] */\n+ { instruction , 0 , 0 , 16,\n+ 0xfc00 , 0xf400 , &NMD::SW_4X4_ , 0,\n+ XMMS_ }, /* SW[4X4] */\n+ { branch_instruction , 0 , 0 , 16,\n+ 0xfc00 , 0x1800 , &NMD::BC_16_ , 0,\n+ 0x0 }, /* BC[16] */\n+ { call_instruction , 0 , 0 , 16,\n+ 0xfc00 , 0x3800 , &NMD::BALC_16_ , 0,\n+ 0x0 }, /* BALC[16] */\n+ { reserved_block , 0 , 0 , 16,\n+ 0xfc00 , 0x5800 , 0 , 0,\n+ 0x0 }, /* P16~*(10) */\n+ { reserved_block , 0 , 0 , 16,\n+ 0xfc00 , 0x7800 , 0 , 0,\n+ 0x0 }, /* P16~*(14) */\n+ { branch_instruction , 0 , 0 , 16,\n+ 0xfc00 , 0x9800 , &NMD::BEQZC_16_ , 0,\n+ 0x0 }, /* BEQZC[16] */\n+ { branch_instruction , 0 , 0 , 16,\n+ 0xfc00 , 0xb800 , &NMD::BNEZC_16_ , 0,\n+ 0x0 }, /* BNEZC[16] */\n+ { pool , P16_BR , 2 , 16,\n+ 0xfc00 , 0xd800 , 0 , 0,\n+ 0x0 }, /* P16.BR */\n+ { reserved_block , 0 , 0 , 16,\n+ 0xfc00 , 0xf800 , 0 , 0,\n+ 0x0 }, /* P16~*(30) */\n+ { pool , P16_SR , 2 , 16,\n+ 0xfc00 , 0x1c00 , 0 , 0,\n+ 0x0 }, /* P16.SR */\n+ { pool , P16_4X4 , 4 , 16,\n+ 0xfc00 , 0x3c00 , 0 , 0,\n+ 0x0 }, /* P16.4X4 */\n+ { pool , P16_LB , 4 , 16,\n+ 0xfc00 , 0x5c00 , 0 , 0,\n+ 0x0 }, /* P16.LB */\n+ { pool , P16_LH , 4 , 16,\n+ 0xfc00 , 0x7c00 , 0 , 0,\n+ 0x0 }, /* P16.LH */\n+ { reserved_block , 0 , 0 , 16,\n+ 0xfc00 , 0x9c00 , 0 , 0,\n+ 0x0 }, /* P16~*(19) */\n+ { instruction , 0 , 0 , 16,\n+ 0xfc00 , 0xbc00 , &NMD::MOVEP , 0,\n+ XMMS_ }, /* MOVEP */\n+ { reserved_block , 0 , 0 , 16,\n+ 0xfc00 , 0xdc00 , 0 , 0,\n+ 0x0 }, /* P16~*(27) */\n+ { instruction , 0 , 0 , 16,\n+ 0xfc00 , 0xfc00 , &NMD::MOVEP_REV_ , 0,\n+ XMMS_ }, /* MOVEP[REV] */\n+};\n+\n+\n+NMD::Pool NMD::MAJOR[2] = {\n+ { pool , P32 , 32 , 32,\n+ 0x10000000, 0x00000000, 0 , 0,\n+ 0x0 }, /* P32 */\n+ { pool , P16 , 32 , 16,\n+ 0x1000 , 0x1000 , 0 , 0,\n+ 0x0 }, /* P16 */\n+};\n+\n+\n+extern \"C\"\n+{\n+ int nanomips_dis(char *buf,\n+ unsigned address,\n+ unsigned short one,\n+ unsigned short two,\n+ unsigned short three)\n+ {\n+ std::string disasm;\n+ uint16 bits[3] = {one, two, three};\n+\n+ NMD::TABLE_ENTRY_TYPE type;\n+ NMD d(address, NMD::ALL_ATTRIBUTES);\n+ int size = d.Disassemble(bits, disasm, type);\n+\n+ strcpy(buf, disasm.c_str());\n+ return size;\n+ }\n+}\ndiff --git a/disas/nanomips.h b/disas/nanomips.h\nnew file mode 100644\nindex 0000000..9f5bc9d\n--- /dev/null\n+++ b/disas/nanomips.h\n@@ -0,0 +1,1208 @@\n+\n+#ifndef NANOMIPS_DISASSEMBLER_H\n+#define NANOMIPS_DISASSEMBLER_H\n+\n+#include <string>\n+#ifdef INCLUDE_STANDALONE_UNIT_TEST\n+typedef unsigned short uint16;\n+typedef unsigned int uint32;\n+typedef long long int64;\n+typedef unsigned long long uint64;\n+\n+namespace img\n+{\n+ typedef unsigned long long address;\n+}\n+#else\n+#include \"imgleeds/imgleeds/address.h\"\n+#endif\n+\n+\n+\n+class NMD\n+{\n+public:\n+ enum TABLE_ENTRY_TYPE {\n+ instruction,\n+ call_instruction,\n+ branch_instruction,\n+ return_instruction,\n+ reserved_block,\n+ pool,\n+ };\n+ enum TABLE_ATTRIBUTE_TYPE {\n+ MIPS64_ = 0x00000001,\n+ XNP_ = 0x00000002,\n+ XMMS_ = 0x00000004,\n+ EVA_ = 0x00000008,\n+ DSP_ = 0x00000010,\n+ MT_ = 0x00000020,\n+ EJTAG_ = 0x00000040,\n+ TLBINV_ = 0x00000080,\n+ CP0_ = 0x00000100,\n+ CP1_ = 0x00000200,\n+ CP2_ = 0x00000400,\n+ UDI_ = 0x00000800,\n+ MCU_ = 0x00001000,\n+ VZ_ = 0x00002000,\n+ TLB_ = 0x00004000,\n+ MVH_ = 0x00008000,\n+ ALL_ATTRIBUTES = 0xffffffffull,\n+ };\n+\n+\n+ NMD(img::address pc, TABLE_ATTRIBUTE_TYPE requested_instruction_catagories)\n+ : m_pc(pc)\n+ , m_requested_instruction_catagories(requested_instruction_catagories)\n+ {\n+ }\n+\n+ int Disassemble(const uint16 *data, std::string & dis,\n+ TABLE_ENTRY_TYPE & type);\n+\n+private:\n+ img::address m_pc;\n+ TABLE_ATTRIBUTE_TYPE m_requested_instruction_catagories;\n+\n+ typedef std::string\n+ (NMD:: *disassembly_function)(uint64 instruction);\n+ typedef bool\n+ (NMD:: *conditional_function)(uint64 instruction);\n+\n+ struct Pool {\n+ TABLE_ENTRY_TYPE type;\n+ struct Pool *next_table;\n+ int next_table_size;\n+ int instructions_size;\n+ uint64 mask;\n+ uint64 value;\n+ disassembly_function disassembly;\n+ conditional_function condition;\n+ uint64 attributes;\n+ };\n+\n+ uint64 extract_op_code_value(const uint16 *data, int size);\n+ int Disassemble(const uint16 *data, std::string & dis,\n+ TABLE_ENTRY_TYPE & type, const Pool *table, int table_size);\n+\n+ uint64 renumber_registers(uint64 index, uint64 *register_list,\n+ size_t register_list_size);\n+ uint64 encode_gpr3(uint64 d);\n+ uint64 encode_gpr3_store(uint64 d);\n+ uint64 encode_rd1_from_rd(uint64 d);\n+ uint64 encode_gpr4_zero(uint64 d);\n+ uint64 encode_gpr4(uint64 d);\n+ uint64 encode_rd2_reg1(uint64 d);\n+ uint64 encode_rd2_reg2(uint64 d);\n+\n+ uint64 copy(uint64 d);\n+ int64 copy(int64 d);\n+ int64 neg_copy(uint64 d);\n+ int64 neg_copy(int64 d);\n+ uint64 encode_rs3_and_check_rs3_ge_rt3(uint64 d);\n+ uint64 encode_rs3_and_check_rs3_lt_rt3(uint64 d);\n+ uint64 encode_s_from_address(uint64 d);\n+ uint64 encode_u_from_address(uint64 d);\n+ uint64 encode_s_from_s_hi(uint64 d);\n+ uint64 encode_count3_from_count(uint64 d);\n+ uint64 encode_shift3_from_shift(uint64 d);\n+ int64 encode_eu_from_s_li16(uint64 d);\n+ uint64 encode_msbd_from_size(uint64 d);\n+ uint64 encode_eu_from_u_andi16(uint64 d);\n+\n+ uint64 encode_msbd_from_pos_and_size(uint64 d);\n+\n+ uint64 encode_rt1_from_rt(uint64 d);\n+ uint64 encode_lsb_from_pos_and_size(uint64 d);\n+\n+ std::string save_restore_list(uint64 rt, uint64 count, uint64 gp);\n+\n+ std::string GPR(uint64 reg);\n+ std::string FPR(uint64 reg);\n+ std::string AC(uint64 reg);\n+ std::string IMMEDIATE(uint64 value);\n+ std::string IMMEDIATE(int64 value);\n+ std::string CPR(uint64 reg);\n+ std::string ADDRESS(uint64 value, int instruction_size);\n+\n+ uint64 extr_codeil0il0bs19Fmsb18(\n+ uint64 instruction);\n+ uint64 extr_shift3il0il0bs3Fmsb2(\n+ uint64 instruction);\n+ uint64 extr_uil3il3bs9Fmsb11(\n+ uint64 instruction);\n+ uint64 extr_countil0il0bs4Fmsb3(\n+ uint64 instruction);\n+ uint64 extr_rtz3il7il0bs3Fmsb2(\n+ uint64 instruction);\n+ uint64 extr_uil1il1bs17Fmsb17(\n+ uint64 instruction);\n+ int64 extr_sil11il0bs10Tmsb9(\n+ uint64 instruction);\n+ int64 extr_sil0il11bs1_il1il1bs10Tmsb11(\n+ uint64 instruction);\n+ uint64 extr_uil10il0bs1Fmsb0(\n+ uint64 instruction);\n+ uint64 extr_rtz4il21il0bs3_il25il3bs1Fmsb3(\n+ uint64 instruction);\n+ uint64 extr_sail11il0bs5Fmsb4(\n+ uint64 instruction);\n+ uint64 extr_shiftil0il0bs5Fmsb4(\n+ uint64 instruction);\n+ uint64 extr_shiftxil7il1bs4Fmsb4(\n+ uint64 instruction);\n+ uint64 extr_hintil21il0bs5Fmsb4(\n+ uint64 instruction);\n+ uint64 extr_count3il12il0bs3Fmsb2(\n+ uint64 instruction);\n+ int64 extr_sil0il31bs1_il2il21bs10_il12il12bs9Tmsb31(\n+ uint64 instruction);\n+ int64 extr_sil0il7bs1_il1il1bs6Tmsb7(\n+ uint64 instruction);\n+ uint64 extr_u2il9il0bs2Fmsb1(\n+ uint64 instruction);\n+ uint64 extr_codeil16il0bs10Fmsb9(\n+ uint64 instruction);\n+ uint64 extr_rsil16il0bs5Fmsb4(\n+ uint64 instruction);\n+ uint64 extr_uil1il1bs2Fmsb2(\n+ uint64 instruction);\n+ uint64 extr_stripeil6il0bs1Fmsb0(\n+ uint64 instruction);\n+ uint64 extr_xil17il0bs1Fmsb0(\n+ uint64 instruction);\n+ uint64 extr_xil2il0bs1_il15il0bs1Fmsb0(\n+ uint64 instruction);\n+ uint64 extr_acil14il0bs2Fmsb1(\n+ uint64 instruction);\n+ uint64 extr_shiftil16il0bs5Fmsb4(\n+ uint64 instruction);\n+ uint64 extr_rd1il24il0bs1Fmsb0(\n+ uint64 instruction);\n+ int64 extr_sil0il10bs1_il1il1bs9Tmsb10(\n+ uint64 instruction);\n+ uint64 extr_euil0il0bs7Fmsb6(\n+ uint64 instruction);\n+ uint64 extr_shiftil0il0bs6Fmsb5(\n+ uint64 instruction);\n+ uint64 extr_xil10il0bs6Fmsb5(\n+ uint64 instruction);\n+ uint64 extr_countil16il0bs4Fmsb3(\n+ uint64 instruction);\n+ uint64 extr_codeil0il0bs3Fmsb2(\n+ uint64 instruction);\n+ uint64 extr_xil10il0bs4_il22il0bs4Fmsb3(\n+ uint64 instruction);\n+ uint64 extr_uil0il0bs12Fmsb11(\n+ uint64 instruction);\n+ uint64 extr_rsil0il0bs5Fmsb4(\n+ uint64 instruction);\n+ uint64 extr_uil3il3bs18Fmsb20(\n+ uint64 instruction);\n+ uint64 extr_xil12il0bs1Fmsb0(\n+ uint64 instruction);\n+ uint64 extr_uil0il2bs4Fmsb5(\n+ uint64 instruction);\n+ uint64 extr_cofunil3il0bs23Fmsb22(\n+ uint64 instruction);\n+ uint64 extr_uil0il2bs3Fmsb4(\n+ uint64 instruction);\n+ uint64 extr_xil10il0bs1Fmsb0(\n+ uint64 instruction);\n+ uint64 extr_rd3il1il0bs3Fmsb2(\n+ uint64 instruction);\n+ uint64 extr_sail12il0bs4Fmsb3(\n+ uint64 instruction);\n+ uint64 extr_rtil21il0bs5Fmsb4(\n+ uint64 instruction);\n+ uint64 extr_ruil3il0bs5Fmsb4(\n+ uint64 instruction);\n+ uint64 extr_xil21il0bs5Fmsb4(\n+ uint64 instruction);\n+ uint64 extr_xil9il0bs3Fmsb2(\n+ uint64 instruction);\n+ uint64 extr_uil0il0bs18Fmsb17(\n+ uint64 instruction);\n+ uint64 extr_xil14il0bs1_il15il0bs1Fmsb0(\n+ uint64 instruction);\n+ uint64 extr_rsz4il0il0bs3_il4il3bs1Fmsb3(\n+ uint64 instruction);\n+ uint64 extr_xil24il0bs1Fmsb0(\n+ uint64 instruction);\n+ int64 extr_sil0il21bs1_il1il1bs20Tmsb21(\n+ uint64 instruction);\n+ uint64 extr_opil3il0bs23Fmsb22(\n+ uint64 instruction);\n+ uint64 extr_rs4il0il0bs3_il4il3bs1Fmsb3(\n+ uint64 instruction);\n+ uint64 extr_bitil21il0bs3Fmsb2(\n+ uint64 instruction);\n+ uint64 extr_rtil37il0bs5Fmsb4(\n+ uint64 instruction);\n+ int64 extr_sil16il0bs6Tmsb5(\n+ uint64 instruction);\n+ uint64 extr_xil6il0bs3_il10il0bs1Fmsb2(\n+ uint64 instruction);\n+ uint64 extr_rd2il3il1bs1_il8il0bs1Fmsb1(\n+ uint64 instruction);\n+ uint64 extr_xil16il0bs5Fmsb4(\n+ uint64 instruction);\n+ uint64 extr_codeil0il0bs18Fmsb17(\n+ uint64 instruction);\n+ uint64 extr_xil0il0bs12Fmsb11(\n+ uint64 instruction);\n+ uint64 extr_sizeil16il0bs5Fmsb4(\n+ uint64 instruction);\n+ int64 extr_sil2il2bs6_il15il8bs1Tmsb8(\n+ uint64 instruction);\n+ uint64 extr_uil0il0bs16Fmsb15(\n+ uint64 instruction);\n+ uint64 extr_fsil16il0bs5Fmsb4(\n+ uint64 instruction);\n+ int64 extr_sil0il0bs8_il15il8bs1Tmsb8(\n+ uint64 instruction);\n+ uint64 extr_stypeil16il0bs5Fmsb4(\n+ uint64 instruction);\n+ uint64 extr_rt1il9il0bs1Fmsb0(\n+ uint64 instruction);\n+ uint64 extr_hsil16il0bs5Fmsb4(\n+ uint64 instruction);\n+ uint64 extr_xil10il0bs1_il14il0bs2Fmsb1(\n+ uint64 instruction);\n+ uint64 extr_selil11il0bs3Fmsb2(\n+ uint64 instruction);\n+ uint64 extr_lsbil0il0bs5Fmsb4(\n+ uint64 instruction);\n+ uint64 extr_xil14il0bs2Fmsb1(\n+ uint64 instruction);\n+ uint64 extr_gpil2il0bs1Fmsb0(\n+ uint64 instruction);\n+ uint64 extr_rt3il7il0bs3Fmsb2(\n+ uint64 instruction);\n+ uint64 extr_ftil21il0bs5Fmsb4(\n+ uint64 instruction);\n+ uint64 extr_uil11il0bs7Fmsb6(\n+ uint64 instruction);\n+ uint64 extr_csil16il0bs5Fmsb4(\n+ uint64 instruction);\n+ uint64 extr_xil16il0bs10Fmsb9(\n+ uint64 instruction);\n+ uint64 extr_rt4il5il0bs3_il9il3bs1Fmsb3(\n+ uint64 instruction);\n+ uint64 extr_msbdil6il0bs5Fmsb4(\n+ uint64 instruction);\n+ uint64 extr_uil0il2bs6Fmsb7(\n+ uint64 instruction);\n+ uint64 extr_xil17il0bs9Fmsb8(\n+ uint64 instruction);\n+ uint64 extr_sail13il0bs3Fmsb2(\n+ uint64 instruction);\n+ int64 extr_sil0il14bs1_il1il1bs13Tmsb14(\n+ uint64 instruction);\n+ uint64 extr_rs3il4il0bs3Fmsb2(\n+ uint64 instruction);\n+ uint64 extr_uil0il32bs32Fmsb63(\n+ uint64 instruction);\n+ uint64 extr_shiftil6il0bs5Fmsb4(\n+ uint64 instruction);\n+ uint64 extr_csil21il0bs5Fmsb4(\n+ uint64 instruction);\n+ uint64 extr_shiftxil6il0bs6Fmsb5(\n+ uint64 instruction);\n+ uint64 extr_rtil5il0bs5Fmsb4(\n+ uint64 instruction);\n+ uint64 extr_opil21il0bs5Fmsb4(\n+ uint64 instruction);\n+ uint64 extr_uil0il2bs7Fmsb8(\n+ uint64 instruction);\n+ uint64 extr_bitil11il0bs6Fmsb5(\n+ uint64 instruction);\n+ uint64 extr_xil10il0bs1_il11il0bs5Fmsb4(\n+ uint64 instruction);\n+ uint64 extr_maskil14il0bs7Fmsb6(\n+ uint64 instruction);\n+ uint64 extr_euil0il0bs4Fmsb3(\n+ uint64 instruction);\n+ uint64 extr_uil4il4bs4Fmsb7(\n+ uint64 instruction);\n+ int64 extr_sil3il3bs5_il15il8bs1Tmsb8(\n+ uint64 instruction);\n+ uint64 extr_ftil11il0bs5Fmsb4(\n+ uint64 instruction);\n+ int64 extr_sil0il16bs16_il16il0bs16Tmsb31(\n+ uint64 instruction);\n+ uint64 extr_uil13il0bs8Fmsb7(\n+ uint64 instruction);\n+ uint64 extr_xil15il0bs1Fmsb0(\n+ uint64 instruction);\n+ uint64 extr_xil11il0bs5Fmsb4(\n+ uint64 instruction);\n+ uint64 extr_uil2il2bs16Fmsb17(\n+ uint64 instruction);\n+ uint64 extr_rdil11il0bs5Fmsb4(\n+ uint64 instruction);\n+ uint64 extr_c0sil16il0bs5Fmsb4(\n+ uint64 instruction);\n+ uint64 extr_codeil0il0bs2Fmsb1(\n+ uint64 instruction);\n+ int64 extr_sil0il25bs1_il1il1bs24Tmsb25(\n+ uint64 instruction);\n+ uint64 extr_xil0il0bs3_il4il0bs1Fmsb2(\n+ uint64 instruction);\n+ uint64 extr_uil0il0bs2Fmsb1(\n+ uint64 instruction);\n+ uint64 extr_uil3il3bs1_il8il2bs1Fmsb3(\n+ uint64 instruction);\n+ uint64 extr_xil9il0bs3_il16il0bs5Fmsb4(\n+ uint64 instruction);\n+ uint64 extr_fdil11il0bs5Fmsb4(\n+ uint64 instruction);\n+ uint64 extr_xil6il0bs3Fmsb2(\n+ uint64 instruction);\n+ uint64 extr_uil0il2bs5Fmsb6(\n+ uint64 instruction);\n+ uint64 extr_rtz4il5il0bs3_il9il3bs1Fmsb3(\n+ uint64 instruction);\n+ uint64 extr_selil11il0bs5Fmsb4(\n+ uint64 instruction);\n+ uint64 extr_ctil21il0bs5Fmsb4(\n+ uint64 instruction);\n+ uint64 extr_xil11il0bs1Fmsb0(\n+ uint64 instruction);\n+ uint64 extr_uil2il2bs19Fmsb20(\n+ uint64 instruction);\n+ int64 extr_sil0il0bs3_il4il3bs1Tmsb3(\n+ uint64 instruction);\n+ uint64 extr_uil0il1bs4Fmsb4(\n+ uint64 instruction);\n+ uint64 extr_xil9il0bs2Fmsb1(\n+ uint64 instruction);\n+\n+ bool BNEC_16__cond(uint64 instruction);\n+ bool ADDIU_32__cond(uint64 instruction);\n+ bool P16_BR1_cond(uint64 instruction);\n+ bool ADDIU_RS5__cond(uint64 instruction);\n+ bool BEQC_16__cond(uint64 instruction);\n+ bool SLTU_cond(uint64 instruction);\n+ bool PREF_S9__cond(uint64 instruction);\n+ bool BALRSC_cond(uint64 instruction);\n+ bool MOVE_cond(uint64 instruction);\n+ bool PREFE_cond(uint64 instruction);\n+\n+ std::string SIGRIE(uint64 instruction);\n+ std::string SYSCALL_32_(uint64 instruction);\n+ std::string HYPCALL(uint64 instruction);\n+ std::string BREAK_32_(uint64 instruction);\n+ std::string SDBBP_32_(uint64 instruction);\n+ std::string ADDIU_32_(uint64 instruction);\n+ std::string TEQ(uint64 instruction);\n+ std::string TNE(uint64 instruction);\n+ std::string SEB(uint64 instruction);\n+ std::string SLLV(uint64 instruction);\n+ std::string MUL_32_(uint64 instruction);\n+ std::string MFC0(uint64 instruction);\n+ std::string MFHC0(uint64 instruction);\n+ std::string SEH(uint64 instruction);\n+ std::string SRLV(uint64 instruction);\n+ std::string MUH(uint64 instruction);\n+ std::string MTC0(uint64 instruction);\n+ std::string MTHC0(uint64 instruction);\n+ std::string SRAV(uint64 instruction);\n+ std::string MULU(uint64 instruction);\n+ std::string MFGC0(uint64 instruction);\n+ std::string MFHGC0(uint64 instruction);\n+ std::string ROTRV(uint64 instruction);\n+ std::string MUHU(uint64 instruction);\n+ std::string MTGC0(uint64 instruction);\n+ std::string MTHGC0(uint64 instruction);\n+ std::string ADD(uint64 instruction);\n+ std::string DIV(uint64 instruction);\n+ std::string DMFC0(uint64 instruction);\n+ std::string ADDU_32_(uint64 instruction);\n+ std::string MOD(uint64 instruction);\n+ std::string DMTC0(uint64 instruction);\n+ std::string SUB(uint64 instruction);\n+ std::string DIVU(uint64 instruction);\n+ std::string DMFGC0(uint64 instruction);\n+ std::string RDHWR(uint64 instruction);\n+ std::string SUBU_32_(uint64 instruction);\n+ std::string MODU(uint64 instruction);\n+ std::string DMTGC0(uint64 instruction);\n+ std::string MOVZ(uint64 instruction);\n+ std::string MOVN(uint64 instruction);\n+ std::string FORK(uint64 instruction);\n+ std::string MFTR(uint64 instruction);\n+ std::string MFHTR(uint64 instruction);\n+ std::string AND_32_(uint64 instruction);\n+ std::string YIELD(uint64 instruction);\n+ std::string MTTR(uint64 instruction);\n+ std::string MTHTR(uint64 instruction);\n+ std::string OR_32_(uint64 instruction);\n+ std::string DMT(uint64 instruction);\n+ std::string DVPE(uint64 instruction);\n+ std::string EMT(uint64 instruction);\n+ std::string EVPE(uint64 instruction);\n+ std::string NOR(uint64 instruction);\n+ std::string XOR_32_(uint64 instruction);\n+ std::string SLT(uint64 instruction);\n+ std::string DVP(uint64 instruction);\n+ std::string EVP(uint64 instruction);\n+ std::string SLTU(uint64 instruction);\n+ std::string SOV(uint64 instruction);\n+ std::string SPECIAL2(uint64 instruction);\n+ std::string COP2_1(uint64 instruction);\n+ std::string UDI(uint64 instruction);\n+ std::string CMP_EQ_PH(uint64 instruction);\n+ std::string ADDQ_PH(uint64 instruction);\n+ std::string ADDQ_S_PH(uint64 instruction);\n+ std::string SHILO(uint64 instruction);\n+ std::string MULEQ_S_W_PHL(uint64 instruction);\n+ std::string MUL_PH(uint64 instruction);\n+ std::string MUL_S_PH(uint64 instruction);\n+ std::string REPL_PH(uint64 instruction);\n+ std::string CMP_LT_PH(uint64 instruction);\n+ std::string ADDQH_PH(uint64 instruction);\n+ std::string ADDQH_R_PH(uint64 instruction);\n+ std::string MULEQ_S_W_PHR(uint64 instruction);\n+ std::string PRECR_QB_PH(uint64 instruction);\n+ std::string CMP_LE_PH(uint64 instruction);\n+ std::string ADDQH_W(uint64 instruction);\n+ std::string ADDQH_R_W(uint64 instruction);\n+ std::string MULEU_S_PH_QBL(uint64 instruction);\n+ std::string PRECRQ_QB_PH(uint64 instruction);\n+ std::string CMPGU_EQ_QB(uint64 instruction);\n+ std::string ADDU_QB(uint64 instruction);\n+ std::string ADDU_S_QB(uint64 instruction);\n+ std::string MULEU_S_PH_QBR(uint64 instruction);\n+ std::string PRECRQ_PH_W(uint64 instruction);\n+ std::string CMPGU_LT_QB(uint64 instruction);\n+ std::string ADDU_PH(uint64 instruction);\n+ std::string ADDU_S_PH(uint64 instruction);\n+ std::string MULQ_RS_PH(uint64 instruction);\n+ std::string PRECRQ_RS_PH_W(uint64 instruction);\n+ std::string CMPGU_LE_QB(uint64 instruction);\n+ std::string ADDUH_QB(uint64 instruction);\n+ std::string ADDUH_R_QB(uint64 instruction);\n+ std::string MULQ_S_PH(uint64 instruction);\n+ std::string PRECRQU_S_QB_PH(uint64 instruction);\n+ std::string CMPGDU_EQ_QB(uint64 instruction);\n+ std::string SHRAV_PH(uint64 instruction);\n+ std::string SHRAV_R_PH(uint64 instruction);\n+ std::string MULQ_RS_W(uint64 instruction);\n+ std::string PACKRL_PH(uint64 instruction);\n+ std::string CMPGDU_LT_QB(uint64 instruction);\n+ std::string SHRAV_QB(uint64 instruction);\n+ std::string SHRAV_R_QB(uint64 instruction);\n+ std::string MULQ_S_W(uint64 instruction);\n+ std::string PICK_QB(uint64 instruction);\n+ std::string CMPGDU_LE_QB(uint64 instruction);\n+ std::string SUBQ_PH(uint64 instruction);\n+ std::string SUBQ_S_PH(uint64 instruction);\n+ std::string APPEND(uint64 instruction);\n+ std::string PICK_PH(uint64 instruction);\n+ std::string CMPU_EQ_QB(uint64 instruction);\n+ std::string SUBQH_PH(uint64 instruction);\n+ std::string SUBQH_R_PH(uint64 instruction);\n+ std::string PREPEND(uint64 instruction);\n+ std::string CMPU_LT_QB(uint64 instruction);\n+ std::string SUBQH_W(uint64 instruction);\n+ std::string SUBQH_R_W(uint64 instruction);\n+ std::string MODSUB(uint64 instruction);\n+ std::string CMPU_LE_QB(uint64 instruction);\n+ std::string SUBU_QB(uint64 instruction);\n+ std::string SUBU_S_QB(uint64 instruction);\n+ std::string SHRAV_R_W(uint64 instruction);\n+ std::string SHRA_R_W(uint64 instruction);\n+ std::string ADDQ_S_W(uint64 instruction);\n+ std::string SUBU_PH(uint64 instruction);\n+ std::string SUBU_S_PH(uint64 instruction);\n+ std::string SHRLV_PH(uint64 instruction);\n+ std::string SHRA_PH(uint64 instruction);\n+ std::string SHRA_R_PH(uint64 instruction);\n+ std::string SUBQ_S_W(uint64 instruction);\n+ std::string SUBUH_QB(uint64 instruction);\n+ std::string SUBUH_R_QB(uint64 instruction);\n+ std::string SHRLV_QB(uint64 instruction);\n+ std::string ADDSC(uint64 instruction);\n+ std::string SHLLV_PH(uint64 instruction);\n+ std::string SHLLV_S_PH(uint64 instruction);\n+ std::string SHLLV_QB(uint64 instruction);\n+ std::string SHLL_PH(uint64 instruction);\n+ std::string SHLL_S_PH(uint64 instruction);\n+ std::string ADDWC(uint64 instruction);\n+ std::string PRECR_SRA_PH_W(uint64 instruction);\n+ std::string PRECR_SRA_R_PH_W(uint64 instruction);\n+ std::string SHLLV_S_W(uint64 instruction);\n+ std::string SHLL_S_W(uint64 instruction);\n+ std::string LBX(uint64 instruction);\n+ std::string SBX(uint64 instruction);\n+ std::string LBUX(uint64 instruction);\n+ std::string LHX(uint64 instruction);\n+ std::string SHX(uint64 instruction);\n+ std::string LHUX(uint64 instruction);\n+ std::string LWUX(uint64 instruction);\n+ std::string LWX(uint64 instruction);\n+ std::string SWX(uint64 instruction);\n+ std::string LWC1X(uint64 instruction);\n+ std::string SWC1X(uint64 instruction);\n+ std::string LDX(uint64 instruction);\n+ std::string SDX(uint64 instruction);\n+ std::string LDC1X(uint64 instruction);\n+ std::string SDC1X(uint64 instruction);\n+ std::string LHXS(uint64 instruction);\n+ std::string SHXS(uint64 instruction);\n+ std::string LHUXS(uint64 instruction);\n+ std::string LWUXS(uint64 instruction);\n+ std::string LWXS_32_(uint64 instruction);\n+ std::string SWXS(uint64 instruction);\n+ std::string LWC1XS(uint64 instruction);\n+ std::string SWC1XS(uint64 instruction);\n+ std::string LDXS(uint64 instruction);\n+ std::string SDXS(uint64 instruction);\n+ std::string LDC1XS(uint64 instruction);\n+ std::string SDC1XS(uint64 instruction);\n+ std::string LSA(uint64 instruction);\n+ std::string EXTW(uint64 instruction);\n+ std::string MFHI_DSP_(uint64 instruction);\n+ std::string MFLO_DSP_(uint64 instruction);\n+ std::string MTHI_DSP_(uint64 instruction);\n+ std::string MTLO_DSP_(uint64 instruction);\n+ std::string MTHLIP(uint64 instruction);\n+ std::string SHILOV(uint64 instruction);\n+ std::string RDDSP(uint64 instruction);\n+ std::string WRDSP(uint64 instruction);\n+ std::string EXTP(uint64 instruction);\n+ std::string EXTPDP(uint64 instruction);\n+ std::string SHLL_QB(uint64 instruction);\n+ std::string SHRL_QB(uint64 instruction);\n+ std::string MAQ_S_W_PHR(uint64 instruction);\n+ std::string MAQ_SA_W_PHR(uint64 instruction);\n+ std::string MAQ_S_W_PHL(uint64 instruction);\n+ std::string MAQ_SA_W_PHL(uint64 instruction);\n+ std::string EXTR_W(uint64 instruction);\n+ std::string EXTR_R_W(uint64 instruction);\n+ std::string EXTR_RS_W(uint64 instruction);\n+ std::string EXTR_S_H(uint64 instruction);\n+ std::string DPA_W_PH(uint64 instruction);\n+ std::string DPAQ_S_W_PH(uint64 instruction);\n+ std::string DPS_W_PH(uint64 instruction);\n+ std::string DPSQ_S_W_PH(uint64 instruction);\n+ std::string MADD_DSP_(uint64 instruction);\n+ std::string MULT_DSP_(uint64 instruction);\n+ std::string EXTRV_W(uint64 instruction);\n+ std::string DPAX_W_PH(uint64 instruction);\n+ std::string DPAQ_SA_L_W(uint64 instruction);\n+ std::string DPSX_W_PH(uint64 instruction);\n+ std::string DPSQ_SA_L_W(uint64 instruction);\n+ std::string MADDU_DSP_(uint64 instruction);\n+ std::string MULTU_DSP_(uint64 instruction);\n+ std::string EXTRV_R_W(uint64 instruction);\n+ std::string DPAU_H_QBL(uint64 instruction);\n+ std::string DPAQX_S_W_PH(uint64 instruction);\n+ std::string DPSU_H_QBL(uint64 instruction);\n+ std::string DPSQX_S_W_PH(uint64 instruction);\n+ std::string EXTPV(uint64 instruction);\n+ std::string MSUB_DSP_(uint64 instruction);\n+ std::string MULSA_W_PH(uint64 instruction);\n+ std::string EXTRV_RS_W(uint64 instruction);\n+ std::string DPAU_H_QBR(uint64 instruction);\n+ std::string DPAQX_SA_W_PH(uint64 instruction);\n+ std::string DPSU_H_QBR(uint64 instruction);\n+ std::string DPSQX_SA_W_PH(uint64 instruction);\n+ std::string EXTPDPV(uint64 instruction);\n+ std::string MSUBU_DSP_(uint64 instruction);\n+ std::string MULSAQ_S_W_PH(uint64 instruction);\n+ std::string EXTRV_S_H(uint64 instruction);\n+ std::string ABSQ_S_QB(uint64 instruction);\n+ std::string REPLV_PH(uint64 instruction);\n+ std::string ABSQ_S_PH(uint64 instruction);\n+ std::string REPLV_QB(uint64 instruction);\n+ std::string ABSQ_S_W(uint64 instruction);\n+ std::string INSV(uint64 instruction);\n+ std::string CLO(uint64 instruction);\n+ std::string MFC2(uint64 instruction);\n+ std::string PRECEQ_W_PHL(uint64 instruction);\n+ std::string CLZ(uint64 instruction);\n+ std::string MTC2(uint64 instruction);\n+ std::string PRECEQ_W_PHR(uint64 instruction);\n+ std::string DMFC2(uint64 instruction);\n+ std::string PRECEQU_PH_QBL(uint64 instruction);\n+ std::string PRECEQU_PH_QBLA(uint64 instruction);\n+ std::string DMTC2(uint64 instruction);\n+ std::string MFHC2(uint64 instruction);\n+ std::string PRECEQU_PH_QBR(uint64 instruction);\n+ std::string PRECEQU_PH_QBRA(uint64 instruction);\n+ std::string MTHC2(uint64 instruction);\n+ std::string PRECEU_PH_QBL(uint64 instruction);\n+ std::string PRECEU_PH_QBLA(uint64 instruction);\n+ std::string CFC2(uint64 instruction);\n+ std::string PRECEU_PH_QBR(uint64 instruction);\n+ std::string PRECEU_PH_QBRA(uint64 instruction);\n+ std::string CTC2(uint64 instruction);\n+ std::string RADDU_W_QB(uint64 instruction);\n+ std::string TLBGP(uint64 instruction);\n+ std::string TLBP(uint64 instruction);\n+ std::string TLBGINV(uint64 instruction);\n+ std::string TLBINV(uint64 instruction);\n+ std::string TLBGR(uint64 instruction);\n+ std::string TLBR(uint64 instruction);\n+ std::string TLBGINVF(uint64 instruction);\n+ std::string TLBINVF(uint64 instruction);\n+ std::string TLBGWI(uint64 instruction);\n+ std::string TLBWI(uint64 instruction);\n+ std::string TLBGWR(uint64 instruction);\n+ std::string TLBWR(uint64 instruction);\n+ std::string DI(uint64 instruction);\n+ std::string EI(uint64 instruction);\n+ std::string WAIT(uint64 instruction);\n+ std::string IRET(uint64 instruction);\n+ std::string RDPGPR(uint64 instruction);\n+ std::string DERET(uint64 instruction);\n+ std::string WRPGPR(uint64 instruction);\n+ std::string ERET(uint64 instruction);\n+ std::string ERETNC(uint64 instruction);\n+ std::string SHRA_QB(uint64 instruction);\n+ std::string SHRA_R_QB(uint64 instruction);\n+ std::string SHRL_PH(uint64 instruction);\n+ std::string REPL_QB(uint64 instruction);\n+ std::string ADDIU_GP_W_(uint64 instruction);\n+ std::string LD_GP_(uint64 instruction);\n+ std::string SD_GP_(uint64 instruction);\n+ std::string LW_GP_(uint64 instruction);\n+ std::string SW_GP_(uint64 instruction);\n+ std::string LI_48_(uint64 instruction);\n+ std::string ADDIU_48_(uint64 instruction);\n+ std::string ADDIU_GP48_(uint64 instruction);\n+ std::string ADDIUPC_48_(uint64 instruction);\n+ std::string LWPC_48_(uint64 instruction);\n+ std::string SWPC_48_(uint64 instruction);\n+ std::string DADDIU_48_(uint64 instruction);\n+ std::string DLUI_48_(uint64 instruction);\n+ std::string LDPC_48_(uint64 instruction);\n+ std::string SDPC_48_(uint64 instruction);\n+ std::string ORI(uint64 instruction);\n+ std::string XORI(uint64 instruction);\n+ std::string ANDI_32_(uint64 instruction);\n+ std::string SAVE_32_(uint64 instruction);\n+ std::string RESTORE_32_(uint64 instruction);\n+ std::string RESTORE_JRC_32_(uint64 instruction);\n+ std::string SAVEF(uint64 instruction);\n+ std::string RESTOREF(uint64 instruction);\n+ std::string SLTI(uint64 instruction);\n+ std::string SLTIU(uint64 instruction);\n+ std::string SEQI(uint64 instruction);\n+ std::string ADDIU_NEG_(uint64 instruction);\n+ std::string DADDIU_U12_(uint64 instruction);\n+ std::string DADDIU_NEG_(uint64 instruction);\n+ std::string DROTX(uint64 instruction);\n+ std::string NOP_32_(uint64 instruction);\n+ std::string EHB(uint64 instruction);\n+ std::string PAUSE(uint64 instruction);\n+ std::string SYNC(uint64 instruction);\n+ std::string SLL_32_(uint64 instruction);\n+ std::string SRL_32_(uint64 instruction);\n+ std::string SRA(uint64 instruction);\n+ std::string ROTR(uint64 instruction);\n+ std::string DSLL(uint64 instruction);\n+ std::string DSLL32(uint64 instruction);\n+ std::string DSRL(uint64 instruction);\n+ std::string DSRL32(uint64 instruction);\n+ std::string DSRA(uint64 instruction);\n+ std::string DSRA32(uint64 instruction);\n+ std::string DROTR(uint64 instruction);\n+ std::string DROTR32(uint64 instruction);\n+ std::string ROTX(uint64 instruction);\n+ std::string INS(uint64 instruction);\n+ std::string DINSU(uint64 instruction);\n+ std::string DINSM(uint64 instruction);\n+ std::string DINS(uint64 instruction);\n+ std::string EXT(uint64 instruction);\n+ std::string DEXTU(uint64 instruction);\n+ std::string DEXTM(uint64 instruction);\n+ std::string DEXT(uint64 instruction);\n+ std::string RINT_S(uint64 instruction);\n+ std::string RINT_D(uint64 instruction);\n+ std::string ADD_S(uint64 instruction);\n+ std::string SELEQZ_S(uint64 instruction);\n+ std::string SELEQZ_D(uint64 instruction);\n+ std::string CLASS_S(uint64 instruction);\n+ std::string CLASS_D(uint64 instruction);\n+ std::string SUB_S(uint64 instruction);\n+ std::string SELNEZ_S(uint64 instruction);\n+ std::string SELNEZ_D(uint64 instruction);\n+ std::string MUL_S(uint64 instruction);\n+ std::string SEL_S(uint64 instruction);\n+ std::string SEL_D(uint64 instruction);\n+ std::string DIV_S(uint64 instruction);\n+ std::string ADD_D(uint64 instruction);\n+ std::string SUB_D(uint64 instruction);\n+ std::string MUL_D(uint64 instruction);\n+ std::string MADDF_S(uint64 instruction);\n+ std::string MADDF_D(uint64 instruction);\n+ std::string DIV_D(uint64 instruction);\n+ std::string MSUBF_S(uint64 instruction);\n+ std::string MSUBF_D(uint64 instruction);\n+ std::string MIN_S(uint64 instruction);\n+ std::string MIN_D(uint64 instruction);\n+ std::string MAX_S(uint64 instruction);\n+ std::string MAX_D(uint64 instruction);\n+ std::string MINA_S(uint64 instruction);\n+ std::string MINA_D(uint64 instruction);\n+ std::string MAXA_S(uint64 instruction);\n+ std::string MAXA_D(uint64 instruction);\n+ std::string CVT_L_S(uint64 instruction);\n+ std::string CVT_L_D(uint64 instruction);\n+ std::string RSQRT_S(uint64 instruction);\n+ std::string RSQRT_D(uint64 instruction);\n+ std::string FLOOR_L_S(uint64 instruction);\n+ std::string FLOOR_L_D(uint64 instruction);\n+ std::string CVT_W_S(uint64 instruction);\n+ std::string CVT_W_D(uint64 instruction);\n+ std::string SQRT_S(uint64 instruction);\n+ std::string SQRT_D(uint64 instruction);\n+ std::string FLOOR_W_S(uint64 instruction);\n+ std::string FLOOR_W_D(uint64 instruction);\n+ std::string CFC1(uint64 instruction);\n+ std::string RECIP_S(uint64 instruction);\n+ std::string RECIP_D(uint64 instruction);\n+ std::string CEIL_L_S(uint64 instruction);\n+ std::string CEIL_L_D(uint64 instruction);\n+ std::string CTC1(uint64 instruction);\n+ std::string CEIL_W_S(uint64 instruction);\n+ std::string CEIL_W_D(uint64 instruction);\n+ std::string MFC1(uint64 instruction);\n+ std::string CVT_S_PL(uint64 instruction);\n+ std::string TRUNC_L_S(uint64 instruction);\n+ std::string TRUNC_L_D(uint64 instruction);\n+ std::string DMFC1(uint64 instruction);\n+ std::string MTC1(uint64 instruction);\n+ std::string CVT_S_PU(uint64 instruction);\n+ std::string TRUNC_W_S(uint64 instruction);\n+ std::string TRUNC_W_D(uint64 instruction);\n+ std::string DMTC1(uint64 instruction);\n+ std::string MFHC1(uint64 instruction);\n+ std::string ROUND_L_S(uint64 instruction);\n+ std::string ROUND_L_D(uint64 instruction);\n+ std::string MTHC1(uint64 instruction);\n+ std::string ROUND_W_S(uint64 instruction);\n+ std::string ROUND_W_D(uint64 instruction);\n+ std::string MOV_S(uint64 instruction);\n+ std::string MOV_D(uint64 instruction);\n+ std::string ABS_S(uint64 instruction);\n+ std::string ABS_D(uint64 instruction);\n+ std::string NEG_S(uint64 instruction);\n+ std::string NEG_D(uint64 instruction);\n+ std::string CVT_D_S(uint64 instruction);\n+ std::string CVT_D_W(uint64 instruction);\n+ std::string CVT_D_L(uint64 instruction);\n+ std::string CVT_S_D(uint64 instruction);\n+ std::string CVT_S_W(uint64 instruction);\n+ std::string CVT_S_L(uint64 instruction);\n+ std::string CMP_AF_S(uint64 instruction);\n+ std::string CMP_UN_S(uint64 instruction);\n+ std::string CMP_EQ_S(uint64 instruction);\n+ std::string CMP_UEQ_S(uint64 instruction);\n+ std::string CMP_LT_S(uint64 instruction);\n+ std::string CMP_ULT_S(uint64 instruction);\n+ std::string CMP_LE_S(uint64 instruction);\n+ std::string CMP_ULE_S(uint64 instruction);\n+ std::string CMP_SAF_S(uint64 instruction);\n+ std::string CMP_SUN_S(uint64 instruction);\n+ std::string CMP_SEQ_S(uint64 instruction);\n+ std::string CMP_SUEQ_S(uint64 instruction);\n+ std::string CMP_SLT_S(uint64 instruction);\n+ std::string CMP_SULT_S(uint64 instruction);\n+ std::string CMP_SLE_S(uint64 instruction);\n+ std::string CMP_SULE_S(uint64 instruction);\n+ std::string CMP_OR_S(uint64 instruction);\n+ std::string CMP_UNE_S(uint64 instruction);\n+ std::string CMP_NE_S(uint64 instruction);\n+ std::string CMP_SOR_S(uint64 instruction);\n+ std::string CMP_SUNE_S(uint64 instruction);\n+ std::string CMP_SNE_S(uint64 instruction);\n+ std::string CMP_AF_D(uint64 instruction);\n+ std::string CMP_UN_D(uint64 instruction);\n+ std::string CMP_EQ_D(uint64 instruction);\n+ std::string CMP_UEQ_D(uint64 instruction);\n+ std::string CMP_LT_D(uint64 instruction);\n+ std::string CMP_ULT_D(uint64 instruction);\n+ std::string CMP_LE_D(uint64 instruction);\n+ std::string CMP_ULE_D(uint64 instruction);\n+ std::string CMP_SAF_D(uint64 instruction);\n+ std::string CMP_SUN_D(uint64 instruction);\n+ std::string CMP_SEQ_D(uint64 instruction);\n+ std::string CMP_SUEQ_D(uint64 instruction);\n+ std::string CMP_SLT_D(uint64 instruction);\n+ std::string CMP_SULT_D(uint64 instruction);\n+ std::string CMP_SLE_D(uint64 instruction);\n+ std::string CMP_SULE_D(uint64 instruction);\n+ std::string CMP_OR_D(uint64 instruction);\n+ std::string CMP_UNE_D(uint64 instruction);\n+ std::string CMP_NE_D(uint64 instruction);\n+ std::string CMP_SOR_D(uint64 instruction);\n+ std::string CMP_SUNE_D(uint64 instruction);\n+ std::string CMP_SNE_D(uint64 instruction);\n+ std::string DLSA(uint64 instruction);\n+ std::string DSLLV(uint64 instruction);\n+ std::string DMUL(uint64 instruction);\n+ std::string DSRLV(uint64 instruction);\n+ std::string DMUH(uint64 instruction);\n+ std::string DSRAV(uint64 instruction);\n+ std::string DMULU(uint64 instruction);\n+ std::string DROTRV(uint64 instruction);\n+ std::string DMUHU(uint64 instruction);\n+ std::string DADD(uint64 instruction);\n+ std::string DDIV(uint64 instruction);\n+ std::string DADDU(uint64 instruction);\n+ std::string DMOD(uint64 instruction);\n+ std::string DSUB(uint64 instruction);\n+ std::string DDIVU(uint64 instruction);\n+ std::string DSUBU(uint64 instruction);\n+ std::string DMODU(uint64 instruction);\n+ std::string EXTD(uint64 instruction);\n+ std::string EXTD32(uint64 instruction);\n+ std::string DCLO(uint64 instruction);\n+ std::string DCLZ(uint64 instruction);\n+ std::string LUI(uint64 instruction);\n+ std::string ALUIPC(uint64 instruction);\n+ std::string ADDIUPC_32_(uint64 instruction);\n+ std::string LB_GP_(uint64 instruction);\n+ std::string SB_GP_(uint64 instruction);\n+ std::string LBU_GP_(uint64 instruction);\n+ std::string ADDIU_GP_B_(uint64 instruction);\n+ std::string LH_GP_(uint64 instruction);\n+ std::string LHU_GP_(uint64 instruction);\n+ std::string SH_GP_(uint64 instruction);\n+ std::string LWC1_GP_(uint64 instruction);\n+ std::string SWC1_GP_(uint64 instruction);\n+ std::string LDC1_GP_(uint64 instruction);\n+ std::string SDC1_GP_(uint64 instruction);\n+ std::string LWU_GP_(uint64 instruction);\n+ std::string LB_U12_(uint64 instruction);\n+ std::string SB_U12_(uint64 instruction);\n+ std::string LBU_U12_(uint64 instruction);\n+ std::string PREF_U12_(uint64 instruction);\n+ std::string LH_U12_(uint64 instruction);\n+ std::string SH_U12_(uint64 instruction);\n+ std::string LHU_U12_(uint64 instruction);\n+ std::string LWU_U12_(uint64 instruction);\n+ std::string LW_U12_(uint64 instruction);\n+ std::string SW_U12_(uint64 instruction);\n+ std::string LWC1_U12_(uint64 instruction);\n+ std::string SWC1_U12_(uint64 instruction);\n+ std::string LD_U12_(uint64 instruction);\n+ std::string SD_U12_(uint64 instruction);\n+ std::string LDC1_U12_(uint64 instruction);\n+ std::string SDC1_U12_(uint64 instruction);\n+ std::string LB_S9_(uint64 instruction);\n+ std::string SB_S9_(uint64 instruction);\n+ std::string LBU_S9_(uint64 instruction);\n+ std::string SYNCI(uint64 instruction);\n+ std::string PREF_S9_(uint64 instruction);\n+ std::string LH_S9_(uint64 instruction);\n+ std::string SH_S9_(uint64 instruction);\n+ std::string LHU_S9_(uint64 instruction);\n+ std::string LWU_S9_(uint64 instruction);\n+ std::string LW_S9_(uint64 instruction);\n+ std::string SW_S9_(uint64 instruction);\n+ std::string LWC1_S9_(uint64 instruction);\n+ std::string SWC1_S9_(uint64 instruction);\n+ std::string LD_S9_(uint64 instruction);\n+ std::string SD_S9_(uint64 instruction);\n+ std::string LDC1_S9_(uint64 instruction);\n+ std::string SDC1_S9_(uint64 instruction);\n+ std::string ASET(uint64 instruction);\n+ std::string ACLR(uint64 instruction);\n+ std::string UALH(uint64 instruction);\n+ std::string UASH(uint64 instruction);\n+ std::string CACHE(uint64 instruction);\n+ std::string LWC2(uint64 instruction);\n+ std::string SWC2(uint64 instruction);\n+ std::string LL(uint64 instruction);\n+ std::string LLWP(uint64 instruction);\n+ std::string SC(uint64 instruction);\n+ std::string SCWP(uint64 instruction);\n+ std::string LDC2(uint64 instruction);\n+ std::string SDC2(uint64 instruction);\n+ std::string LLD(uint64 instruction);\n+ std::string LLDP(uint64 instruction);\n+ std::string SCD(uint64 instruction);\n+ std::string SCDP(uint64 instruction);\n+ std::string LBE(uint64 instruction);\n+ std::string SBE(uint64 instruction);\n+ std::string LBUE(uint64 instruction);\n+ std::string SYNCIE(uint64 instruction);\n+ std::string PREFE(uint64 instruction);\n+ std::string LHE(uint64 instruction);\n+ std::string SHE(uint64 instruction);\n+ std::string LHUE(uint64 instruction);\n+ std::string CACHEE(uint64 instruction);\n+ std::string LWE(uint64 instruction);\n+ std::string SWE(uint64 instruction);\n+ std::string LLE(uint64 instruction);\n+ std::string LLWPE(uint64 instruction);\n+ std::string SCE(uint64 instruction);\n+ std::string SCWPE(uint64 instruction);\n+ std::string LWM(uint64 instruction);\n+ std::string SWM(uint64 instruction);\n+ std::string UALWM(uint64 instruction);\n+ std::string UASWM(uint64 instruction);\n+ std::string LDM(uint64 instruction);\n+ std::string SDM(uint64 instruction);\n+ std::string UALDM(uint64 instruction);\n+ std::string UASDM(uint64 instruction);\n+ std::string MOVE_BALC(uint64 instruction);\n+ std::string BC_32_(uint64 instruction);\n+ std::string BALC_32_(uint64 instruction);\n+ std::string JALRC_32_(uint64 instruction);\n+ std::string JALRC_HB(uint64 instruction);\n+ std::string BRSC(uint64 instruction);\n+ std::string BALRSC(uint64 instruction);\n+ std::string BEQC_32_(uint64 instruction);\n+ std::string BC1EQZC(uint64 instruction);\n+ std::string BC1NEZC(uint64 instruction);\n+ std::string BC2EQZC(uint64 instruction);\n+ std::string BC2NEZC(uint64 instruction);\n+ std::string BPOSGE32C(uint64 instruction);\n+ std::string BGEC(uint64 instruction);\n+ std::string BGEUC(uint64 instruction);\n+ std::string BNEC_32_(uint64 instruction);\n+ std::string BLTC(uint64 instruction);\n+ std::string BLTUC(uint64 instruction);\n+ std::string BEQIC(uint64 instruction);\n+ std::string BBEQZC(uint64 instruction);\n+ std::string BGEIC(uint64 instruction);\n+ std::string BGEIUC(uint64 instruction);\n+ std::string BNEIC(uint64 instruction);\n+ std::string BBNEZC(uint64 instruction);\n+ std::string BLTIC(uint64 instruction);\n+ std::string BLTIUC(uint64 instruction);\n+ std::string SYSCALL_16_(uint64 instruction);\n+ std::string HYPCALL_16_(uint64 instruction);\n+ std::string BREAK_16_(uint64 instruction);\n+ std::string SDBBP_16_(uint64 instruction);\n+ std::string MOVE(uint64 instruction);\n+ std::string SLL_16_(uint64 instruction);\n+ std::string SRL_16_(uint64 instruction);\n+ std::string NOT_16_(uint64 instruction);\n+ std::string XOR_16_(uint64 instruction);\n+ std::string AND_16_(uint64 instruction);\n+ std::string OR_16_(uint64 instruction);\n+ std::string LWXS_16_(uint64 instruction);\n+ std::string ADDIU_R1_SP_(uint64 instruction);\n+ std::string ADDIU_R2_(uint64 instruction);\n+ std::string NOP_16_(uint64 instruction);\n+ std::string ADDIU_RS5_(uint64 instruction);\n+ std::string ADDU_16_(uint64 instruction);\n+ std::string SUBU_16_(uint64 instruction);\n+ std::string LI_16_(uint64 instruction);\n+ std::string ANDI_16_(uint64 instruction);\n+ std::string LW_16_(uint64 instruction);\n+ std::string LW_SP_(uint64 instruction);\n+ std::string LW_GP16_(uint64 instruction);\n+ std::string LW_4X4_(uint64 instruction);\n+ std::string SW_16_(uint64 instruction);\n+ std::string SW_SP_(uint64 instruction);\n+ std::string SW_GP16_(uint64 instruction);\n+ std::string SW_4X4_(uint64 instruction);\n+ std::string BC_16_(uint64 instruction);\n+ std::string BALC_16_(uint64 instruction);\n+ std::string BEQZC_16_(uint64 instruction);\n+ std::string BNEZC_16_(uint64 instruction);\n+ std::string JRC(uint64 instruction);\n+ std::string JALRC_16_(uint64 instruction);\n+ std::string BEQC_16_(uint64 instruction);\n+ std::string BNEC_16_(uint64 instruction);\n+ std::string SAVE_16_(uint64 instruction);\n+ std::string RESTORE_JRC_16_(uint64 instruction);\n+ std::string ADDU_4X4_(uint64 instruction);\n+ std::string MUL_4X4_(uint64 instruction);\n+ std::string LB_16_(uint64 instruction);\n+ std::string SB_16_(uint64 instruction);\n+ std::string LBU_16_(uint64 instruction);\n+ std::string LH_16_(uint64 instruction);\n+ std::string SH_16_(uint64 instruction);\n+ std::string LHU_16_(uint64 instruction);\n+ std::string MOVEP(uint64 instruction);\n+ std::string MOVEP_REV_(uint64 instruction);\n+\n+ static Pool P_SYSCALL[2];\n+ static Pool P_RI[4];\n+ static Pool P_ADDIU[2];\n+ static Pool P_TRAP[2];\n+ static Pool P_CMOVE[2];\n+ static Pool P_D_MT_VPE[2];\n+ static Pool P_E_MT_VPE[2];\n+ static Pool _P_MT_VPE[2];\n+ static Pool P_MT_VPE[8];\n+ static Pool P_DVP[2];\n+ static Pool P_SLTU[2];\n+ static Pool _POOL32A0[128];\n+ static Pool ADDQ__S__PH[2];\n+ static Pool MUL__S__PH[2];\n+ static Pool ADDQH__R__PH[2];\n+ static Pool ADDQH__R__W[2];\n+ static Pool ADDU__S__QB[2];\n+ static Pool ADDU__S__PH[2];\n+ static Pool ADDUH__R__QB[2];\n+ static Pool SHRAV__R__PH[2];\n+ static Pool SHRAV__R__QB[2];\n+ static Pool SUBQ__S__PH[2];\n+ static Pool SUBQH__R__PH[2];\n+ static Pool SUBQH__R__W[2];\n+ static Pool SUBU__S__QB[2];\n+ static Pool SUBU__S__PH[2];\n+ static Pool SHRA__R__PH[2];\n+ static Pool SUBUH__R__QB[2];\n+ static Pool SHLLV__S__PH[2];\n+ static Pool SHLL__S__PH[4];\n+ static Pool PRECR_SRA__R__PH_W[2];\n+ static Pool _POOL32A5[128];\n+ static Pool PP_LSX[16];\n+ static Pool PP_LSXS[16];\n+ static Pool P_LSX[2];\n+ static Pool POOL32Axf_1_0[4];\n+ static Pool POOL32Axf_1_1[4];\n+ static Pool POOL32Axf_1_3[4];\n+ static Pool POOL32Axf_1_4[2];\n+ static Pool MAQ_S_A__W_PHR[2];\n+ static Pool MAQ_S_A__W_PHL[2];\n+ static Pool POOL32Axf_1_5[2];\n+ static Pool POOL32Axf_1_7[4];\n+ static Pool POOL32Axf_1[8];\n+ static Pool POOL32Axf_2_DSP__0_7[8];\n+ static Pool POOL32Axf_2_DSP__8_15[8];\n+ static Pool POOL32Axf_2_DSP__16_23[8];\n+ static Pool POOL32Axf_2_DSP__24_31[8];\n+ static Pool POOL32Axf_2[4];\n+ static Pool POOL32Axf_4[128];\n+ static Pool POOL32Axf_5_group0[32];\n+ static Pool POOL32Axf_5_group1[32];\n+ static Pool ERETx[2];\n+ static Pool POOL32Axf_5_group3[32];\n+ static Pool POOL32Axf_5[4];\n+ static Pool SHRA__R__QB[2];\n+ static Pool POOL32Axf_7[8];\n+ static Pool POOL32Axf[8];\n+ static Pool _POOL32A7[8];\n+ static Pool P32A[8];\n+ static Pool P_GP_D[2];\n+ static Pool P_GP_W[4];\n+ static Pool POOL48I[32];\n+ static Pool PP_SR[4];\n+ static Pool P_SR_F[8];\n+ static Pool P_SR[2];\n+ static Pool P_SLL[5];\n+ static Pool P_SHIFT[16];\n+ static Pool P_ROTX[4];\n+ static Pool P_INS[4];\n+ static Pool P_EXT[4];\n+ static Pool P_U12[16];\n+ static Pool RINT_fmt[2];\n+ static Pool ADD_fmt0[2];\n+ static Pool SELEQZ_fmt[2];\n+ static Pool CLASS_fmt[2];\n+ static Pool SUB_fmt0[2];\n+ static Pool SELNEZ_fmt[2];\n+ static Pool MUL_fmt0[2];\n+ static Pool SEL_fmt[2];\n+ static Pool DIV_fmt0[2];\n+ static Pool ADD_fmt1[2];\n+ static Pool SUB_fmt1[2];\n+ static Pool MUL_fmt1[2];\n+ static Pool MADDF_fmt[2];\n+ static Pool DIV_fmt1[2];\n+ static Pool MSUBF_fmt[2];\n+ static Pool POOL32F_0[64];\n+ static Pool MIN_fmt[2];\n+ static Pool MAX_fmt[2];\n+ static Pool MINA_fmt[2];\n+ static Pool MAXA_fmt[2];\n+ static Pool CVT_L_fmt[2];\n+ static Pool RSQRT_fmt[2];\n+ static Pool FLOOR_L_fmt[2];\n+ static Pool CVT_W_fmt[2];\n+ static Pool SQRT_fmt[2];\n+ static Pool FLOOR_W_fmt[2];\n+ static Pool RECIP_fmt[2];\n+ static Pool CEIL_L_fmt[2];\n+ static Pool CEIL_W_fmt[2];\n+ static Pool TRUNC_L_fmt[2];\n+ static Pool TRUNC_W_fmt[2];\n+ static Pool ROUND_L_fmt[2];\n+ static Pool ROUND_W_fmt[2];\n+ static Pool POOL32Fxf_0[64];\n+ static Pool MOV_fmt[4];\n+ static Pool ABS_fmt[4];\n+ static Pool NEG_fmt[4];\n+ static Pool CVT_D_fmt[4];\n+ static Pool CVT_S_fmt[4];\n+ static Pool POOL32Fxf_1[32];\n+ static Pool POOL32Fxf[4];\n+ static Pool POOL32F_3[8];\n+ static Pool CMP_condn_S[32];\n+ static Pool CMP_condn_D[32];\n+ static Pool POOL32F_5[8];\n+ static Pool POOL32F[8];\n+ static Pool POOL32S_0[64];\n+ static Pool POOL32Sxf_4[128];\n+ static Pool POOL32Sxf[8];\n+ static Pool POOL32S_4[8];\n+ static Pool POOL32S[8];\n+ static Pool P_LUI[2];\n+ static Pool P_GP_LH[2];\n+ static Pool P_GP_SH[2];\n+ static Pool P_GP_CP1[4];\n+ static Pool P_GP_M64[4];\n+ static Pool P_GP_BH[8];\n+ static Pool P_LS_U12[16];\n+ static Pool P_PREF_S9_[2];\n+ static Pool P_LS_S0[16];\n+ static Pool ASET_ACLR[2];\n+ static Pool P_LL[4];\n+ static Pool P_SC[4];\n+ static Pool P_LLD[8];\n+ static Pool P_SCD[8];\n+ static Pool P_LS_S1[16];\n+ static Pool P_PREFE[2];\n+ static Pool P_LLE[4];\n+ static Pool P_SCE[4];\n+ static Pool P_LS_E0[16];\n+ static Pool P_LS_WM[2];\n+ static Pool P_LS_UAWM[2];\n+ static Pool P_LS_DM[2];\n+ static Pool P_LS_UADM[2];\n+ static Pool P_LS_S9[8];\n+ static Pool P_BAL[2];\n+ static Pool P_BALRSC[2];\n+ static Pool P_J[16];\n+ static Pool P_BR3A[32];\n+ static Pool P_BR1[4];\n+ static Pool P_BR2[4];\n+ static Pool P_BRI[8];\n+ static Pool P32[32];\n+ static Pool P16_SYSCALL[2];\n+ static Pool P16_RI[4];\n+ static Pool P16_MV[2];\n+ static Pool P16_SHIFT[2];\n+ static Pool POOL16C_00[4];\n+ static Pool POOL16C_0[2];\n+ static Pool P16C[2];\n+ static Pool P16_A1[2];\n+ static Pool P_ADDIU_RS5_[2];\n+ static Pool P16_A2[2];\n+ static Pool P16_ADDU[2];\n+ static Pool P16_JRC[2];\n+ static Pool P16_BR1[2];\n+ static Pool P16_BR[2];\n+ static Pool P16_SR[2];\n+ static Pool P16_4X4[4];\n+ static Pool P16_LB[4];\n+ static Pool P16_LH[4];\n+ static Pool P16[32];\n+ static Pool MAJOR[2];\n+\n+\n+};\n+\n+#endif\ndiff --git a/include/disas/bfd.h b/include/disas/bfd.h\nindex 1f69a6e..4c41e9c 100644\n--- a/include/disas/bfd.h\n+++ b/include/disas/bfd.h\n@@ -387,6 +387,7 @@ typedef int (*disassembler_ftype) (bfd_vma, disassemble_info *);\n int print_insn_tci(bfd_vma, disassemble_info*);\n int print_insn_big_mips (bfd_vma, disassemble_info*);\n int print_insn_little_mips (bfd_vma, disassemble_info*);\n+int print_insn_micromips (bfd_vma, disassemble_info*);\n int print_insn_i386 (bfd_vma, disassemble_info*);\n int print_insn_m68k (bfd_vma, disassemble_info*);\n int print_insn_z8001 (bfd_vma, disassemble_info*);\ndiff --git a/target/mips/cpu.c b/target/mips/cpu.c\nindex 497706b..f309eb9 100644\n--- a/target/mips/cpu.c\n+++ b/target/mips/cpu.c\n@@ -113,11 +113,19 @@ static void mips_cpu_reset(CPUState *s)\n }\n \n static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) {\n+ MIPSCPU *cpu = MIPS_CPU(s);\n+ CPUMIPSState *env = &cpu->env;\n+\n+ if (!(env->hflags & MIPS_HFLAG_M16) &&\n+ !(env->insn_flags & ISA_NANOMIPS32)) {\n #ifdef TARGET_WORDS_BIGENDIAN\n- info->print_insn = print_insn_big_mips;\n+ info->print_insn = print_insn_big_mips;\n #else\n- info->print_insn = print_insn_little_mips;\n+ info->print_insn = print_insn_little_mips;\n #endif\n+ } else {\n+ info->print_insn = print_insn_micromips;\n+ }\n }\n \n static void mips_cpu_realizefn(DeviceState *dev, Error **errp)\n", "prefixes": [ "v7", "45/80" ] }