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GET /api/patches/954072/?format=api
{ "id": 954072, "url": "http://patchwork.ozlabs.org/api/patches/954072/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-40-git-send-email-aleksandar.markovic@rt-rk.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1533574847-19294-40-git-send-email-aleksandar.markovic@rt-rk.com>", "list_archive_url": null, "date": "2018-08-06T17:00:06", "name": "[v7,39/80] target/mips: Add emulation of DSP ASE for nanoMIPS - part 1", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ad4f55e33dadfc20e36529123c0d74ff9ac87a47", "submitter": { "id": 68635, "url": "http://patchwork.ozlabs.org/api/people/68635/?format=api", "name": "Aleksandar Markovic", "email": "aleksandar.markovic@rt-rk.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-40-git-send-email-aleksandar.markovic@rt-rk.com/mbox/", "series": [ { "id": 59520, "url": "http://patchwork.ozlabs.org/api/series/59520/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=59520", "date": "2018-08-06T16:59:27", "name": "Add nanoMIPS support to QEMU", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/59520/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/954072/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/954072/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=rt-rk.com" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 41klZT4MrWz9rvt\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 7 Aug 2018 03:51:29 +1000 (AEST)", "from localhost ([::1]:35443 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1fmjfD-0005bL-6B\n\tfor incoming@patchwork.ozlabs.org; Mon, 06 Aug 2018 13:51:27 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:33950)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmj7X-0007R7-Qt\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:16:44 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmj7U-0008Mz-G1\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:16:38 -0400", "from mx2.rt-rk.com ([89.216.37.149]:54371 helo=mail.rt-rk.com)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <aleksandar.markovic@rt-rk.com>)\n\tid 1fmj7T-0008Lh-VC\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:16:36 -0400", "from localhost (localhost [127.0.0.1])\n\tby mail.rt-rk.com (Postfix) with ESMTP id BACBE1A20AF;\n\tMon, 6 Aug 2018 19:16:34 +0200 (CEST)", "from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local\n\t[10.10.13.43])\n\tby mail.rt-rk.com (Postfix) with ESMTPSA id 924961A2036;\n\tMon, 6 Aug 2018 19:16:34 +0200 (CEST)" ], "X-Virus-Scanned": "amavisd-new at rt-rk.com", "From": "Aleksandar Markovic <aleksandar.markovic@rt-rk.com>", "To": "qemu-devel@nongnu.org", "Date": "Mon, 6 Aug 2018 19:00:06 +0200", "Message-Id": "<1533574847-19294-40-git-send-email-aleksandar.markovic@rt-rk.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "References": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 3.x [fuzzy]", "X-Received-From": "89.216.37.149", "Subject": "[Qemu-devel] [PATCH v7 39/80] target/mips: Add emulation of DSP ASE\n\tfor nanoMIPS - part 1", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, thuth@redhat.com, pburton@wavecomp.com,\n\tsmarkovic@wavecomp.com, riku.voipio@iki.fi,\n\trichard.henderson@linaro.org, laurent@vivier.eu,\n\tarmbru@redhat.com, arikalo@wavecomp.com,\n\tphilippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com,\n\tpjovanovic@wavecomp.com, aurelien@aurel32.net", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Stefan Markovic <smarkovic@wavecomp.com>\n\nAdd emulation of DSP ASE instructions for nanoMIPS - part 1.\n\nSigned-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>\nSigned-off-by: Stefan Markovic <smarkovic@wavecomp.com>\n---\n target/mips/translate.c | 619 ++++++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 619 insertions(+)", "diff": "diff --git a/target/mips/translate.c b/target/mips/translate.c\nindex 441431d..78b1c72 100644\n--- a/target/mips/translate.c\n+++ b/target/mips/translate.c\n@@ -17661,6 +17661,619 @@ static void gen_pool32f_nanomips_insn(DisasContext *ctx)\n }\n }\n \n+static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,\n+ int rd, int rs, int rt)\n+{\n+ int ret = rd;\n+\n+ TCGv t0;\n+ TCGv v1_t;\n+ TCGv v2_t;\n+\n+ t0 = tcg_temp_new();\n+ v1_t = tcg_temp_new();\n+ v2_t = tcg_temp_new();\n+\n+ gen_load_gpr(v1_t, rs);\n+ gen_load_gpr(v2_t, rt);\n+\n+ switch (opc) {\n+ case NM_CMP_EQ_PH:\n+ check_dsp(ctx);\n+ gen_helper_cmp_eq_ph(v1_t, v2_t, cpu_env);\n+ break;\n+ case NM_CMP_LT_PH:\n+ check_dsp(ctx);\n+ gen_helper_cmp_lt_ph(v1_t, v2_t, cpu_env);\n+ break;\n+ case NM_CMP_LE_PH:\n+ check_dsp(ctx);\n+ gen_helper_cmp_le_ph(v1_t, v2_t, cpu_env);\n+ break;\n+ case NM_CMPU_EQ_QB:\n+ check_dsp(ctx);\n+ gen_helper_cmpu_eq_qb(v1_t, v2_t, cpu_env);\n+ break;\n+ case NM_CMPU_LT_QB:\n+ check_dsp(ctx);\n+ gen_helper_cmpu_lt_qb(v1_t, v2_t, cpu_env);\n+ break;\n+ case NM_CMPU_LE_QB:\n+ check_dsp(ctx);\n+ gen_helper_cmpu_le_qb(v1_t, v2_t, cpu_env);\n+ break;\n+ case NM_CMPGU_EQ_QB:\n+ check_dsp(ctx);\n+ gen_helper_cmpgu_eq_qb(v1_t, v1_t, v2_t);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case NM_CMPGU_LT_QB:\n+ check_dsp(ctx);\n+ gen_helper_cmpgu_lt_qb(v1_t, v1_t, v2_t);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case NM_CMPGU_LE_QB:\n+ check_dsp(ctx);\n+ gen_helper_cmpgu_le_qb(v1_t, v1_t, v2_t);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case NM_CMPGDU_EQ_QB:\n+ check_dspr2(ctx);\n+ gen_helper_cmpgu_eq_qb(v1_t, v1_t, v2_t);\n+ tcg_gen_deposit_tl(cpu_dspctrl, cpu_dspctrl, v1_t, 24, 4);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case NM_CMPGDU_LT_QB:\n+ check_dspr2(ctx);\n+ gen_helper_cmpgu_lt_qb(v1_t, v1_t, v2_t);\n+ tcg_gen_deposit_tl(cpu_dspctrl, cpu_dspctrl, v1_t, 24, 4);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case NM_CMPGDU_LE_QB:\n+ check_dspr2(ctx);\n+ gen_helper_cmpgu_le_qb(v1_t, v1_t, v2_t);\n+ tcg_gen_deposit_tl(cpu_dspctrl, cpu_dspctrl, v1_t, 24, 4);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case NM_PACKRL_PH:\n+ check_dsp(ctx);\n+ gen_helper_packrl_ph(v1_t, v1_t, v2_t);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case NM_PICK_QB:\n+ check_dsp(ctx);\n+ gen_helper_pick_qb(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case NM_PICK_PH:\n+ check_dsp(ctx);\n+ gen_helper_pick_ph(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case NM_ADDQ_S_W:\n+ check_dsp(ctx);\n+ gen_helper_addq_s_w(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case NM_SUBQ_S_W:\n+ check_dsp(ctx);\n+ gen_helper_subq_s_w(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case NM_ADDSC:\n+ check_dsp(ctx);\n+ gen_helper_addsc(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case NM_ADDWC:\n+ check_dsp(ctx);\n+ gen_helper_addwc(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case NM_ADDQ_S_PH:\n+ check_dsp(ctx);\n+ switch (extract32(ctx->opcode, 10, 1)) {\n+ case 0:\n+ /* ADDQ_PH */\n+ gen_helper_addq_ph(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case 1:\n+ /* ADDQ_S_PH */\n+ gen_helper_addq_s_ph(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ case NM_ADDQH_R_PH:\n+ check_dspr2(ctx);\n+ switch (extract32(ctx->opcode, 10, 1)) {\n+ case 0:\n+ /* ADDQH_PH */\n+ gen_helper_addqh_ph(v1_t, v1_t, v2_t);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case 1:\n+ /* ADDQH_R_PH */\n+ gen_helper_addqh_r_ph(v1_t, v1_t, v2_t);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ case NM_ADDQH_R_W:\n+ check_dspr2(ctx);\n+ switch (extract32(ctx->opcode, 10, 1)) {\n+ case 0:\n+ /* ADDQH_W */\n+ gen_helper_addqh_w(v1_t, v1_t, v2_t);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case 1:\n+ /* ADDQH_R_W */\n+ gen_helper_addqh_r_w(v1_t, v1_t, v2_t);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ case NM_ADDU_S_QB:\n+ check_dsp(ctx);\n+ switch (extract32(ctx->opcode, 10, 1)) {\n+ case 0:\n+ /* ADDU_QB */\n+ gen_helper_addu_qb(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case 1:\n+ /* ADDU_S_QB */\n+ gen_helper_addu_s_qb(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ case NM_ADDU_S_PH:\n+ check_dspr2(ctx);\n+ switch (extract32(ctx->opcode, 10, 1)) {\n+ case 0:\n+ /* ADDU_PH */\n+ gen_helper_addu_ph(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case 1:\n+ /* ADDU_S_PH */\n+ gen_helper_addu_s_ph(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ case NM_ADDUH_R_QB:\n+ check_dspr2(ctx);\n+ switch (extract32(ctx->opcode, 10, 1)) {\n+ case 0:\n+ /* ADDUH_QB */\n+ gen_helper_adduh_qb(v1_t, v1_t, v2_t);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case 1:\n+ /* ADDUH_R_QB */\n+ gen_helper_adduh_r_qb(v1_t, v1_t, v2_t);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ case NM_SHRAV_R_PH:\n+ check_dsp(ctx);\n+ switch (extract32(ctx->opcode, 10, 1)) {\n+ case 0:\n+ /* SHRAV_PH */\n+ gen_helper_shra_ph(v1_t, v1_t, v2_t);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case 1:\n+ /* SHRAV_R_PH */\n+ gen_helper_shra_r_ph(v1_t, v1_t, v2_t);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ case NM_SHRAV_R_QB:\n+ check_dspr2(ctx);\n+ switch (extract32(ctx->opcode, 10, 1)) {\n+ case 0:\n+ /* SHRAV_QB */\n+ gen_helper_shra_qb(v1_t, v1_t, v2_t);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case 1:\n+ /* SHRAV_R_QB */\n+ gen_helper_shra_r_qb(v1_t, v1_t, v2_t);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ case NM_SUBQ_S_PH:\n+ check_dsp(ctx);\n+ switch (extract32(ctx->opcode, 10, 1)) {\n+ case 0:\n+ /* SUBQ_PH */\n+ gen_helper_subq_ph(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case 1:\n+ /* SUBQ_S_PH */\n+ gen_helper_subq_s_ph(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ case NM_SUBQH_R_PH:\n+ check_dspr2(ctx);\n+ switch (extract32(ctx->opcode, 10, 1)) {\n+ case 0:\n+ /* SUBQH_PH */\n+ gen_helper_subqh_ph(v1_t, v1_t, v2_t);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case 1:\n+ /* SUBQH_R_PH */\n+ gen_helper_subqh_r_ph(v1_t, v1_t, v2_t);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ case NM_SUBQH_R_W:\n+ check_dspr2(ctx);\n+ switch (extract32(ctx->opcode, 10, 1)) {\n+ case 0:\n+ /* SUBQH_W */\n+ gen_helper_subqh_w(v1_t, v1_t, v2_t);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case 1:\n+ /* SUBQH_R_W */\n+ gen_helper_subqh_r_w(v1_t, v1_t, v2_t);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ case NM_SUBU_S_QB:\n+ check_dsp(ctx);\n+ switch (extract32(ctx->opcode, 10, 1)) {\n+ case 0:\n+ /* SUBU_QB */\n+ gen_helper_subu_qb(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case 1:\n+ /* SUBU_S_QB */\n+ gen_helper_subu_s_qb(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ case NM_SUBU_S_PH:\n+ check_dspr2(ctx);\n+ switch (extract32(ctx->opcode, 10, 1)) {\n+ case 0:\n+ /* SUBU_PH */\n+ gen_helper_subu_ph(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case 1:\n+ /* SUBU_S_PH */\n+ gen_helper_subu_s_ph(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ case NM_SUBUH_R_QB:\n+ check_dspr2(ctx);\n+ switch (extract32(ctx->opcode, 10, 1)) {\n+ case 0:\n+ /* SUBUH_QB */\n+ gen_helper_subuh_qb(v1_t, v1_t, v2_t);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case 1:\n+ /* SUBUH_R_QB */\n+ gen_helper_subuh_r_qb(v1_t, v1_t, v2_t);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ case NM_SHLLV_S_PH:\n+ check_dsp(ctx);\n+ switch (extract32(ctx->opcode, 10, 1)) {\n+ case 0:\n+ /* SHLLV_PH */\n+ gen_helper_shll_ph(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case 1:\n+ /* SHLLV_S_PH */\n+ gen_helper_shll_s_ph(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ case NM_PRECR_SRA_R_PH_W:\n+ check_dspr2(ctx);\n+ switch (extract32(ctx->opcode, 10, 1)) {\n+ case 0:\n+ /* PRECR_SRA_PH_W */\n+ {\n+ TCGv_i32 sa_t = tcg_const_i32(rd);\n+ gen_helper_precr_sra_ph_w(v1_t, sa_t, v1_t,\n+ cpu_gpr[rt]);\n+ gen_store_gpr(v1_t, rt);\n+ tcg_temp_free_i32(sa_t);\n+ }\n+ break;\n+ case 1:\n+ /* PRECR_SRA_R_PH_W */\n+ {\n+ TCGv_i32 sa_t = tcg_const_i32(rd);\n+ gen_helper_precr_sra_r_ph_w(v1_t, sa_t, v1_t,\n+ cpu_gpr[rt]);\n+ gen_store_gpr(v1_t, rt);\n+ tcg_temp_free_i32(sa_t);\n+ }\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ case NM_MULEU_S_PH_QBL:\n+ check_dsp(ctx);\n+ gen_helper_muleu_s_ph_qbl(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case NM_MULEU_S_PH_QBR:\n+ check_dsp(ctx);\n+ gen_helper_muleu_s_ph_qbr(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case NM_MULQ_RS_PH:\n+ check_dsp(ctx);\n+ gen_helper_mulq_rs_ph(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case NM_MULQ_S_PH:\n+ check_dspr2(ctx);\n+ gen_helper_mulq_s_ph(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case NM_MULQ_RS_W:\n+ check_dspr2(ctx);\n+ gen_helper_mulq_rs_w(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case NM_MULQ_S_W:\n+ check_dspr2(ctx);\n+ gen_helper_mulq_s_w(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case NM_APPEND:\n+ gen_load_gpr(t0, rs);\n+\n+ if (rd != 0) {\n+ tcg_gen_deposit_tl(cpu_gpr[rt], t0, cpu_gpr[rt], rd, 32 - rd);\n+ }\n+ tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);\n+ break;\n+ case NM_MODSUB:\n+ check_dsp(ctx);\n+ gen_helper_modsub(v1_t, v1_t, v2_t);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case NM_SHRAV_R_W:\n+ check_dsp(ctx);\n+ gen_helper_shra_r_w(v1_t, v1_t, v2_t);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case NM_SHRLV_PH:\n+ check_dspr2(ctx);\n+ gen_helper_shrl_ph(v1_t, v1_t, v2_t);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case NM_SHRLV_QB:\n+ check_dsp(ctx);\n+ gen_helper_shrl_qb(v1_t, v1_t, v2_t);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case NM_SHLLV_QB:\n+ check_dsp(ctx);\n+ gen_helper_shll_qb(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case NM_SHLLV_S_W:\n+ check_dsp(ctx);\n+ gen_helper_shll_s_w(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case NM_SHILO:\n+ {\n+ TCGv tv0;\n+ TCGv tv1;\n+ tv0 = tcg_temp_new();\n+ tv1 = tcg_temp_new();\n+\n+ int16_t imm = extract32(ctx->opcode, 16, 7);\n+\n+ check_dsp(ctx);\n+ tcg_gen_movi_tl(tv0, rd >> 3);\n+ tcg_gen_movi_tl(tv1, imm);\n+\n+ gen_helper_shilo(tv0, tv1, cpu_env);\n+ }\n+ break;\n+ case NM_MULEQ_S_W_PHL:\n+ check_dsp(ctx);\n+ gen_helper_muleq_s_w_phl(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case NM_MULEQ_S_W_PHR:\n+ check_dsp(ctx);\n+ gen_helper_muleq_s_w_phr(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case NM_MUL_S_PH:\n+ check_dspr2(ctx);\n+ switch (extract32(ctx->opcode, 10, 1)) {\n+ case 0:\n+ /* MUL_PH */\n+ gen_helper_mul_ph(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case 1:\n+ /* MUL_S_PH */\n+ gen_helper_mul_s_ph(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ case NM_PRECR_QB_PH:\n+ check_dspr2(ctx);\n+ gen_helper_precr_qb_ph(v1_t, v1_t, v2_t);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case NM_PRECRQ_QB_PH:\n+ check_dsp(ctx);\n+ gen_helper_precrq_qb_ph(v1_t, v1_t, v2_t);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case NM_PRECRQ_PH_W:\n+ check_dsp(ctx);\n+ gen_helper_precrq_ph_w(v1_t, v1_t, v2_t);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case NM_PRECRQ_RS_PH_W:\n+ check_dsp(ctx);\n+ gen_helper_precrq_rs_ph_w(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case NM_PRECRQU_S_QB_PH:\n+ check_dsp(ctx);\n+ gen_helper_precrqu_s_qb_ph(v1_t, v1_t, v2_t, cpu_env);\n+ gen_store_gpr(v1_t, ret);\n+ break;\n+ case NM_SHRA_R_W:\n+ tcg_gen_movi_tl(t0, rd);\n+ check_dsp(ctx);\n+ gen_helper_shra_r_w(v1_t, t0, v1_t);\n+ gen_store_gpr(v1_t, rt);\n+ break;\n+ case NM_SHRA_R_PH:\n+ check_dsp(ctx);\n+ tcg_gen_movi_tl(t0, rd >> 1);\n+ switch (extract32(ctx->opcode, 10, 1)) {\n+ case 0:\n+ /* SHRA_PH */\n+ gen_helper_shra_ph(v1_t, t0, v1_t);\n+ break;\n+ gen_store_gpr(v1_t, rt);\n+ case 1:\n+ /* SHRA_R_PH */\n+ gen_helper_shra_r_ph(v1_t, t0, v1_t);\n+ gen_store_gpr(v1_t, rt);\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ case NM_SHLL_S_PH:\n+ check_dsp(ctx);\n+ tcg_gen_movi_tl(t0, rd >> 1);\n+ switch (extract32(ctx->opcode, 10, 2)) {\n+ case 0:\n+ /* SHLL_PH */\n+ gen_helper_shll_ph(v1_t, t0, v1_t, cpu_env);\n+ gen_store_gpr(v1_t, rt);\n+ break;\n+ case 2:\n+ /* SHLL_S_PH */\n+ gen_helper_shll_s_ph(v1_t, t0, v1_t, cpu_env);\n+ gen_store_gpr(v1_t, rt);\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ case NM_SHLL_S_W:\n+ check_dsp(ctx);\n+ tcg_gen_movi_tl(t0, rd);\n+ gen_helper_shll_s_w(v1_t, t0, v1_t, cpu_env);\n+ gen_store_gpr(v1_t, rt);\n+ break;\n+ case NM_REPL_PH:\n+ check_dsp(ctx);\n+ {\n+ int16_t imm;\n+ imm = extract32(ctx->opcode, 11, 11);\n+ imm = (int16_t)(imm << 6) >> 6;\n+ if (rt != 0) {\n+ tcg_gen_movi_tl(cpu_gpr[rt], \\\n+ (target_long)((int32_t)imm << 16 | \\\n+ (uint16_t)imm));\n+ }\n+ }\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+}\n+\n static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)\n {\n uint16_t insn;\n@@ -17731,6 +18344,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)\n case NM_POOL32A0:\n gen_pool32a0_nanomips_insn(env, ctx);\n break;\n+ case NM_POOL32A5:\n+ {\n+ int32_t op1 = extract32(ctx->opcode, 3, 7);\n+ gen_pool32a5_nanomips_insn(ctx, op1, rd, rs, rt);\n+ }\n+ break;\n case NM_POOL32A7:\n switch (extract32(ctx->opcode, 3, 3)) {\n case NM_P_LSX:\n", "prefixes": [ "v7", "39/80" ] }